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HHHHEHLHE@HE@HE@DHE@DHE@HEHEHHAPWVEHH=cH UHH@H}HuHUHEH@@HEHEHEHEЋ@ HHHHEHLHE@DHE@HE@HE@DHE@DHE@HEHEHAQAPWVEEHH=wH HEЋ@HEH0HEE?EEHEAHH=o谧HEЋ@t_HEH8HEEEEff%EHEAAHH=AJUHH0H}HuHUHEH@@HEHEHEHE@ HHHHEHLHE@HE@HE@DHE@DHE@HEHEHHAPWVEHH=舦H UHH0H}HuHUHEH@@HEHEHEHE@ HHHHEHLHE@HE@HE@DHE@DHE@HEHEHHAPWVEHH=ǥH UHH@H}HuHUHEH@@HEHEHEHEЋ@ HHHHEHLHE@HE@HE@DHE@DHE@HEHEHHAPWVEHH=ESH HEЋ@tqHEH0HEEf%?ЋEHEщHH=?S踤HEH8HEE?HEHH==S臤UHH0H}HuHUHEH@@HEHEHEHE@ HHHHEHH8HE@HE@DHE@DHE@HEHEHWVHH=ߣHUHSHHH}HuHUHEH@@HEHEHEHE@ HHHHEHLHE@DHE@DHE@HE@HE@HE@DHE@HEHEHHARAQAPWVAEHH=dH0HE@tKHEH0HEEEEEHEAAHH=s蔢H]UHH0H}HuHUHEH@@HEHEHEHE@ HHHHEHLHE@DHE@HE@HE@DHE@DHE@HEHEHAQAPWVEEHH=U辡H UHH0H}HuHUHEH@@HEHEHEHE@ HHHHEHLHE@HE@HE@DHE@DHE@HEHEHHAPWVEHH= H UHH0H}HuHUHEH@@HEHEHEHE@ HHHHEHLHE@HE@HE@DHE@DHE@HEHEHHAPWVEHH=39HE@ UHcHcHHHHHiѨHH-4HЋuEE;E|HE@ UHcHcHHHHHiѨHH-4HЋЉHEHE@EHEUHcHHH‹EEHHUMHcHHHHHEPHEPUHHpH}HudH%(HE1EEEEEHEƀ(HEHEEHEH HEUHcHHHЋHcHHHHHHEHE@,GHE@(HEH HEHP0HcHHHHHiѨHH#,4HЋEHEH HEHP0HcHHHHHiѨHH+4HHHE}!H}tE̺Љ‹E ЉE(}~"H}tẼ EEEtHE@(u jHEUHcHHHHHHEHEH@0HHH HcH HH}EЃ ЈEH}EЃ ЈEЃMH}EЃ ЈEH}EЃ ЈEЃMH}t|EڃEEۃEfH}tbEڃEEڃELH}v KH}t7EڃEHEEڃ ЈEEHE@9EQEuDHE@tEЃEEЃEHE@tEЃEEЃEЃ}u$HUHEHHgEă}tEEEЃ ЈEЋEEf% fEЋE ‹E% ЉEHE@ HHiШH(4??EӃ ЈEEكEHE@ HHiШH(4Eك ЈEEڃEHE@ %u!E  ‹E% ЉEHE@ HHiШHH(4HHUH(HH |HEHEHEH HEUHcHHHЋHcHHHHHHEHE@,HE@(uuHEUHcHHHЋEHE@ UHcHcHHHHHiѨHH'4HHHUH(HH 蜑EHE@9E!EH HMH(AHH JEH HMH(AHHn EۃH HMH(AHH6 אEHS HMH(AHH 蜐EH2 HMH(AHH dHE@HUHEH(HUHEH0HEHHudH34%(tzUHH H}KE}tE@H;@t*Hl;E}t }t}uUHH H}5KE}tE@H!;@t*H ;E}t}t }tUHH}HEHEHE@t]UHH}uHEHEHE@9E|E]UHH}uHEHE}xHE@9E}]UHH(H}uUHMHEH@@HEEEE;EEEEHHiШHEH EHcHHHHHH(HHEHEHHiШHEH EHcHHHHHH0HHEHPHEH@EHHiШHEH EHcHHHHHH8HEHP HE@(EHHiШHEH EHcHHHHHH<HE؉уP8 ʈP8E+EEEHcHHHHHH.o4HHEHEHcHHHHHHo4HHEHPHEH@EHcHEHP EHcHHHHHHn4HE؉P(HEP8P8HE@,EHcHEHP0HEH@@UHH(H}uHUHEH@@HEHEHEEHHiШHEHHHEHEHHiШHEHHPHEHPEHHiШHEHЋ@UHcHiʨHUHʋR ЉHEHP HEH@HE؋UP0HEPHE؉P(EHE؉P4HE؋@4HE؉P4UHH@H}HuHEHEH0!4HEHEH@HEEEEHHiШHEHHHuS}~EHHiHXHEHHH HUHRMH}IH5} #EEHHiШHEHH@Hu %d) for %s %s::%s%s (%s.%d): activated %s ,%s (%s.%d): trying %s %s (%s.%d): %d PMU blacklisted, skipping initialization %s (%s.%d): %s PMU not exported by OS successfailurePMU forced to %s (%s) : %s %s (%s.%d): %d PMU detected out of %d supported %s (%s.%d): OS layer %s activated %s (%s.%d): default OS layer: %s :.%s (%s.%d): cannot mix raw umask with umask %s (%s.%d): PMU %s does not support RAW umasks RAW_UMASK%s (%s.%d): raw umask (%s) is not a number %s (%s.%d): cannot find attribute %s %s (%s.%d): too many attributes %s (%s.%d): %d %d %d %d %d %s , ::%s (%s.%d): %d %d %d %s %s (%s.%d): %d %d RAW_UMASK (0x%x) not supportedinvalid parameterspfmlib not initializedevent not foundinvalid combination of model specific featuresinvalid or missing unit maskout of memoryinvalid event attributeinvalid event attribute valueattribute value already settoo many parametersparameter is too smallunknown error codeinvalid pattrs for event %d event %d duplicate pattrs %s %s (%s.%d): %s %#lx %s::%s:%scannot encode event %s : %s pmu: %s :: initialization failed pmu id: %d :: no name pmu: %s :: no description pmu: %s :: invalid PMU id pmu: %s :: max encoding too high pmu: %s :: no events pmu: %s :: missing pmu_detect callback pmu: %s :: missing get_event_first callback pmu: %s :: missing get_event_next callback pmu: %s :: missing get_event_info callback pmu: %s :: missing get_event_attr_info callback pmu: %s :: no os event encoding callback pmu: %s :: max_encoding is zero pmu: %s :: duplicate name pmu: %s :: duplicate id %s (%s.%d): PMU %s does not support PFM_OS_NONE pfmlib_check_structpfmlib_pmu_sanity_checkspfmlib_pmu_activatepfmlib_init_pmuspfmlib_init_ospfmlib_parse_event_attrpfmlib_build_event_pattrspfmlib_parse_eventpfmlib_validate_encodingpfmlib_raw_pmu_encodePERF_COUNT_HW_CPU_CYCLESCYCLESCPU-CYCLESPERF_COUNT_HW_INSTRUCTIONSINSTRUCTIONSPERF_COUNT_HW_CACHE_REFERENCESCACHE-REFERENCESPERF_COUNT_HW_CACHE_MISSESCACHE-MISSESPERF_COUNT_HW_BRANCH_INSTRUCTIONSBRANCH-INSTRUCTIONSBRANCHESPERF_COUNT_HW_BRANCH_MISSESBRANCH-MISSESPERF_COUNT_HW_BUS_CYCLESBUS-CYCLESPERF_COUNT_HW_STALLED_CYCLES_FRONTENDSTALLED-CYCLES-FRONTENDIDLE-CYCLES-FRONTENDPERF_COUNT_HW_STALLED_CYCLES_BACKENDSTALLED-CYCLES-BACKENDIDLE-CYCLES-BACKENDPERF_COUNT_HW_REF_CPU_CYCLESREF-CYCLESPERF_COUNT_SW_CPU_CLOCKCPU-CLOCKPERF_COUNT_SW_TASK_CLOCKTASK-CLOCKPERF_COUNT_SW_PAGE_FAULTSPAGE-FAULTSFAULTSPERF_COUNT_SW_CONTEXT_SWITCHESCONTEXT-SWITCHESCSPERF_COUNT_SW_CPU_MIGRATIONSCPU-MIGRATIONSMIGRATIONSPERF_COUNT_SW_PAGE_FAULTS_MINMINOR-FAULTSPERF_COUNT_SW_PAGE_FAULTS_MAJMAJOR-FAULTSPERF_COUNT_HW_CACHE_L1DL1 data cacheREADread accessWRITEwrite accessPREFETCHprefetch accessACCESShit accessMISSmiss accessL1-DCACHE-LOADSL1 cache load accessesPERF_COUNT_HW_CACHE_L1D:READ:ACCESSL1-DCACHE-LOAD-MISSESL1 cache load missesPERF_COUNT_HW_CACHE_L1D:READ:MISSL1-DCACHE-STORESL1 cache store accessesPERF_COUNT_HW_CACHE_L1D:WRITE:ACCESSL1-DCACHE-STORE-MISSESL1 cache store missesPERF_COUNT_HW_CACHE_L1D:WRITE:MISSL1-DCACHE-PREFETCHESL1 cache prefetch accessesPERF_COUNT_HW_CACHE_L1D:PREFETCH:ACCESSL1-DCACHE-PREFETCH-MISSESL1 cache prefetch missesPERF_COUNT_HW_CACHE_L1D:PREFETCH:MISSPERF_COUNT_HW_CACHE_L1IL1 instruction cacheL1-ICACHE-LOADSL1I cache load accessesPERF_COUNT_HW_CACHE_L1I:READ:ACCESSL1-ICACHE-LOAD-MISSESL1I cache load missesPERF_COUNT_HW_CACHE_L1I:READ:MISSL1-ICACHE-PREFETCHESL1I cache prefetch accessesPERF_COUNT_HW_CACHE_L1I:PREFETCH:ACCESSL1-ICACHE-PREFETCH-MISSESL1I cache prefetch missesPERF_COUNT_HW_CACHE_L1I:PREFETCH:MISSPERF_COUNT_HW_CACHE_LLLast level cacheLLC-LOADSLast level cache load accessesPERF_COUNT_HW_CACHE_LL:READ:ACCESSLLC-LOAD-MISSESLast level cache load missesPERF_COUNT_HW_CACHE_LL:READ:MISSLLC-STORESLast level cache store accessesPERF_COUNT_HW_CACHE_LL:WRITE:ACCESSLLC-STORE-MISSESLast level cache store missesPERF_COUNT_HW_CACHE_LL:WRITE:MISSLLC-PREFETCHESLast level cache prefetch accessesPERF_COUNT_HW_CACHE_LL:PREFETCH:ACCESSLLC-PREFETCH-MISSESLast level cache prefetch missesPERF_COUNT_HW_CACHE_LL:PREFETCH:MISSPERF_COUNT_HW_CACHE_DTLBData Translation Lookaside BufferDTLB-LOADSData TLB load accessesPERF_COUNT_HW_CACHE_DTLB:READ:ACCESSDTLB-LOAD-MISSESData TLB load missesPERF_COUNT_HW_CACHE_DTLB:READ:MISSDTLB-STORESData TLB store accessesPERF_COUNT_HW_CACHE_DTLB:WRITE:ACCESSDTLB-STORE-MISSESData TLB store missesPERF_COUNT_HW_CACHE_DTLB:WRITE:MISSDTLB-PREFETCHESData TLB prefetch accessesPERF_COUNT_HW_CACHE_DTLB:PREFETCH:ACCESSDTLB-PREFETCH-MISSESData TLB prefetch missesPERF_COUNT_HW_CACHE_DTLB:PREFETCH:MISSPERF_COUNT_HW_CACHE_ITLBInstruction Translation Lookaside BufferITLB-LOADSInstruction TLB load accessesPERF_COUNT_HW_CACHE_ITLB:READ:ACCESSITLB-LOAD-MISSESInstruction TLB load missesPERF_COUNT_HW_CACHE_ITLB:READ:MISSPERF_COUNT_HW_CACHE_BPUBranch Prediction UnitBRANCH-LOADSBranch load accessesPERF_COUNT_HW_CACHE_BPU:READ:ACCESSBRANCH-LOAD-MISSESBranch load missesPERF_COUNT_HW_CACHE_BPU:READ:MISSPERF_COUNT_HW_CACHE_NODENode memory accessNODE-LOADSNode load accessesPERF_COUNT_HW_CACHE_NODE:READ:ACCESSNODE-LOAD-MISSESNode load missesPERF_COUNT_HW_CACHE_NODE:READ:MISSNODE-STORESNode store accessesPERF_COUNT_HW_CACHE_NODE:WRITE:ACCESSNODE-STORE-MISSESNode store missesPERF_COUNT_HW_CACHE_NODE:WRITE:MISSNODE-PREFETCHESNode prefetch accessesPERF_COUNT_HW_CACHE_NODE:PREFETCH:ACCESSNODE-PREFETCH-MISSESNode prefetch missesPERF_COUNT_HW_CACHE_NODE:PREFETCH:MISSpfmlib_perf_event_pmu.c%s (%s.%d): no core CPU PMU, going with default %s (%s.%d): guessing plm from %s PMU plm=0x%x r/proc/mountsdebugfs...%s/%stracepoint%s/%s/id%s (%s.%d): idpath=%s:%s id=%lu /proc/sys/kernel/perf_event_paranoid/proc/sys/kernel/perf_counter_paranoid%s (%s.%d): added default %s for group %d %s (%s.%d): no default found for event %s unit mask group %d %s:%s%s (%s.%d): unsupported event type=%d ??pmu: %s event%d: :: no name (prev event was %s) pmu: %s event%d: %s :: no description pmu: %s event%d: %s :: invalid type pmu: %s event%d: %s :: numasks too big (<%d) pmu: %s event%d: %s :: overflow umask idx defined but not needed (<%d) pmu: %s event%d: %s :: ngrp cannot be zero pmu: %s event%d: %s :: ngrp must be zero pmu: %s event%d: %s umask%d :: no name pmu: %s event%d:%s umask%d: %s :: no description pmu: %s event%d: %s umask%d: %s :: invalid grpid %d (must be < %d) pmu: %s event%d: %s :: numasks (%d) invalid more events exists perf_events generic PMUperfgen_tracepoint_tablepfm_perf_pmu_supported_plmpfm_perf_add_defaultspfm_perf_get_encodingpfm_perf_get_perf_encodingumonitor at user levelkmonitor at kernel levelhmonitor at hypervisor levelmgmonitor guest executionmhmonitor host executionperiodsampling periodfreqsampling frequency (Hz)preciseprecise ipexclexclusive accesscpuCPU to programpinnedpin event to counterswarning: mismatch attr struct size user=%d libpfm=%zu pfmlib_perf_event.c%s (%s.%d): PMU %s does not support PFM_OS_NONE PERF[type=%x config=0x%lx config1=0x%lx excl=%d e_u=%d e_k=%d e_hv=%d e_host=%d e_gu=%d period=%lu freq=%d precise=%d pinned=%d] %s :%s=%lu:%s=%d9Yy Sr:_/proc/sys/kernel/perf_event_paranoidperf_eventperf_event extendedpfmlib_perf_event_encode/proc/sys/kernel/perf_event_paranoid/proc/sys/kernel/perf_counter_paranoidr%lxr0000perf_events raw event syntax: r[0-9a-fA-F]+%lxperf_events raw PMUperf_raw/sys/bus/event_source/devices/%s/typer%dpfmlib_intel_x86_perf_event.c%s (%s.%d): %s: unsupported count=%d %s (%s.%d): perf PMU %s, not supported by OS %s (%s.%d): PMU %s perf type=%d %s (%s.%d): perf_encoding: offcore=1 count=%d %s (%s.%d): perf_encoding: frontend_retired=1 count=%d %s (%s.%d): perf_encoding: ldlat count=%d /sys/devices/%spfm_intel_x86_get_perf_encoding/sys/bus/event_source/devices/%s/typer%dpfmlib_amd64_perf_event.c%s (%s.%d): %s: unsupported count=%d %s (%s.%d): amd64_get_perf_encoding: PMU type=%d pfm_amd64_get_perf_encoding/sys/bus/event_source/devices/%s/typer%dkmonitor at priv level 0umonitor at priv level 1, 2, 3eedge leveliinvertccounter-mask in range [0-255]hmonitor in hypervisorgmeasure in guest~[0x%lx event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d guest=%d host=%d] %s [0x%lx event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s AuthenticAMDpfmlib_amd64.c%s (%s.%d): added default for %s j=%d idx=%d %s (%s.%d): no default found for event %s unit mask group %d %s (%s.%d): event does not support unit mask combination within a group %s (%s.%d): raw umask is invalid %s:%s:0x%x:%s=%lu0oPbppmu: %s missing attr_desc pmu: %s supported_plm not set ??pmu: %s event%d: :: no name (prev event was %s) pmu: %s event%d: %s :: no description pmu: %s event%d: %s :: numasks but no umasks pmu: %s event%d: %s :: numasks=0 but umasks defined pmu: %s event%d: %s :: ngrp cannot be zero pmu: %s event%d: %s :: ngrp must be zero pmu: %s event%d: %s :: ngrp too big (max=%d) pmu: %s event%d: %s umask%d :: no name pmu: %s event%d:%s umask%d: %s :: no description pmu: %s event%d: %s umask%d: %s :: invalid grpid %d (must be < %d) pmu: %s event%d: %s :: more than one default unit mask with same code pmu: %s event%d: %s, only one umask but no default pmu: %s event%d: %s :: NCOMBO is unit mask only flag pmu: %s event%d: %s :: umask %s and %s have overlapping code bits amd64_add_defaultspfm_amd64_get_encodingPORT_0On port 0PORT_1On port 1PORT_2On port 2PORT_3On port 3PORT_4On port 4PORT_5On port 5ANYOn any portPORT_0:PORT_1:PORT_2:PORT_3:PORT_4:PORT_5STALoads blocked by a preceding store with unknown addressSTDLoads blocked by a preceding store with unknown dataOVERLAP_STORELoads that partially overlap an earlier store, or 4K equived with a previous storeUNTIL_RETIRELoads blocked until retirementL1DLoads blocked by the L1 data cacheORDERCycles while store is waiting for a preceding store to be globally observedSNOOPA store is blocked due to a conflict with an external or internal snoopNTAStreaming SIMD Extensions (SSE) Prefetch NTA instructions executedL1Streaming SIMD Extensions (SSE) PrefetchT0 instructions executedL2Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executedSTORESStreaming SIMD Extensions (SSE) Weakly-ordered store instructions executedAny memory access that missed the DTLBMISS_LDDTLB misses due to load operationsL0_MISS_LDL0 DTLB misses due to load operationsMISS_STDTLB misses due to store operationsRESETMemory disambiguation reset cyclesSUCCESSNumber of loads that were successfully disambiguatedCOUNTNumber of page-walks executedCYCLESDuration of page-walks in core cyclesFPDelayed bypass to FP operationSIMDDelayed bypass to SIMD operationLOADDelayed bypass to load operationSELFThis coreBOTH_CORESBoth coresAll inclusivePREFETCHHardware prefetch onlyEXCL_PREFETCHExclude hardware prefetchMESIAny cacheline accessM_STATE:E_STATE:S_STATE:I_STATEI_STATEInvalid cachelineS_STATEShared cachelineE_STATEExclusive cachelineM_STATEModified cachelineCORE_PCore cycles when core is not haltedBUSBus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratioNO_OTHERBus cycles when core is active and the other is haltedLOADSCache line split loads from the L1 data cacheCache line split stores to the L1 data cacheStreaming SIMD Extensions (SSE) Prefetch NTA instructions missing all cache levelsStreaming SIMD Extensions (SSE) PrefetchT0 instructions missing all cache levelsStreaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions missing all cache levelsREQUESTSL1 data cache prefetch requestsTHIS_AGENTThis agentALL_AGENTSAny agent on the busAny external snoop responseCLEANExternal snoop CLEAN responseHITExternal snoop HIT responseHITMExternal snoop HITM responseL1 data cache is snooped by other coreSHAREL1 data cache is snooped for sharing by other coreINVALIDATEL1 data cache is snooped for Invalidation by other coreSMALL_MISSITLB small page missesLARGE_MISSITLB large page missesFLUSHITLB flushesMISSESITLB missesFULLCycles during which the instruction queue is fullDECODEDInstructions decodedCISC_DECODEDCISC instructions decodedSYNCHESP register content synchronizationADDITIONSESP register automatic additionsMULSIMD packed multiply micro-ops executedSHIFTSIMD packed shift micro-ops executedPACKSIMD pack micro-ops executedUNPACKSIMD unpack micro-ops executedLOGICALSIMD packed logical micro-ops executedARITHMETICSIMD packed arithmetic micro-ops executedANY_PInstructions retired (Precise Event)Instructions retired, which contain a loadInstructions retired, which contain a storeOTHERInstructions retired, with no load or store operationFXCHFXCH instructions retiredRetired floating-point computational operations (Precise Event)LD_IND_BRFused load+op or load+indirect branch retiredSTD_STAFused store address + data retiredMACRO_FUSIONRetired instruction pairs fused into one micro-opNON_FUSEDNon-fused micro-ops retiredFUSEDFused micro-ops retiredMicro-ops retiredSMCSelf-Modifying Code detectedMEM_ORDERExecution pipeline restart due to memory ordering conflict or memory disambiguation mispredictionRetired branch instructionsPRED_NOT_TAKENRetired branch instructions that were predicted not-takenMISPRED_NOT_TAKENRetired branch instructions that were mispredicted not-takenPRED_TAKENRetired branch instructions that were predicted takenMISPRED_TAKENRetired branch instructions that were mispredicted takenTAKENRetired taken branch instructionsPACKED_SINGLERetired Streaming SIMD Extensions (SSE) packed-single instructionsSCALAR_SINGLERetired Streaming SIMD Extensions (SSE) scalar-single instructionsPACKED_DOUBLERetired Streaming SIMD Extensions 2 (SSE2) packed-double instructionsSCALAR_DOUBLERetired Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsVECTORRetired Streaming SIMD Extensions 2 (SSE2) vector integer instructionsRetired Streaming SIMD instructions (Precise Event)Retired computational Streaming SIMD Extensions (SSE) packed-single instructionsRetired computational Streaming SIMD Extensions (SSE) scalar-single instructionsRetired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructionsRetired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsL1D_MISSRetired loads that miss the L1 data cache (Precise Event)L1D_LINE_MISSL1 data cache line missed by retired loads (Precise Event)L2_MISSRetired loads that miss the L2 cache (Precise Event)L2_LINE_MISSL2 cache line missed by retired loads (Precise Event)DTLB_MISSRetired loads that miss the DTLB (Precise Event)TO_FPTransitions from MMX (TM) Instructions to Floating Point InstructionsTO_MMXTransitions from Floating Point to MMX (TM) InstructionsROB_READ_PORTROB read port stalls cyclesPARTIAL_CYCLESPartial register stall cyclesFLAGSFlag stall cyclesFPSWFPU status word stallAll RAT stall cyclesESSegment rename stalls - ES DSSegment rename stalls - DSFSSegment rename stalls - FSGSSegment rename stalls - GSAny (ES/DS/FS/GS) segment rename stallSegment renames - ESSegment renames - DSSegment renames - FSSegment renames - GSAny (ES/DS/FS/GS) segment renameROB_FULLCycles during which the ROB is fullRS_FULLCycles during which the RS is fullLD_STCycles during which the pipeline has exceeded load or store limit or waiting to commit all storesFPCWCycles stalled due to FPU control word writeBR_MISS_CLEARCycles stalled due to branch mispredictionResource related stallsUNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted)INSTRUCTION_RETIREDCount the number of instructions at retirementINSTRUCTIONS_RETIREDThis is an alias from INSTRUCTION_RETIREDUNHALTED_REFERENCE_CYCLESUnhalted reference cyclesLLC_REFERENCESCount each request originating equiv the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESILAST_LEVEL_CACHE_REFERENCESThis is an alias for LLC_REFERENCESLLC_MISSESCount each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATELAST_LEVEL_CACHE_MISSESThis is an alias for LLC_MISSESBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction.BR_INST_RETIRED:ANYMISPREDICTED_BRANCH_RETIREDCount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware.BR_INST_RETIRED_MISPREDRS_UOPS_DISPATCHED_CYCLESCycles micro-ops dispatched for executionRS_UOPS_DISPATCHEDNumber of micro-ops dispatched for executionRS_UOPS_DISPATCHED_NONENumber of of cycles in which no micro-ops is dispatched for executionRS_UOPS_DISPATCHED:i=1:c=1LOAD_BLOCKLoads blockedSB_DRAIN_CYCLESCycles while stores are blocked due to store buffer drainSTORE_BLOCKCycles while store is waitingSEGMENT_REG_LOADSNumber of segment register loadsSSE_PRE_EXECStreaming SIMD Extensions (SSE) Prefetch instructions executedDTLB_MISSESMemory accesses that missed the DTLBMEMORY_DISAMBIGUATIONMemory disambiguationPAGE_WALKSFP_COMP_OPS_EXEFloating point computational micro-ops executedFP_ASSISTFloating point assistsMultiply operations executedDIVDivide operations executedCYCLES_DIV_BUSYCycles the divider is busyIDLE_DURING_DIVCycles the divider is busy and all other execution units are idleDELAYED_BYPASSDelayed bypassL2_ADSCycles L2 address bus is in useL2_DBUS_BUSY_RDCycles the L2 transfers data to the coreL2_LINES_INL2 cache missesL2_M_LINES_INL2 cache line modificationsL2_LINES_OUTL2 cache lines evictedL2_M_LINES_OUTModified lines evicted from the L2 cacheL2_IFETCHL2 cacheable instruction fetch requestsL2_LDL2 cache readsL2_STL2 store requestsL2_LOCKL2 locked accessesL2_RQSTSL2 cache requestsL2_REJECT_BUSQRejected L2 cache requestsL2_NO_REQCycles no L2 cache requests are pendingEIST_TRANSNumber of Enhanced Intel SpeedStep(R) Technology (EIST) transitionsTHERMAL_TRIPNumber of thermal tripsCPU_CLK_UNHALTEDL1D_CACHE_LDL1 cacheable data readsL1D_CACHE_STL1 cacheable data writesL1D_CACHE_LOCKL1 data cacheable locked readsL1D_ALL_REFAll references to the L1 data cacheL1D_ALL_CACHE_REFL1 Data cacheable reads and writesL1D_REPLCache lines allocated in the L1 data cacheL1D_M_REPLModified cache lines allocated in the L1 data cacheL1D_M_EVICTModified cache lines evicted from the L1 data cacheL1D_PEND_MISSTotal number of outstanding L1 data cache misses at any cycleL1D_SPLITCache line split from L1 data cacheSSE_PRE_MISSStreaming SIMD Extensions (SSE) instructions missing all cache levelsLOAD_HIT_PRELoad operations conflicting with a software prefetch to the same addressL1D_PREFETCHL1 data cache prefetchBUS_REQUEST_OUTSTANDINGNumber of pending full cache line read transactions on the bus occurring in each cycleBUS_BNR_DRVNumber of Bus Not Ready signals assertedBUS_DRDY_CLOCKSBus cycles when data is sent on the busBUS_LOCK_CLOCKSBus cycles when a LOCK signal is assertedBUS_DATA_RCVBus cycles while processor receives dataBUS_TRANS_BRDBurst read bus transactionsBUS_TRANS_RFORFO bus transactionsBUS_TRANS_WBExplicit writeback bus transactionsBUS_TRANS_IFETCHInstruction-fetch bus transactionsBUS_TRANS_INVALInvalidate bus transactionsBUS_TRANS_PWRPartial write bus transactionBUS_TRANS_PPartial bus transactionsBUS_TRANS_IOIO bus transactionsBUS_TRANS_DEFDeferred bus transactionsBUS_TRANS_BURSTBurst (full cache-line) bus transactionsBUS_TRANS_MEMMemory bus transactionsBUS_TRANS_ANYAll bus transactionsEXT_SNOOPExternal snoops responsesCMP_SNOOPBUS_HIT_DRVHIT signal assertedBUS_HITM_DRVHITM signal assertedBUSQ_EMPTYBus queue is emptySNOOP_STALL_DRVBus stalled for snoopsBUS_IO_WAITIO requests waiting in the bus queueL1I_READSInstruction fetchesL1I_MISSESInstruction Fetch Unit missesITLBINST_QUEUECYCLES_L1I_MEM_STALLEDCycles during which instruction fetches are stalledILD_STALLInstruction Length Decoder stall cycles due to a length changing prefixBR_INST_EXECBranch instructions executedBR_MISSP_EXECMispredicted branch instructions executedBR_BAC_MISSP_EXECBranch instructions mispredicted at decodingBR_CND_EXECConditional branch instructions executedBR_CND_MISSP_EXECMispredicted conditional branch instructions executedBR_IND_EXECIndirect branch instructions executedBR_IND_MISSP_EXECMispredicted indirect branch instructions executedBR_RET_EXECRET instructions executedBR_RET_MISSP_EXECMispredicted RET instructions executedBR_RET_BAC_MISSP_EXECRET instructions executed mispredicted at decodingBR_CALL_EXECCALL instructions executedBR_CALL_MISSP_EXECMispredicted CALL instructions executedBR_IND_CALL_EXECIndirect CALL instructions executedBR_TKN_BUBBLE_1Branch predicted taken with bubble IBR_TKN_BUBBLE_2Branch predicted taken with bubble IIMACRO_INSTSESPSIMD_UOPS_EXECSIMD micro-ops executed (excluding stores)SIMD_SAT_UOP_EXECSIMD saturated arithmetic micro-ops executedSIMD_UOP_TYPE_EXECINST_RETIREDInstructions retiredX87_OPS_RETIREDUOPS_RETIREDMACHINE_NUKESBR_INST_RETIREDRetired mispredicted branch instructions (Precise_Event)CYCLES_INT_MASKEDCycles during which interrupts are disabledCYCLES_INT_PENDING_AND_MASKEDCycles during which interrupts are pending and disabledSIMD_INST_RETIREDHW_INT_RCVHardware interrupts receivedITLB_MISS_RETIREDRetired instructions that missed the ITLBSIMD_COMP_INST_RETIREDMEM_LOAD_RETIREDRetired loads that miss the L1 data cacheFP_MMX_TRANSSIMD_ASSISTSIMD assists invokedSIMD_INSTR_RETIREDSIMD Instructions retiredSIMD_SAT_INSTR_RETIREDSaturated arithmetic instructions retiredRAT_STALLSSEG_RENAME_STALLSSEG_REG_RENAMESRESOURCE_STALLSBR_INST_DECODEDBranch instructions decodedBOGUS_BRBogus branchesBACLEARSBACLEARS assertedPREF_RQSTS_UPUpward prefetches issued from the DPLPREF_RQSTS_DNDownward prefetches issued from the DPLIntel Corecorekmonitor at priv level 0umonitor at priv level 1, 2, 3eedge level (may require counter-mask >= 1)iinvertccounter-mask in range [0-255]tmeasure any threadldlatload latency threshold (cycles, [3-65535])intxmonitor only inside transactional memory regionintxcpdo not count occurrences inside aborted transactional memory regionfe_thresfrontend bubble latency threshold in cycles ([1-4095][0x%lx event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d any=%d] [0x%lx] %s GenuineIntelpfmlib_intel_x86.c%s (%s.%d): added default %s for group %d j=%d idx=%d ucode=0x%lx %s (%s.%d): two max_grpid, old=%d new=%d %s (%s.%d): no default found for event %s unit mask group %d (max_grpid=%d) %s (%s.%d): max_grpid=%d nattrs=%d k=%d umask=0x%lx %s (%s.%d): check: max_grpid=%d %s (%s.%d): exclusive unit mask group error %s (%s.%d): event requires grpid %d %s (%s.%d): max_req_grpid=%d %s (%s.%d): umask %s does not support unit mask combination within group %d %s (%s.%d): cannot override event with two different codes for %s %s (%s.%d): raw umask is too wide max %d bits %s (%s.%d): required grpid %d umask missing %s (%s.%d): excl_grp_but_0=%d %s (%s.%d): grpcounts[%d]=%d %s (%s.%d): GRP_EXCL_BUT_0 but grpcounts[%d]=%d %s (%s.%d): event %s: umask from grp > %d %s (%s.%d): required modifiers missing: 0x%x %s:%s:0x%x%s (%s.%d): missing fe_thres= for umask, forcing to default %d cycles %s (%s.%d): passed ldlat= but not using ldlat umask %s (%s.%d): missing ldlat= for umask, forcing to default %d cycles %s (%s.%d): edge requires cmask >= 1 :%s=%lu:%s=%d:tp1G l,Dpmu: %s missing attr_desc pmu: %s supported_plm not set ??pmu: %s event%d: :: no name (prev event was %s) pmu: %s event%d: %s :: no description pmu: %s event%d: %s :: empty description pmu: %s event%d: %s :: cntmsk=0 pmu: %s event%d: %s :: ngrp cannot be zero pmu: %s event%d: %s :: numasks but no umasks pmu: %s event%d: %s :: numasks=0 but umasks defined pmu: %s event%d: %s :: ngrp must be zero pmu: %s event%d: %s :: ngrp too big (max=%d) pmu: %s event%d: %s :: model too big (max=%d) pmu: %s events %s and %s have the same code 0x%x pmu: %s event%d: %s umask%d :: no name pmu: %s event%d: %s umask%d: %s :: modhw not subset of modmsk pmu: %s event%d: umask%d: %s :: no description pmu: %s event%d: umask%d: %s :: empty description pmu: %s event%d: %s umask%d: %s :: invalid grpid %d (must be < %d) pmu: %s event%d: %s umask%d: %s :: invalid req_grpid %d (must be < %d) pmu: %s event%d: %s umask%d: %s :: model too big (max=%d) pmu: %s event%d: %s, pebs umasks but event pebs flag not set pmu: %s event%d: %s, pebs event flag but not umask has pebs flag pmu: %s event%d: %s, only one umask but no default pmu: %s event%d: %s grpid %d has 2 default umasks pmu: %s event%d: %s :: NCOMBO is unit mask only flag pmu: %s event%d: %s :: umask %s and %s have overlapping code bits %s (%s.%d): invalid event index %d pfm_intel_x86_add_defaultsintel_x86_check_max_grpidpfm_intel_x86_encode_genpfm_intel_x86_get_event_attr_infopfm_intel_x86_get_event_infoUNHALTED_CORE_CYCLEScount core clock cycles whenever the clock signal on the specific core is running (not halted)INSTRUCTION_RETIREDcount the number of instructions at retirement. For instructions that consists of multiple micro-ops, this event counts the retirement of the last micro-op of the instructionUNHALTED_REFERENCE_CYCLEScount reference clock cycles while the clock signal on the specific core is running. The reference clock operates at a fixed frequency, irrespective of core frequency changes due to performance state transitionsLLC_REFERENCEScount each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetchLLC_MISSEScount each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetchBRANCH_INSTRUCTIONS_RETIREDcount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instructionMISPREDICTED_BRANCH_RETIREDcount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwarepfmlib_intel_x86_arch.c%s (%s.%d): version=%d evt_msk=0x%x Intel X86 architectural PMUix86archcreate_arch_event_tableMESIAny cacheline accessI_STATEInvalid cachelineS_STATEShared cachelineE_STATEExclusive cachelineM_STATEModified cachelineSELFThis coreBOTH_CORESBoth coresANYAll inclusivePREFETCHHardware prefetch onlyACCESSESInstruction fetches, including uncacheacble fetchesMISSESCount all instructions fetches that miss the icache or produce memory requests. This includes uncacheache fetches. Any instruction fetch miss is counted only once and not once for every cycle it is outstandingMicro-ops retiredSTALLED_CYCLESCycles no micro-ops retiredSTALLSPeriods no micro-ops retiredPACKED_SINGLERetired computational Streaming SIMD Extensions (SSE) packed-single instructionsSCALAR_SINGLERetired computational Streaming SIMD Extensions (SSE) scalar-single instructionsPACKED_DOUBLERetired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructionsSCALAR_DOUBLERetired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsSSIMD saturated arithmetic micro-ops executedARSIMD saturated arithmetic micro-ops retiredANY_PInstructions retired using generic counter (precise event)LDL1 Cacheable Data ReadsSTL1 Cacheable Data WritesMultiply operations executedMultiply operations retiredDivide operations executedDivide operations retiredTHIS_AGENTThis agentALL_AGENTSAny agent on the busFLUSHITLB flushesITLB missesMUL_SSIMD packed multiply micro-ops executedMUL_ARSIMD packed multiply micro-ops retiredSHIFT_SSIMD packed shift micro-ops executedSHIFT_ARSIMD packed shift micro-ops retiredPACK_SSIMD packed micro-ops executedPACK_ARSIMD packed micro-ops retiredUNPACK_SSIMD unpacked micro-ops executedUNPACK_ARSIMD unpacked micro-ops retiredLOGICAL_SSIMD packed logical micro-ops executedLOGICAL_ARSIMD packed logical micro-ops retiredARITHMETIC_SSIMD packed arithmetic micro-ops executedARITHMETIC_ARSIMD packed arithmetic micro-ops retiredRetired Streaming SIMD Extensions (SSE) packed-single instructionsRetired Streaming SIMD Extensions (SSE) scalar-single instructionsRetired Streaming SIMD Extensions 2 (SSE2) packed-double instructionsRetired Streaming SIMD Extensions 2 (SSE2) scalar-double instructionsVECTORRetired Streaming SIMD Extensions 2 (SSE2) vector instructionsRetired Streaming SIMD instructionsPREFETCHT0Streaming SIMD Extensions (SSE) PrefetchT0 instructions executedSW_L2Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executedPREFETCHNTAStreaming SIMD Extensions (SSE) Prefetch NTA instructions executedNumber of SIMD saturated arithmetic micro-ops executedNumber of SIMD saturated arithmetic micro-ops retiredSMCSelf-Modifying Code detectedRetired branch instructionsPRED_NOT_TAKENRetired branch instructions that were predicted not-takenMISPRED_NOT_TAKENRetired branch instructions that were mispredicted not-takenPRED_TAKENRetired branch instructions that were predicted takenMISPRED_TAKENRetired branch instructions that were mispredicted takenMISPREDRetired mispredicted branch instructionsTAKENRetired taken branch instructionsANY1NON_CISC_DECODEDNon-CISC macro instructions decoded ALL_DECODEDAll Instructions decodedNumber of segment register loadsBACLEARS assertedCYCLES_INT_MASKEDCycles during which interrupts are disabledCYCLES_INT_PENDING_AND_MASKEDCycles during which interrupts are pending and disabledFloating point assists for executed instructionsFloating point assists for retired instructionsDTLB_MISSMemory accesses that missed the DTLBDTLB_MISS_LDDTLB misses due to load operationsL0_DTLB_MISS_LDL0 (micro-TLB) misses due to load operationsDTLB_MISS_STDTLB misses due to store operationsGOODGood store forwardsCORE_PCore cycles when core is not haltedBUSBus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratioNO_OTHERBus cycles when core is active and other is haltedL2_HITRetired loads that hit the L2 cache (precise event)L2_MISSRetired loads that miss the L2 cache (precise event)Retired loads that miss the DTLB (precise event)ANY_SFloating point computational micro-ops executedANY_ARFloating point computational micro-ops retiredWALKSNumber of page-walks executedCYCLESDuration of page-walks in core cyclesUNHALTED_CORE_CYCLESUnhalted core cyclesUNHALTED_REFERENCE_CYCLESUnhalted reference cycleINSTRUCTION_RETIREDInstructions retiredINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDLLC_REFERENCESLast level of cache referencesLAST_LEVEL_CACHE_REFERENCESThis is an alias for LLC_REFERENCESLLC_MISSESLast level of cache missesLAST_LEVEL_CACHE_MISSESThis is an alias for LLC_MISSESBRANCH_INSTRUCTIONS_RETIREDBranch instructions retiredBR_INST_RETIRED:ANYMISPREDICTED_BRANCH_RETIREDMispredicted branch instruction retiredSIMD_INSTR_RETIREDSIMD Instructions retiredL2_REJECT_BUSQRejected L2 cache requestsSIMD_SAT_INSTR_RETIREDSaturated arithmetic instructions retiredICACHEInstruction fetchesL2_LOCKL2 locked accessesUOPS_RETIREDL2_M_LINES_OUTModified lines evicted from the L2 cacheSIMD_COMP_INST_RETIREDRetired computational Streaming SIMD Extensions (SSE) instructionsSNOOP_STALL_DRVBus stalled for snoopsBUS_TRANS_BURSTBurst (full cache-line) bus transactionsSIMD_SAT_UOP_EXECBUS_TRANS_IOIO bus transactionsBUS_TRANS_RFORFO bus transactionsSIMD_ASSISTSIMD assists invokedINST_RETIREDL1D_CACHEMULDIVBUS_TRANS_PPartial bus transactionsBUS_IO_WAITIO requests waiting in the bus queueL2_M_LINES_INL2 cache line modificationsL2_LINES_INL2 cache missesBUSQ_EMPTYBus queue is emptyL2_IFETCHL2 cacheable instruction fetch requestsBUS_HITM_DRVHITM signal assertedITLBITLB hitsBUS_TRANS_MEMMemory bus transactionsBUS_TRANS_PWRPartial write bus transactionBR_INST_DECODEDBranch instructions decodedBUS_TRANS_INVALInvalidate bus transactionsSIMD_UOP_TYPE_EXECSIMD micro-ops executedSIMD_INST_RETIREDRetired Streaming SIMD Extensions (SSE) instructionsCYCLES_DIV_BUSYCycles the divider is busyL2_RQSTSL2 cache requestsSIMD_UOPS_EXECSIMD micro-ops executed (excluding stores)HW_INT_RCVHardware interrupts received (warning overcounts by 2x)BUS_TRANS_BRDBurst read bus transactionsBOGUS_BRBogus branchesBUS_DATA_RCVBus cycles while processor receives dataMACHINE_CLEARSBR_INST_RETIREDL2_ADSCycles L2 address bus is in useEIST_TRANSNumber of Enhanced Intel SpeedStep(R) Technology (EIST) transitionsBUS_TRANS_WBExplicit writeback bus transactionsMACRO_INSTSMacro-instructions decodedL2_LINES_OUTL2 cache lines evicted. L2_LDL2 cache readsSEGMENT_REG_LOADSL2_NO_REQCycles no L2 cache requests are pendingTHERMAL_TRIPNumber of thermal tripsEXT_SNOOPExternal snoopsBACLEARSBranch address calculatorFP_ASSISTFloating point assistsL2_STL2 store requestsBUS_TRANS_DEFDeferred bus transactionsDATA_TLB_MISSESBUS_BNR_DRVNumber of Bus Not Ready signals assertedSTORE_FORWARDSAll store forwardsCPU_CLK_UNHALTEDBUS_TRANS_ANYAll bus transactionsMEM_LOAD_RETIREDRetired loadsX87_COMP_OPS_EXEPAGE_WALKSBUS_LOCK_CLOCKSBus cycles when a LOCK signal is assertedBUS_REQUEST_OUTSTANDINGOutstanding cacheable data read bus requests durationBUS_TRANS_IFETCHInstruction-fetch bus transactionsBUS_HIT_DRVHIT signal assertedBUS_DRDY_CLOCKSBus cycles when data is sent on the busL2_DBUS_BUSYCycles the L2 cache data bus is busy&'56Intel AtomatomCH0DRAM Channel 0 open commands issued for read or writeCH1DRAM Channel 1 open commands issued for read or writeCH2DRAM Channel 2 open commands issued for read or writeDRAM Channel 0 page closeDRAM Channel 1 page closeDRAM Channel 2 page closeDRAM Channel 0 page missDRAM Channel 1 page missDRAM Channel 2 page missDRAM Channel 0 precharge all commandsDRAM Channel 1 precharge all commandsDRAM Channel 2 precharge all commandsDRAM Channel 0 read CAS commandsAUTOPRE_CH0DRAM Channel 0 read CAS auto page close commandsDRAM Channel 1 read CAS commandsAUTOPRE_CH1DRAM Channel 1 read CAS auto page close commandsDRAM Channel 2 read CAS commandsAUTOPRE_CH2DRAM Channel 2 read CAS auto page close commandsDRAM Channel 0 refresh commandsDRAM Channel 1 refresh commandsDRAM Channel 2 refresh commandsDRAM Channel 0 write CAS commandsDRAM Channel 0 write CAS auto page close commandsDRAM Channel 1 write CAS commandsDRAM Channel 1 write CAS auto page close commandsDRAM Channel 2 write CAS commandsDRAM Channel 2 write CAS auto page close commandsREAD_TRACKERGQ read tracker requestsRT_LLC_MISSGQ read tracker LLC missesRT_TO_LLC_RESPGQ read tracker LLC requestsRT_TO_RTID_ACQUIREDGQ read tracker LLC miss to RTID acquiredWT_TO_RTID_ACQUIREDGQ write tracker LLC miss to RTID acquiredWRITE_TRACKERGQ write tracker LLC missesPEER_PROBE_TRACKERGQ peer probe tracker requestsCycles GQ read tracker is full.Cycles GQ write tracker is full.Cycles GQ peer probe tracker is full.Cycles GQ read tracker is busyCycles GQ write tracker is busyCycles GQ peer probe tracker is busyQPICycles GQ data is imported from Quickpath interfaceQMCCycles GQ data is imported from Quickpath memory interfaceLLCCycles GQ data is imported from LLCCORES_02Cycles GQ data is imported from Cores 0 and 2CORES_13Cycles GQ data is imported from Cores 1 and 3QPI_QMCCycles GQ data sent to the QPI or QMCCycles GQ data sent to LLCCORESCycles GQ data sent to coresREADNumber of LLC read hitsWRITENumber of LLC write hitsPROBENumber of LLC peer probe hitsANYNumber of LLC hitsM_STATELLC lines allocated in M stateE_STATELLC lines allocated in E stateS_STATELLC lines allocated in S stateF_STATELLC lines allocated in F stateLLC lines allocatedLLC lines victimized in M stateLLC lines victimized in E stateLLC lines victimized in S stateI_STATELLC lines victimized in I stateLLC lines victimized in F stateLLC lines victimizedNumber of LLC read missesNumber of LLC write missesNumber of LLC peer probe missesNumber of LLC misses2WAYQHL 2 way address conflicts3WAYQHL 3 way address conflictsIOHQHL IOH Tracker conflict cyclesREMOTEQHL Remote Tracker conflict cyclesLOCALQHL Local Tracker conflict cyclesCycles QHL Remote Tracker is fullCycles QHL Local Tracker is fullCycles QHL IOH Tracker is fullCycles QHL IOH is busyCycles QHL Remote Tracker is busyCycles QHL Local Tracker is busyQHL FrcAckCnflts sent to local homeCycles QHL IOH Tracker Allocate to Deallocate Read OccupancyCycles QHL Remote Tracker Allocate to Deallocate Read OccupancyCycles QHL Local Tracker Allocate to Deallocate Read OccupancyLOCAL_READSQuickpath Home Logic local read requestsLOCAL_WRITESQuickpath Home Logic local write requestsREMOTE_READSQuickpath Home Logic remote read requestsIOH_READSQuickpath Home Logic IOH read requestsIOH_WRITESQuickpath Home Logic IOH write requestsREMOTE_WRITESQuickpath Home Logic remote write requestsREAD_CH0Cycles QMC channel 0 busy with a read requestREAD_CH1Cycles QMC channel 1 busy with a read requestREAD_CH2Cycles QMC channel 2 busy with a read requestWRITE_CH0Cycles QMC channel 0 busy with a write requestWRITE_CH1Cycles QMC channel 1 busy with a write requestWRITE_CH2Cycles QMC channel 2 busy with a write requestQMC channel 0 cancelsQMC channel 1 cancelsQMC channel 2 cancelsQMC cancelsQMC channel 0 critical priority read requestsQMC channel 1 critical priority read requestsQMC channel 2 critical priority read requestsQMC critical priority read requestsQMC channel 0 high priority read requestsQMC channel 1 high priority read requestsQMC channel 2 high priority read requestsQMC high priority read requestsCycles DRAM channel 0 full with isochronous read requestsCycles DRAM channel 1 full with isochronous read requestsCycles DRAM channel 2 full with isochronous read requestsCycles DRAM channel 0 full with isochronous write requestsCycles DRAM channel 1 full with isochronous write requestsCycles DRAM channel 2 full with isochronous write requestsIMC channel 0 isochronous read request occupancyIMC channel 1 isochronous read request occupancyIMC channel 2 isochronous read request occupancyIMC isochronous read request occupancyCycles DRAM channel 0 full with normal read requestsCycles DRAM channel 1 full with normal read requestsCycles DRAM channel 2 full with normal read requestsCycles DRAM channel 0 full with normal write requestsCycles DRAM channel 1 full with normal write requestsCycles DRAM channel 2 full with normal write requestsQMC channel 0 normal read requestsQMC channel 1 normal read requestsQMC channel 2 normal read requestsQMC normal read requestsIMC channel 0 normal read request occupancyIMC channel 1 normal read request occupancyIMC channel 2 normal read request occupancyQMC channel 0 priority updatesQMC channel 1 priority updatesQMC channel 2 priority updatesQMC priority updatesFULL_CH0QMC channel 0 full cache line writesFULL_CH1QMC channel 1 full cache line writesFULL_CH2QMC channel 2 full cache line writesFULL_ANYQMC full cache line writesPARTIAL_CH0QMC channel 0 partial cache line writesPARTIAL_CH1QMC channel 1 partial cache line writesPARTIAL_CH2QMC channel 2 partial cache line writesPARTIAL_ANYQMC partial cache line writesSTALLS_LINK_0Link 0 snoop stalls due to no PPT entrySTALLS_LINK_1Link 1 snoop stalls due to no PPT entryBUSY_LINK_0Cycles link 0 outbound header busyBUSY_LINK_1Cycles link 1 outbound header busyDRS_LINK_0Cycles QPI outbound link 0 DRS stalledNCB_LINK_0Cycles QPI outbound link 0 NCB stalledNCS_LINK_0Cycles QPI outbound link 0 NCS stalledDRS_LINK_1Cycles QPI outbound link 1 DRS stalledNCB_LINK_1Cycles QPI outbound link 1 NCB stalledNCS_LINK_1Cycles QPI outbound link 1 NCS stalledLINK_0Cycles QPI outbound link 0 multi flit stalledLINK_1Cycles QPI outbound link 1 multi flit stalledHOME_LINK_0Cycles QPI outbound link 0 HOME stalledSNOOP_LINK_0Cycles QPI outbound link 0 SNOOP stalledNDR_LINK_0Cycles QPI outbound link 0 NDR stalledHOME_LINK_1Cycles QPI outbound link 1 HOME stalledSNOOP_LINK_1Cycles QPI outbound link 1 SNOOP stalledNDR_LINK_1Cycles QPI outbound link 1 NDR stalledCycles QPI outbound link 0 single flit stalledCycles QPI outbound link 1 single flit stalledLocal home snoop response - LLC does not have cache lineLocal home snoop response - LLC has cache line in S stateFWD_S_STATELocal home snoop response - LLC forwarding cache line in S state.FWD_I_STATELocal home snoop response - LLC has forwarded a modified cache lineCONFLICTLocal home conflict snoop responseWBLocal home snoop response - LLC has cache line in the M stateRemote home snoop response - LLC does not have cache lineRemote home snoop response - LLC has cache line in S stateRemote home snoop response - LLC forwarding cache line in S state.Remote home snoop response - LLC has forwarded a modified cache lineRemote home conflict snoop responseRemote home snoop response - LLC has cache line in the M stateHITMRemote home snoop response - LLC HITMUNC_CLK_UNHALTEDUncore clockticks.UNC_DRAM_OPENDRAM open commands issued for read or writeUNC_DRAM_PAGE_CLOSEDRAM page close due to idle timer expirationUNC_DRAM_PAGE_MISSUNC_DRAM_PRE_ALLUNC_DRAM_READ_CASUNC_DRAM_REFRESHUNC_DRAM_WRITE_CASUNC_GQ_ALLOCUNC_GQ_CYCLES_FULLUNC_GQ_CYCLES_NOT_EMPTYUNC_GQ_DATA_FROMCycles GQ data is importedUNC_GQ_DATA_TOCycles GQ data is exportedUNC_LLC_HITSUNC_LLC_LINES_INUNC_LLC_LINES_OUTUNC_LLC_MISSUNC_QHL_ADDRESS_CONFLICTSUNC_QHL_CONFLICT_CYCLESUNC_QHL_CYCLES_FULLUNC_QHL_CYCLES_NOT_EMPTYCycles QHL Tracker is not emptyUNC_QHL_FRC_ACK_CNFLTSUNC_QHL_OCCUPANCYCycles QHL Tracker Allocate to Deallocate Read OccupancyUNC_QHL_REQUESTSUNC_QHL_TO_QMC_BYPASSNumber of requests to QMC that bypass QHLUNC_QMC_BUSYCycles QMC busy with a read requestUNC_QMC_CANCELUNC_QMC_CRITICAL_PRIORITY_READSUNC_QMC_HIGH_PRIORITY_READSUNC_QMC_ISOC_FULLCycles DRAM full with isochronous (ISOC) read requestsUNC_IMC_ISOC_OCCUPANCYIMC isochronous (ISOC) Read OccupancyUNC_QMC_NORMAL_FULLCycles DRAM full with normal read requestsUNC_QMC_NORMAL_READSUNC_QMC_OCCUPANCYQMC OccupancyUNC_QMC_PRIORITY_UPDATESUNC_QMC_WRITESQMC cache line writesUNC_QPI_RX_NO_PPT_CREDITUNC_QPI_TX_HEADERUNC_QPI_TX_STALLED_MULTI_FLITCycles QPI outbound stallsUNC_QPI_TX_STALLED_SINGLE_FLITCycles QPI outbound link stallsUNC_SNP_RESP_TO_LOCAL_HOMELocal home snoop responseUNC_SNP_RESP_TO_REMOTE_HOMERemote home snoop responseIn the read trackerIOH_ORDERDue to IOH ordering (write after read) conflictsREMOTE_ORDERDue to remote socket ordering (write after read) conflictsLOCAL_ORDERDue to local socket ordering (write after read) conflictsIOH_CONFLICTDue to IOH address conflictsREMOTE_CONFLICTDue to remote socket address conflictsLOCAL_CONFLICTDue to local socket address conflictsChannel 0Channel 1Channel 2Any channelCORE_0Core 0CORE_1Core 1CORE_2Core 2CORE_3Core 3UNC_GC_OCCUPANCYNumber of queue entriesUNC_DRAM_THERMAL_THROTTLEDUncore cycles DRAM was throttled due to its temperature being above thermal throttling thresholdUNC_QHL_SLEEPSNumber of occurrences a request was put to sleepUNC_IMC_RETRYNumber of IMC DRAM channel retries (retries occur in RAS mode only)UNC_THERMAL_THROTTLING_TEMPUncore cycles that the PCU records core temperature above thresholdUNC_THERMAL_THROTTLED_TEMPUncore cycles that the PCU records that core is in power throttled state due to temperature being above thresholdUNC_PROCHOT_ASSERTIONNumber of system assertions of PROCHOT indicating the entire processor has exceeded the thermal limitUNC_THERMAL_THROTTLING_PROCHOTUncore cycles that the PCU records that core is in power throttled state due PROCHOT assertionsUNC_TURBO_MODEUncore cycles that a core is operating in turbo modeUNC_CYCLES_UNHALTED_L3_FLL_ENABLEUncore cycles where at least one core is unhalted and all L3 ways are enabledUNC_CYCLES_UNHALTED_L3_FLL_DISABLEUncore cycles where at least one core is unhalted and all L3 ways are disabledeedge leveliinvertccounter-mask in range [0-255]oqueue occupancy,/pfmlib_intel_nhm_unc.c%s (%s.%d): exclusive unit mask group error %s (%s.%d): event does not support unit mask combination within a group :%s%s (%s.%d): raw umask is 8-bit wide %s (%s.%d): required modifiers missing: 0x%x %s:0x%x:%s=%lu[UNC_PERFEVTSEL=0x%lx event=0x%x umask=0x%x en=%d int=%d inv=%d edge=%d occ=%d cnt_msk=%d] %s Intel Nehalem uncorenhm_uncuncoreIntel Westmere uncorewsm_uncpfm_nhm_unc_get_encodingCYCLES_DIV_BUSYCounts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.DIVCounts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.CYCLES_DIV_BUSY:c=1:i=1:e=1MULCounts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD.BAD_TARGETBACLEAR asserted with bad target addressCLEARBACLEAR asserted, regardless of causeEARLYEarly Branch Prediction Unit clearsLATELate Branch Prediction Unit clearsANYCount any Branch Prediction Unit clearsBranch instructions executedCONDConditional branch instructions executedDIRECTUnconditional branches executedDIRECT_NEAR_CALLUnconditional call branches executedINDIRECT_NEAR_CALLIndirect call branches executedINDIRECT_NON_CALLIndirect non call branches executedNEAR_CALLSCall branches executedNON_CALLSAll non call branches executedRETURN_NEARIndirect return branches executedTAKENTaken branches executedALL_BRANCHESRetired branch instructions (Precise Event)CONDITIONALRetired conditional branch instructions (Precise Event)NEAR_CALLRetired near call instructions (Precise Event)Mispredicted branches executedMispredicted conditional branches executedMispredicted unconditional branches executedMispredicted non call branches executedMispredicted indirect call branches executedMispredicted indirect non call branches executedMispredicted call branches executedMispredicted return branches executedMispredicted taken branches executedCounts mispredicted direct and indirect near unconditional retired callsL1DCycles L1D lockedL1D_L2Cycles L1D and L2 lockedTHREAD_PCycles when thread is not halted (programmable counter)REF_PReference base clock (133 Mhz) cycles when thread is not haltedTOTAL_CYCLESTotal number of elapsed cycles. Does not work when C-state enabledTHREAD_P:c=2:i=1DTLB load missesPDE_MISSDTLB load miss caused by low part of addressWALK_COMPLETEDDTLB load miss page walks completeSTLB_HITDTLB second level hitPDP_MISSNumber of DTLB cache load misses where the high part of the linear to physical address translation was missedLARGE_WALK_COMPLETEDCounts number of completed large page walks due to load miss in the STLBDTLB missesDTLB first level misses but second level hitDTLB miss page walksNumber of DTLB cache misses where the low part of the linear to physical address translation was missedNumber of DTLB misses where the high part of the linear to physical address translation was missedCounts number of completed large page walks due to misses in the STLBEPDE_MISSExtended Page Directory Entry missEPDPE_MISSExtended Page Directory Pointer missEPDPE_HITExtended Page Directory Pointer hitALLFloating point assists (Precise Event)INPUTFloating point assists for invalid input value (Precise Event)OUTPUTFloating point assists for invalid output value (Precise Event)MMXMMX UopsSSE_DOUBLE_PRECISIONSSE* FP double precision UopsSSE_FPSSE and SSE2 FP UopsSSE_FP_PACKEDSSE FP packed UopsSSE_FP_SCALARSSE FP scalar UopsSSE_SINGLE_PRECISIONSSE* FP single precision UopsSSE2_INTEGERSSE2 integer UopsX87Computational floating-point operations executedAll Floating Point to and from MMX transitionsTO_FPTransitions from MMX to Floating Point instructionsTO_MMXTransitions from Floating Point to MMX instructionsFULLInstruction Fetche unit victim cache fullL1I_EVICTIONL1 Instruction cache evictionsAny Instruction Length Decoder stall cyclesIQ_FULL:LCP:MRU:REGENIQ_FULLInstruction Queue full stall cyclesLCPLength Change Prefix stall cyclesMRUStall cycles due to BPU MRU bypassREGENRegen stall cyclesDEC0Instructions that must be decoded by decoder 0ANY_PInstructions Retired (Precise Event)Retired floating-point operations (Precise Event)M_EVICTL1D cache lines replaced in M stateM_REPLL1D cache lines allocated in the M stateM_SNOOP_EVICTL1D snoop eviction of cache lines in M stateREPLL1 data cache lines allocatedAll references to the L1 data cacheCACHEABLEL1 data cacheable reads and writesE_STATEL1 data cache read in E stateI_STATEL1 data cache read in I state (misses)M_STATEL1 data cache read in M stateMESIL1 data cache readsS_STATEL1 data cache read in S stateL1 data cache load locks in E stateHITL1 data cache load lock hitsL1 data cache load locks in M stateL1 data cache load locks in S stateL1 data cache stores in E stateL1 data cache store in the I stateL1 data cache stores in M stateL1 data cache stores in S stateL1 data cache store in all statesMISSL1D hardware prefetch missesREQUESTSL1D hardware prefetch requestsTRIGGERSL1D hardware prefetch requests triggeredL1 writebacks to L2 in E stateL1 writebacks to L2 in I state (misses)L1 writebacks to L2 in M stateL1 writebacks to L2 in S stateAll L1 writebacks to L2CYCLES_STALLEDL1I instruction fetch stall cyclesHITSL1I instruction fetch hitsMISSESL1I instruction fetch missesREADSL1I Instruction fetchesAll L2 data requestsDEMAND_E_STATEL2 data demand loads in E stateDEMAND_I_STATEL2 data demand loads in I state (misses)DEMAND_M_STATEL2 data demand loads in M stateDEMAND_MESIL2 data demand requestsDEMAND_S_STATEL2 data demand loads in S statePREFETCH_E_STATEL2 data prefetches in E statePREFETCH_I_STATEL2 data prefetches in the I state (misses)PREFETCH_M_STATEL2 data prefetches in M statePREFETCH_MESIAll L2 data prefetchesPREFETCH_S_STATEL2 data prefetches in the S stateCount L2 HW prefetcher detector hitsALLOCCount L2 HW prefetcher allocationsDATA_TRIGGERCount L2 HW data prefetcher triggeredCODE_TRIGGERCount L2 HW code prefetcher triggeredDCA_TRIGGERCount L2 HW DCA prefetcher triggeredKICK_STARTCount L2 HW prefetcher kick startedL2 lines allocatedL2 lines allocated in the E stateL2 lines allocated in the S stateL2 lines evictedDEMAND_CLEANL2 lines evicted by a demand requestDEMAND_DIRTYL2 modified lines evicted by a demand requestPREFETCH_CLEANL2 lines evicted by a prefetch requestPREFETCH_DIRTYL2 modified lines evicted by a prefetch requestAll L2 missesREFERENCESAll L2 requestsIFETCH_HITL2 instruction fetch hitsIFETCH_MISSL2 instruction fetch missesIFETCHESL2 instruction fetchesLD_HITL2 load hitsLD_MISSL2 load missesLOADSL2 requestsPREFETCH_HITL2 prefetch hitsPREFETCH_MISSL2 prefetch missesPREFETCHESAll L2 prefetchesRFO_HITL2 RFO hitsRFO_MISSL2 RFO missesRFOSL2 RFO requestsAll L2 transactionsFILLL2 fill transactionsIFETCHL2 instruction fetch transactionsL1D_WBL1D writeback to L2 transactionsLOADL2 Load transactionsPREFETCHL2 prefetch transactionsRFOL2 RFO transactionsWBL2 writeback to LLC transactionsLOCK_E_STATEL2 demand lock RFOs in E stateLOCK_I_STATEL2 demand lock RFOs in I state (misses)LOCK_S_STATEL2 demand lock RFOs in S stateLOCK_HITAll demand L2 lock RFOs that hit the cacheLOCK_M_STATEL2 demand lock RFOs in M stateLOCK_MESIAll demand L2 lock RFOsAll L2 demand store RFOs that hit the cacheRFO_I_STATEL2 demand store RFOs in I state (misses)RFO_E_STATEL2 demand store RFOs in the E state (exclusive)RFO_M_STATEL2 demand store RFOs in M stateRFO_MESIAll L2 demand store RFOsRFO_S_STATEL2 demand store RFOs in S stateLarge ITLB hitAll loads dispatchedMOBLoads dispatched from the MOBRSLoads dispatched that bypass the MOBRS_DELAYEDLoads dispatched from stage 305REFERENCELongest latency cache referenceLongest latency cache missACTIVECycles when uops were delivered by the LSDINACTIVECycles no uops were delivered by the LSDACTIVE:i=1SMCSelf-Modifying Code detectedCYCLESCycles machine clear assertedMEM_ORDERExecution pipeline restart due to Memory ordering conflictsFUSION_ASSISTCounts the number of macro-fusion assistsDECODEDInstructions decodedFUSIONS_DECODEDMacro-fused instructions decodedRESETCounts memory disambiguation reset cyclesWATCHDOGCounts the number of times the memory disambiguation watchdog kicked inWATCH_CYCLESCounts the cycles that the memory disambiguation watchdog is activeLATENCY_ABOVE_THRESHOLDMemory instructions retired above programmed clocks, minimum threshold value is 3, (Precise Event and ldlat required)Instructions retired which contains a load (Precise Event)STORESInstructions retired which contains a store (Precise Event)DTLB_MISSRetired loads that miss the DTLB (Precise Event)HIT_LFBRetired loads that miss L1D and hit an previously allocated LFB (Precise Event)L1D_HITRetired loads that hit the L1 data cache (Precise Event)L2_HITRetired loads that hit the L2 cache (Precise Event)L3_MISSRetired loads that miss the L3 cache (Precise Event)LLC_MISSThis is an alias for L3_MISSL3_UNSHARED_HITRetired loads that hit valid versions in the L3 cache (Precise Event)LLC_UNSHARED_HITThis is an alias for L3_UNSHARED_HITOTHER_CORE_L2_HIT_HITMRetired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)Retired stores that miss the DTLB (Precise Event)OTHER_CORE_L2_HITMLoad instructions retired that HIT modified data in sibling core (Precise Event)REMOTE_CACHE_LOCAL_HOME_HITLoad instructions retired remote cache HIT data source (Precise Event)REMOTE_DRAMLoad instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)LOCAL_DRAMLoad instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)L3_DATA_MISS_UNKNOWNLoad instructions retired where the memory reference missed L3 and data source is unknown (Model 46 only, Precise Event)UNCACHEABLELoad instructions retired where the memory reference missed L1, L2, L3 caches and to perform I/O (Model 46 only, Precise Event)All offcore requestsANY_READOffcore read requestsANY_RFOOffcore RFO requestsDEMAND_READ_CODECounts number of offcore demand code read requests. Does not count L2 prefetch requests.DEMAND_READ_DATAOffcore demand data read requestsDEMAND_RFOOffcore demand RFO requestsL1D_WRITEBACKOffcore L1 data cache writebacksUNCACHED_MEMCounts number of offcore uncached memory requestsTPR_READSCounts number of TPR readsTPR_WRITESCounts number of TPR writesFLAGSFlag stall cyclesREGISTERSPartial register stall cyclesROB_READ_PORTROB read port stalls cyclesSCOREBOARDScoreboard stall cyclesAll RAT stall cyclesFPCWFPU control word write stall cyclesLoad buffer stall cyclesMXCSRMXCSR rename stall cyclesRS_FULLReservation Station full stall cyclesSTOREStore buffer stall cyclesOTHEROther Resource related stall cyclesROB_FULLROB full stall cyclesResource related stall cyclesPACK128 bit SIMD integer pack operationsPACKED_ARITH128 bit SIMD integer arithmetic operationsPACKED_LOGICAL128 bit SIMD integer logical operationsPACKED_MPY128 bit SIMD integer multiply operationsPACKED_SHIFT128 bit SIMD integer shift operationsSHUFFLE_MOVE128 bit SIMD integer shuffle/move operationsUNPACK128 bit SIMD integer unpack operationsSIMD integer 64 bit pack operationsSIMD integer 64 bit arithmetic operationsSIMD integer 64 bit logical operationsSIMD integer 64 bit packed multiply operationsSIMD integer 64 bit shift operationsSIMD integer 64 bit shuffle/move operationsSIMD integer 64 bit unpack operationsThread responded HIT to snoopHITEThread responded HITE to snoopHITMThread responded HITM to snoopPROMOTIONCounts the number of L2 secondary misses that hit the Super QueuePROMOTION_POST_GOCounts the number of L2 secondary misses during the Super Queue filling L2LRU_HINTSCounts number of Super Queue LRU hints sent to L3FILL_DROPPEDCounts the number of SQ L2 fills dropped due to L2 busySPLIT_LOCKSuper Queue lock splits across a cache lineNTAStreaming SIMD L1D NTA prefetch missPACKED_DOUBLESIMD Packed-Double Uops retired (Precise Event)PACKED_SINGLESIMD Packed-Single Uops retired (Precise Event)SCALAR_DOUBLESIMD Scalar-Double Uops retired (Precise Event)SCALAR_SINGLESIMD Scalar-Single Uops retired (Precise Event)VECTOR_INTEGERSIMD Vector Integer Uops retired (Precise Event)AT_RETLoads delayed with at-Retirement block codeL1D_BLOCKCacheable loads delayed with L1D block codeNOT_STALoads delayed due to a store blocked for unknown dataSTALoads delayed due to a store blocked for an unknown addressESP_FOLDINGStack pointer instructions decodedESP_SYNCStack pointer sync operationsMSUops decoded by Microcode SequencerMS_CYCLES_ACTIVECycles in which at least one uop is decoded by Microcode SequencerMS:c=1PORT0Uops executed on port 0PORT1Uops executed on port 1PORT2_COREUops executed on port 2 on any thread (core count only)PORT3_COREUops executed on port 3 on any thread (core count only)PORT4_COREUops executed on port 4 on any thread (core count only)PORT5Uops executed on port 5PORT015Uops issued on ports 0, 1 or 5PORT234_COREUops issued on ports 2, 3 or 4 on any thread (core count only)PORT015_STALL_CYCLESCycles no Uops issued on ports 0, 1 or 5PORT015:c=1:i=1Uops issuedSTALLED_CYCLESCycles stalled no issued uopsANY:c=1:i=1FUSEDFused Uops issuedUops retired (Precise Event)RETIRE_SLOTSRetirement slots used (Precise Event)ACTIVE_CYCLESCycles Uops are being retired (Precise Event)ANY:c=1STALL_CYCLESCycles No Uops retired (Precise Event)MACRO_FUSEDMacro-fused Uops retired (Precise Event)DMND_DATA_RDRequest: counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFODMND_IFETCHRequest: counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesRequest: counts the number of writeback (modified to exclusive) transactionsPF_DATA_RDRequest: counts the number of data cacheline reads generated by L2 prefetchersPF_RFORequest: counts the number of RFO requests generated by L2 prefetchersPF_IFETCHRequest: counts the number of code reads generated by L2 prefetchersRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockANY_IFETCHRequest: combination of PF_IFETCH | DMND_IFETCHPF_IFETCH:DMND_IFETCHANY_REQUESTRequest: combination of all requests umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:OTHERANY_DATARequest: any data read/write requestDMND_DATA_RD:PF_DATA_RD:DMND_RFO:PF_RFOANY_DATA_RDRequest: any data read in requestDMND_DATA_RD:PF_DATA_RDRequest: combination of DMND_RFO | PF_RFODMND_RFO:PF_RFOUNCORE_HITResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)OTHER_CORE_HIT_SNPResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)OTHER_CORE_HITMResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)REMOTE_CACHE_HITMResponse: counts L3 Hit: local or remote home requests that hit a remote L3 cacheline in modified (HITM) stateREMOTE_CACHE_FWDResponse: counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)Response: counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAMResponse: counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAMNON_DRAMResponse: Non-DRAM requests that were serviced by IOHANY_CACHE_DRAMResponse: requests serviced by any source but IOHUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_FWD:REMOTE_CACHE_HITM:REMOTE_DRAM:LOCAL_DRAMANY_DRAMResponse: requests serviced by local or remote DRAMREMOTE_DRAM:LOCAL_DRAMANY_LLC_MISSResponse: requests that missed in L3REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAMLOCAL_CACHE_DRAMResponse: requests hit local core or uncore caches or local DRAMUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:LOCAL_DRAMREMOTE_CACHE_DRAMResponse: requests that miss L3 and hit remote caches or DRAMREMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAMANY_RESPONSEResponse: combination of all response umasksUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_FWD:REMOTE_CACHE_HITM:REMOTE_DRAM:LOCAL_DRAM:NON_DRAMUNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted)INSTRUCTION_RETIREDCount the number of instructions at retirementINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDUNHALTED_REFERENCE_CYCLESUnhalted reference cyclesLLC_REFERENCESCount each request originating equiv the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESILAST_LEVEL_CACHE_REFERENCESThis is an alias for LLC_REFERENCESLLC_MISSESCount each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATELAST_LEVEL_CACHE_MISSESThis is an equiv for LLC_MISSESBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction.BR_INST_RETIRED:ALL_BRANCHESARITHCounts arithmetic multiply and divide operationsBACLEARBranch address calculatorBACLEAR_FORCE_IQInstruction queue forced BACLEARBOGUS_BRCounts the number of bogus branches.BPU_CLEARSBranch prediction Unit clearsBPU_MISSED_CALL_RETBranch prediction unit missed call or returnBR_INST_DECODEDBranch instructions decodedBR_INST_EXECBR_INST_RETIREDRetired branch instructionsBR_MISP_EXECBR_MISP_RETIREDCount Mispredicted Branch ActivityCACHE_LOCK_CYCLESCache lock cyclesCPU_CLK_UNHALTEDCycles when processor is not in halted stateDTLB_LOAD_MISSESData TLB load missesDTLB_MISSESData TLB missesEPTExtended Page DirectoryES_REG_RENAMESES segment renamesFP_ASSISTFloating point assistsFP_COMP_OPS_EXEFloating point computational micro-opsFP_MMX_TRANSFloating Point to and from MMX transitionsIFU_IVCInstruction Fetch unit victim cacheILD_STALLInstruction Length Decoder stallsINST_DECODEDINST_QUEUE_WRITESInstructions written to instruction queue.INST_QUEUE_WRITE_CYCLESCycles instructions are written to the instruction queueINST_RETIREDInstructions retiredIO_TRANSACTIONSI/O transactionsITLB_FLUSHCounts the number of ITLB flushesITLB_MISSESInstruction TLB missesITLB_MISS_RETIREDRetired instructions that missed the ITLB (Precise Event)L1D cacheL1D_ALL_REFL1D referencesL1D_CACHE_LDL1D cacheable loads. WARNING: event may overcount loadsL1D_CACHE_LOCKL1 data cache load lockL1D_CACHE_LOCK_FB_HITL1D load lock accepted in fill bufferL1D_CACHE_PREFETCH_LOCK_FB_HITL1D prefetch load lock accepted in fill bufferL1D_CACHE_STL1 data cache storesL1D_PREFETCHL1D hardware prefetchL1D_WB_L2L1 writebacks to L2L1IL1I instruction fetchesL1I_OPPORTUNISTIC_HITSOpportunistic hits in streamingL2_DATA_RQSTSL2 data requestsL2_HW_PREFETCHL2 HW prefetchesL2_LINES_INL2_LINES_OUTL2_RQSTSL2_TRANSACTIONSL2 transactionsL2_WRITEL2 demand lock/store RFOLARGE_ITLBLarge instruction TLBLOAD_DISPATCHLoads dispatchedLOAD_HIT_PRELoad operations conflicting with software prefetchesLONGEST_LAT_CACHELSDLoop stream detectorMACHINE_CLEARSMachine ClearMACRO_INSTSMacro-fused instructionsMEMORY_DISAMBIGUATIONMemory Disambiguation ActivityMEM_INST_RETIREDMemory instructions retiredMEM_LOAD_RETIREDRetired loadsMEM_STORE_RETIREDRetired storesMEM_UNCORE_RETIREDLoad instructions retired which hit offcoreOFFCORE_REQUESTSOffcore memory requestsOFFCORE_REQUESTS_SQ_FULLCounts cycles the Offcore Request buffer or Super Queue is full.PARTIAL_ADDRESS_ALIASFalse dependencies due to partial address formingPIC_ACCESSESProgrammable interrupt controllerRAT_STALLSRegister allocation table stallsRESOURCE_STALLSProcessor stallsSEG_RENAME_STALLSSegment rename stall cyclesSEGMENT_REG_LOADSCounts number of segment register loadsSIMD_INT_128128 bit SIMD integer operationsSIMD_INT_6464 bit SIMD integer operationsSNOOP_RESPONSESnoopSQ_FULL_STALL_CYCLESCounts cycles the Offcore Request buffer or Super Queue is full and request(s) are outstanding.SQ_MISCSuper Queue Activity Related to L2 Cache AccessSSE_MEM_EXECStreaming SIMD executedSSEX_UOPS_RETIREDSIMD micro-ops retiredSTORE_BLOCKSDelayed loadsTWO_UOP_INSTS_DECODEDTwo micro-ops instructions decodedUOPS_DECODED_DEC0Micro-ops decoded by decoder 0UOPS_DECODEDMicro-ops decodedUOPS_EXECUTEDMicro-ops executedUOPS_ISSUEDMicro-ops issuedUOPS_RETIREDMicro-ops retiredUOP_UNFUSIONMicro-ops unfusions due to FP exceptionsOFFCORE_RESPONSE_0Offcore response 0 (must provide at least one request and one response umasks).unknown L3 cache missminimal latency core cache hit. Request was satisfied by L1 data cachepending core cache HIT. Outstanding core cache miss to same cacheline address already underwaydata request satisfied by the L2L3 HIT. Local or remote home request that hit L3 in the uncore with no coherency actions required (snooping)L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where no modified copy was found (clean)L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where modified copies were found (HITM)reservedL3 MISS. Local homed request that missed L3 and was serviced by forwarded data following a cross package snoop where no modified copy was found (remote home requests are not counted)L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to shared state)L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to shared state)L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to exclusive state)L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to exclusive state)request to uncacheable memoryIntel NehalemnhmIntel Nehalem EXnhm_exESP_FOLDINGStack pointer instructions decodedESP_SYNCStack pointer sync operationsMSCounts the number of uops decoded by the Microcode Sequencer (MS). The MS delivers uops when the instruction is more than 4 uops long or a microcode assist is occurring.MS_CYCLES_ACTIVEUops decoded by Microcode SequencerMS:c=1STALL_CYCLESCycles no Uops are decodedEARLYEarly Branch Prediction Unit clearsLATELate Branch Prediction Unit clearsANYUops retired (Precise Event)MACRO_FUSEDMacro-fused Uops retired (Precise Event)RETIRE_SLOTSRetirement slots used (Precise Event)Cycles Uops are not retiring (Precise Event)ANY:c=1:i=1TOTAL_CYCLESTotal cycles using precise uop retired event (Precise Event)ANY:c=16:i=1ACTIVE_CYCLESAlias for TOTAL_CYCLES (Precise Event)ANY:c=1ALL_BRANCHESMispredicted retired branch instructions (Precise Event)NEAR_CALLMispredicted near retired calls (Precise Event)CONDITIONALMispredicted conditional branches retired (Precise Event)WALK_CYCLESExtended Page Table walk cyclesPORT0Uops executed on port 0 (integer arithmetic, SIMD and FP add uops)PORT1Uops executed on port 1 (integer arithmetic, SIMD, integer shift, FP multiply, FP divide uops)PORT2_COREUops executed on port 2 on any thread (load uops) (core count only)PORT3_COREUops executed on port 3 on any thread (store uops) (core count only)PORT4_COREUops executed on port 4 on any thread (handle store values for stores on port 3) (core count only)PORT5Uops executed on port 5PORT015Uops issued on ports 0, 1 or 5PORT234_COREUops issued on ports 2, 3 or 4 on any thread (core count only)PORT015_STALL_CYCLESCycles no Uops issued on ports 0, 1 or 5PORT015:c=1:i=1CORE_ACTIVE_CYCLES_NO_PORT5Cycles in which uops are executed only on port0-4 on any thread (core count only)CORE_ACTIVE_CYCLESCycles in which uops are executed on any port any thread (core count only)CORE_STALL_CYCLESCycles in which no uops are executed on any port any thread (core count only)CORE_STALL_CYCLES_NO_PORT5Cycles in which no uops are executed on any port0-4 on any thread (core count only)CORE_STALL_COUNTNumber of transitions from stalled to uops to execute on any port any thread (core count only)CORE_STALL_CYCLES:e:t:i:c=1CORE_STALL_COUNT_NO_PORT5Number of transitions from stalled to uops to execute on ports 0-4 on any thread (core count only)CORE_STALL_CYCLES_NO_PORT5:e:t:i:c=1ANY_PInstructions Retired (Precise Event)X87Retired floating-point operations (Precise Event)MMXRetired MMX instructions (Precise Event)Total cycles (Precise Event)ANY_P:c=16:i=1Any Instruction Length Decoder stall cyclesIQ_FULL:LCP:MRU:REGENIQ_FULLInstruction Queue full stall cyclesLCPLength Change Prefix stall cyclesMRUStall cycles due to BPU MRU bypassREGENRegen stall cyclesDTLB load missesPDE_MISSDTLB load miss caused by low part of addressSTLB_HITDTLB second level hitWALK_COMPLETEDDTLB load miss page walks completeDTLB load miss page walk cyclesLARGE_WALK_COMPLETEDDTLB load miss large page walk cyclesL2 lines allocatedE_STATEL2 lines allocated in the E stateS_STATEL2 lines allocated in the S statePACKED_DOUBLESIMD Packed-Double Uops retired (Precise Event)PACKED_SINGLESIMD Packed-Single Uops retired (Precise Event)SCALAR_DOUBLESIMD Scalar-Double Uops retired (Precise Event)SCALAR_SINGLESIMD Scalar-Single Uops retired (Precise Event)VECTOR_INTEGERSIMD Vector Integer Uops retired (Precise Event)AT_RETLoads delayed with at-Retirement block codeL1D_BLOCKCacheable loads delayed with L1D block codeAll Floating Point to and from MMX transitionsTO_FPTransitions from MMX to Floating Point instructionsTO_MMXTransitions from Floating Point to MMX instructionsL1DCycles L1D lockedL1D_L2Cycles L1D and L2 lockedMISSLast level cache missREFERENCELast level cache referencePACKSIMD integer 64 bit pack operationsPACKED_ARITHSIMD integer 64 bit arithmetic operationsPACKED_LOGICALSIMD integer 64 bit logical operationsPACKED_MPYSIMD integer 64 bit packed multiply operationsPACKED_SHIFTSIMD integer 64 bit shift operationsSHUFFLE_MOVESIMD integer 64 bit shuffle/move operationsUNPACKSIMD integer 64 bit unpack operationsMispredicted branches executedCONDMispredicted conditional branches executedDIRECTMispredicted unconditional branches executedDIRECT_NEAR_CALLMispredicted non call branches executedINDIRECT_NEAR_CALLMispredicted indirect call branches executedINDIRECT_NON_CALLMispredicted indirect non call branches executedNEAR_CALLSMispredicted call branches executedNON_CALLSRETURN_NEARMispredicted return branches executedTAKENMispredicted taken branches executedBAD_TARGETBACLEAR asserted with bad target addressCLEARBACLEAR asserted, regardless of causeDTLB missesDTLB miss large page walksDTLB first level misses but second level hitDTLB miss page walksDTLB miss page walk cyclesDTLB miss caused by low part of addressLATENCY_ABOVE_THRESHOLDMemory instructions retired above programmed clocks, minimum threshold value is 3, (Precise Event and ldlat required)LOADSInstructions retired which contains a load (Precise Event)STORESInstructions retired which contains a store (Precise Event)Uops issuedCycles stalled no issued uopsFUSEDFused Uops issuedCYCLES_ALL_THREADSCycles uops issued on either threads (core count)ANY:c=1:t=1Cycles no uops issued on any threads (core count)ANY:c=1:i=1:t=1IFETCH_HITL2 instruction fetch hitsIFETCH_MISSL2 instruction fetch missesIFETCHESL2 instruction fetchesLD_HITL2 load hitsLD_MISSL2 load missesL2 requestsAll L2 missesPREFETCH_HITL2 prefetch hitsPREFETCH_MISSL2 prefetch missesPREFETCHESAll L2 prefetchesREFERENCESAll L2 requestsRFO_HITL2 RFO hitsRFO_MISSL2 RFO missesRFOSL2 RFO requestsAll loads dispatchedRSNumber of loads dispatched from the Reservation Station (RS) that bypass the Memory Order BufferRS_DELAYEDNumber of delayed RS dispatches at the stage latchMOBNumber of loads dispatched from Reservation Station (RS)CODESnoop code requestsDATASnoop data requestsINVALIDATESnoop invalidate requestsAll offcore requestsANY_READOffcore read requestsANY_RFOOffcore RFO requestsDEMAND_READ_CODEOffcore demand code read requestsDEMAND_READ_DATAOffcore demand data read requestsDEMAND_RFOOffcore demand RFO requestsL1D_WRITEBACKOffcore L1 data cache writebacksOVERLAP_STORELoads that partially overlap an earlier storeSTOREStore referenced with misaligned addressMEM_ORDERExecution pipeline restart due to Memory ordering conflicts CYCLESCycles machine clear is assertedSMCSelf-modifying code detectedMMX UopsSSE_DOUBLE_PRECISIONSSE FP double precision UopsSSE_FPSSE and SSE2 FP UopsSSE_FP_PACKEDSSE FP packed UopsSSE_FP_SCALARSSE FP scalar UopsSSE_SINGLE_PRECISIONSSE FP single precision UopsSSE2_INTEGERSSE2 integer UopsComputational floating-point operations executedRetired branch instructions (Precise Event)Retired conditional branch instructions (Precise Event)Retired near call instructions (Precise Event)HITLarge ITLB hitUOPSCounts the number of micro-ops delivered by LSDACTIVECycles is which at least one micro-op delivered by LSDUOPS:c=1INACTIVECycles is which no micro-op is delivered by LSDUOPS:c=1:i=1L2 lines evictedDEMAND_CLEANL2 lines evicted by a demand requestDEMAND_DIRTYL2 modified lines evicted by a demand requestPREFETCH_CLEANL2 lines evicted by a prefetch requestPREFETCH_DIRTYL2 modified lines evicted by a prefetch requestITLB missITLB miss page walksITLB miss page walk cyclesNumber of completed large page walks due to misses in the STLBITLB misses hitting second level TLBL1D hardware prefetch missesREQUESTSL1D hardware prefetch requestsTRIGGERSL1D hardware prefetch requests triggeredLRU_HINTSSuper Queue LRU hints sent to LLCSPLIT_LOCKSuper Queue lock splits across a cache lineALLAll X87 Floating point assists (Precise Event)INPUTX87 Floating point assists for invalid input value (Precise Event)OUTPUTX87 Floating point assists for invalid output value (Precise Event)128 bit SIMD integer pack operations128 bit SIMD integer arithmetic operations128 bit SIMD integer logical operations128 bit SIMD integer multiply operations128 bit SIMD integer shift operations128 bit SIMD integer shuffle/move operations128 bit SIMD integer unpack operationsOutstanding offcore readsOutstanding offcore demand code readsOutstanding offcore demand data readsOutstanding offcore demand RFOsANY_READ_NOT_EMPTYNumber of cycles with offcore reads busyANY_READ:c=1READ_DATA_NOT_EMPTYNumber of cycles with offcore demand data reads busyDEMAND_READ_DATA:c=1READ_CODE_NOT_EMPTYNumber of cycles with offcore code reads busyDEMAND_READ_CODE:c=1RFO_NOT_EMPTYNumber of cycles with offcore rfo busyDEMAND_RFO:c=1DTLB_MISSRetired stores that miss the DTLB (Precise Event)DEC0Instructions that must be decoded by decoder 0DECODEDInstructions decodedCYCLES_DIV_BUSYCounts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Count may be incorrect when HT is onDIVCounts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Count may be incorrect when HT is onCYCLES_DIV_BUSY:c=1:i=1:e=1MULCounts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. Count may be incorrect when HT is onAll L2 transactionsFILLL2 fill transactionsIFETCHL2 instruction fetch transactionsL1D_WBL1D writeback to L2 transactionsLOADL2 Load transactionsPREFETCHL2 prefetch transactionsRFOL2 RFO transactionsWBL2 writeback to LLC transactionsAll Store buffer stall cyclesLOCAL_HITMLoad instructions retired that HIT modified data in sibling core (Precise Event)LOCAL_DRAM_AND_REMOTE_CACHE_HITLoad instructions retired local dram and remote cache HIT data sources (Precise Event)REMOTE_DRAMLoad instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)UNCACHEABLELoad instructions retired IO (Precise Event)REMOTE_HITMRetired loads that hit remote socket in modified state (Precise Event)OTHER_LLC_MISSLoad instructions retired other LLC miss (Precise Event)UNKNOWN_SOURCELoad instructions retired unknown LLC miss (Precise Event)LOCAL_DRAMRetired loads with a data source of local DRAM or locally homed remote cache HITM (Precise Event)OTHER_CORE_L2_HITMRetired loads instruction that hit modified data in sibling core (Precise Event)REMOTE_CACHE_LOCAL_HOME_HITRetired loads instruction that hit remote cache hit data source (Precise Event)Retired loads instruction remote DRAM and remote home-remote cache HITM (Precise Event)All L2 data requestsDEMAND_E_STATEL2 data demand loads in E stateDEMAND_I_STATEL2 data demand loads in I state (misses)DEMAND_M_STATEL2 data demand loads in M stateDEMAND_MESIL2 data demand requestsDEMAND_S_STATEL2 data demand loads in S statePREFETCH_E_STATEL2 data prefetches in E statePREFETCH_I_STATEL2 data prefetches in the I state (misses)PREFETCH_M_STATEL2 data prefetches in M statePREFETCH_MESIAll L2 data prefetchesPREFETCH_S_STATEL2 data prefetches in the S stateBranch instructions executedConditional branch instructions executedUnconditional branches executedUnconditional call branches executedIndirect call branches executedIndirect non call branches executedCall branches executedAll non call branches executedIndirect return branches executedTaken branches executedOutstanding snoop code requestsCODE_NOT_EMPTYCycles snoop code requests queue not emptyCODE:c=1Outstanding snoop data requestsDATA_NOT_EMPTYCycles snoop data requests queue not emptyDATA:c=1Outstanding snoop invalidate requestsINVALIDATE_NOT_EMPTYCycles snoop invalidate requests queue not emptyINVALIDATE:c=1Retired loads that miss the DTLB (Precise Event)HIT_LFBRetired loads that miss L1D and hit an previously allocated LFB (Precise Event)L1D_HITRetired loads that hit the L1 data cache (Precise Event)L2_HITRetired loads that hit the L2 cache (Precise Event)L3_MISSRetired loads that miss the LLC cache (Precise Event)LLC_MISSThis is an alias for L3_MISSL3_UNSHARED_HITRetired loads that hit valid versions in the LLC cache (Precise Event)LLC_UNSHARED_HITThis is an alias for L3_UNSHARED_HITOTHER_CORE_L2_HIT_HITMRetired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)CYCLES_STALLEDL1I instruction fetch stall cyclesHITSL1I instruction fetch hitsMISSESL1I instruction fetch missesREADSL1I Instruction fetchesLOCK_E_STATEL2 demand lock RFOs in E stateLOCK_HITAll demand L2 lock RFOs that hit the cacheLOCK_I_STATEL2 demand lock RFOs in I state (misses)LOCK_M_STATEL2 demand lock RFOs in M stateLOCK_MESIAll demand L2 lock RFOsLOCK_S_STATEL2 demand lock RFOs in S stateAll L2 demand store RFOs that hit the cacheRFO_I_STATEL2 demand store RFOs in I state (misses)RFO_M_STATEL2 demand store RFOs in M stateRFO_MESIAll L2 demand store RFOsRFO_S_STATEL2 demand store RFOs in S stateThread responded HIT to snoopHITEThread responded HITE to snoopHITMThread responded HITM to snoopM_EVICTL1D cache lines replaced in M state M_REPLL1D cache lines allocated in the M stateM_SNOOP_EVICTL1D snoop eviction of cache lines in M stateREPLL1 data cache lines allocatedResource related stall cyclesFPCWFPU control word write stall cyclesLoad buffer stall cyclesMXCSRMXCSR rename stall cyclesOTHEROther Resource related stall cyclesROB_FULLROB full stall cyclesRS_FULLReservation Station full stall cyclesStore buffer stall cyclesAll RAT stall cyclesFLAGS:REGISTERS:ROB_READ_PORT:SCOREBOARDFLAGSFlag stall cyclesREGISTERSPartial register stall cyclesROB_READ_PORTROB read port stalls cyclesSCOREBOARDScoreboard stall cyclesTHREAD_PCycles when thread is not halted (programmable counter)REF_PReference base clock (133 Mhz) cycles when thread is not haltedTotal number of elapsed cycles. Does not work when C-state enabledTHREAD_P:c=2:i=1L1 writebacks to L2 in E stateI_STATEL1 writebacks to L2 in I state (misses)M_STATEL1 writebacks to L2 in M stateMESIAll L1 writebacks to L2L1 writebacks to L2 in S stateDMND_DATA_RDRequest: counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFODMND_IFETCHRequest: counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesRequest: counts the number of writeback (modified to exclusive) transactionsPF_DATA_RDRequest: counts the number of data cacheline reads generated by L2 prefetchersPF_RFORequest: counts the number of RFO requests generated by L2 prefetchersPF_IFETCHRequest: counts the number of code reads generated by L2 prefetchersRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockANY_IFETCHRequest: combination of PF_IFETCH | DMND_IFETCHPF_IFETCH:DMND_IFETCHANY_REQUESTRequest: combination of all requests umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:OTHERANY_DATARequest: any data read/write requestDMND_DATA_RD:PF_DATA_RD:DMND_RFO:PF_RFOANY_DATA_RDRequest: any data read in requestDMND_DATA_RD:PF_DATA_RDRequest: combination of DMND_RFO | PF_RFODMND_RFO:PF_RFOUNCORE_HITResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)OTHER_CORE_HIT_SNPResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)OTHER_CORE_HITMResponse: counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)REMOTE_CACHE_HITMResponse: counts L3 Hit: local or remote home requests that hit a remote L3 cacheline in modified (HITM) stateREMOTE_CACHE_FWDResponse: counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)Response: counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM or a remote cacheResponse: counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAMResponse: counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAMResponse: counts L3 Miss: remote home requests that missed the L3 cacheNON_DRAMResponse: Non-DRAM requests that were serviced by IOHANY_CACHE_DRAMResponse: requests serviced by any source but IOHUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_FWD:REMOTE_CACHE_HITM:REMOTE_DRAM:LOCAL_DRAMUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:OTHER_LLC_MISS:REMOTE_DRAM:LOCAL_DRAM_AND_REMOTE_CACHE_HITANY_DRAMResponse: requests serviced by local or remote DRAMREMOTE_DRAM:LOCAL_DRAMANY_LLC_MISSResponse: requests that missed in L3REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAMREMOTE_CACHE_HITM:REMOTE_DRAM:OTHER_LLC_MISS:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:NON_DRAMLOCAL_CACHE_DRAMResponse: requests hit local core or uncore caches or local DRAMUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:LOCAL_DRAMREMOTE_CACHE_DRAMResponse: requests that miss L3 and hit remote caches or DRAMREMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAMLOCAL_CACHEResponse: any local (core and socket) cachesUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITMANY_RESPONSEResponse: combination of all response umasksUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:REMOTE_CACHE_FWD:REMOTE_DRAM:LOCAL_DRAM:NON_DRAMUNCORE_HIT:OTHER_CORE_HIT_SNP:OTHER_CORE_HITM:REMOTE_CACHE_HITM:REMOTE_DRAM:OTHER_LLC_MISS:LOCAL_DRAM_AND_REMOTE_CACHE_HIT:NON_DRAMUNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted).INSTRUCTION_RETIREDCount the number of instructions at retirement.INSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDUNHALTED_REFERENCE_CYCLESUnhalted reference cyclesLLC_REFERENCESCount each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch (Alias for L3_LAT_CACHE:REFERENCE).L3_LAT_CACHE:REFERENCELAST_LEVEL_CACHE_REFERENCESThis is an alias for L3_LAT_CACHE:REFERENCELLC_MISSESCount each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch (Alias for L3_LAT_CACHE:MISS)L3_LAT_CACHE:MISSLAST_LEVEL_CACHE_MISSESThis is an alias for L3_LAT_CACHE:MISSBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction.BR_INST_RETIRED:ALL_BRANCHESUOPS_DECODEDMicro-ops decodedL1D_CACHE_LOCK_FB_HITL1D cacheable load lock speculated or retired accepted into the fill bufferBPU_CLEARSBranch Prediction Unit clearsUOPS_RETIREDCycles Uops are being retired (Precise Event)BR_MISP_RETIREDMispredicted retired branches (Precise Event)EPTExtended Page TableUOPS_EXECUTEDMicro-ops executedIO_TRANSACTIONSI/O transactionsES_REG_RENAMESES segment renamesINST_RETIREDInstructions retired (Precise Event)ILD_STALLInstruction Length Decoder stallsDTLB_LOAD_MISSESL2_LINES_INSSEX_UOPS_RETIREDSIMD micro-ops retired (Precise Event)STORE_BLOCKSLoad delayed by block codeFP_MMX_TRANSFloating Point to and from MMX transitionsCACHE_LOCK_CYCLESCache lockedOFFCORE_REQUESTS_SQ_FULLOffcore requests blocked due to Super Queue fullLONGEST_LAT_CACHELast level cache accessesL3_LAT_CACHESIMD_INT_64SIMD 64-bit integer operationsBR_INST_DECODEDBranch instructions decodedBR_MISP_EXECSQ_FULL_STALL_CYCLESSuper Queue full stall cyclesBACLEARBranch address calculator clearsDTLB_MISSESData TLB missesMEM_INST_RETIREDMemory instructions retired (Precise Event)UOPS_ISSUEDL2_RQSTSTWO_UOP_INSTS_DECODEDTwo Uop instructions decodedLOAD_DISPATCHLoads dispatchedBACLEAR_FORCE_IQBACLEAR forced by Instruction queueSNOOPQ_REQUESTSSnoopq requestsOFFCORE_REQUESTSOffcore requestsLOAD_BLOCKLoads blockedMISALIGN_MEMORYMisaligned accessesINST_QUEUE_WRITE_CYCLESCycles instructions are written to the instruction queueLSD_OVERFLOWNumber of loops that cannot stream from the instruction queue.MACHINE_CLEARSMachine clear assertedFP_COMP_OPS_EXESSE/MMX micro-opsITLB_FLUSHITLB flushesBR_INST_RETIREDL1D_CACHE_PREFETCH_LOCK_FB_HITL1D prefetch load lock accepted in fill bufferLARGE_ITLBLarge ITLB accessesLSDLoop stream detectorL2_LINES_OUTITLB_MISSESL1D_PREFETCHL1D hardware prefetchSQ_MISCSuper Queue miscellaneousSEG_RENAME_STALLSSegment rename stall cyclesFP_ASSISTX87 Floating point assists (Precise Event)SIMD_INT_128128 bit SIMD operationsOFFCORE_REQUESTS_OUTSTANDINGOutstanding offcore requestsMEM_STORE_RETIREDRetired storesINST_DECODEDMACRO_INSTS_FUSIONS_DECODEDCount the number of instructions decoded that are macros-fused but not necessarily executed or retiredMACRO_INSTSMacro-instructionsPARTIAL_ADDRESS_ALIASFalse dependencies due to partial address aliasingARITHCounts arithmetic multiply and divide operationsL2_TRANSACTIONSL2 transactionsINST_QUEUE_WRITESInstructions written to instruction queue.SB_DRAINStore bufferLOAD_HIT_PRELoad operations conflicting with software prefetchesMEM_UNCORE_RETIREDLoad instructions retired (Precise Event)L2_DATA_RQSTSBR_INST_EXECITLB_MISS_RETIREDRetired instructions that missed the ITLB (Precise Event)BPU_MISSED_CALL_RETBranch prediction unit missed call or returnSNOOPQ_REQUESTS_OUTSTANDINGOutstanding snoop requestsMEM_LOAD_RETIREDMemory loads retired (Precise Event)L1IL1I instruction fetchL2_WRITEL2 demand lock/store RFOSNOOP_RESPONSESnoopL1D cacheRESOURCE_STALLSRAT_STALLSCPU_CLK_UNHALTEDCycles when processor is not in halted stateL1D_WB_L2L1D writebacks to L2MISPREDICTED_BRANCH_RETIREDCount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwareBR_MISP_RETIRED:ALL_BRANCHESTHREAD_ACTIVECycles thread is activeUOP_UNFUSIONCounts unfusion events due to floating point exception to a fused uopOFFCORE_RESPONSE_0Offcore response 0 (must provide at least one request and one response umasks)OFFCORE_RESPONSE_1Offcore response 1 (must provide at least one request and one response umasks)%,/Intel Westmere (single-socket)wsmIntel Westmere DPwsm_dpCOUNTThis event counts executed load operationsFPU_DIV_ACTIVECycles that the divider is active, includes integer and floating pointFPU_DIVNumber of cycles the divider is activated, includes integer and floating pointFPU_DIV_ACTIVE:c=1:e=1NONTAKEN_CONDAll macro conditional non-taken branch instructionsTAKEN_CONDAll macro conditional taken branch instructionsTAKEN_DIRECT_JUMPAll macro unconditional taken branch instructions, excluding calls and indirectsTAKEN_INDIRECT_JUMP_NON_CALL_RETAll taken indirect branches that are not calls nor returnsTAKEN_RETURN_NEARAll taken indirect branches that have a return mnemonicTAKEN_DIRECT_NEAR_CALLAll taken non-indirect callsTAKEN_INDIRECT_NEAR_CALLAll taken indirect calls, including both register and memory indirectALL_BRANCHESAll near executed branches instructions (not necessarily retired)ALL_CONDITIONALAll macro conditional branch instructionsANY_CONDANY_INDIRECT_JUMP_NON_CALL_RETAll indirect branches that are not calls nor returnsANY_DIRECT_NEAR_CALLAll non-indirect callsALL_DIRECT_JMPSpeculative and retired macro-unconditional branches excluding calls and indirectsALL_INDIRECT_NEAR_RETURNSpeculative and retired indirect return branchesAll taken and not taken macro branches including far branches (Precise Event)CONDITIONALAll taken and not taken macro conditional branch instructions (Precise Event)FAR_BRANCHNumber of far branch instructions retired (Precise Event)NEAR_CALLAll macro direct and indirect near calls, does not count far calls (Precise Event)NEAR_RETURNNumber of near ret instructions retired (Precise Event)NEAR_TAKENNumber of near branch taken instructions retired (Precise Event)NOT_TAKENAll not taken macro branch instructions retired (Precise Event)All non-taken mispredicted macro conditional branch instructionsAll taken mispredicted macro conditional branch instructionsAll taken mispredicted indirect branches that are not calls nor returnsAll taken mispredicted indirect branches that have a return mnemonicAll taken mispredicted non-indirect callsAll taken mispredicted indirect calls, including both register and memory indirectAll mispredicted macro conditional branch instructionsAll mispredicted non-indirect callsAll mispredicted indirect branches that are not calls nor returnsAll mispredicted branch instructionsAll mispredicted macro branches (Precise Event)All mispredicted macro conditional branch instructions (Precise Event)All macro direct and indirect near calls (Precise Event)Number of branch instructions retired that were mispredicted and not-taken (Precise Event)TAKENNumber of branch instructions retired that were mispredicted and taken (Precise Event)SPLIT_LOCK_UC_LOCK_DURATIONCycles in which the L1D and L2 are locked, due to a UC lock or split lockCACHE_LOCK_DURATIONCycles in which the L1D is lockedRING0Unhalted core cycles the thread was in ring 0RING0_TRANSTransitions from rings 1, 2, or 3 to ring 0RING0:c=1:e=1RING123Unhalted core cycles the thread was in rings 1, 2, or 3REF_PCycles when the core is unhalted (count at 100 Mhz)REF_XCLKCount Xclk pulses (100Mhz) when the core is unhaltedREF_XCLK_ANYCount Xclk pulses (100Mhz) when the at least one thread on the physical core is unhaltedREF_XCLK:tTHREAD_PCycles when thread is not haltedONE_THREAD_ACTIVECounts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is haltedNumber of DSB to MITE switchesPENALTY_CYCLESCycles SB to MITE switches caused delayALL_CANCELNumber of times a valid DSB fill has been cancelled for any reasonEXCEED_DSB_LINESDSB Fill encountered > 3 DSB linesOTHER_CANCELNumber of times a valid DSB fill has been cancelled not because of exceeding way limitMISS_CAUSES_A_WALKDemand load miss in all TLB levels which causes an page walk of any page sizeCAUSES_A_WALKSTLB_HITNumber of DTLB lookups for loads which missed first level DTLB but hit second level DTLB (STLB); No page walk.WALK_COMPLETEDDemand load miss in all TLB levels which causes a page walk that completes for any page sizeWALK_DURATIONCycles PMH is busy with a walkMiss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G)First level miss but second level hit; no page walk. Only relevant if multiple levelsMiss in all TLB levels that causes a page walk that completes of any page size (4K/2M/4M/1G)Cycles PMH is busy with this walkANYCycles with any input/output SSE or FP assistsSIMD_INPUTNumber of SIMD FP assists due to input valuesSIMD_OUTPUTNumber of SIMD FP assists due to output valuesX87_INPUTNumber of X87 assists due to input valueX87_OUTPUTNumber of X87 assists due to output valueALLCycles with any input and output SSE or FP assistX87Number of X87 uops executedSSE_FP_PACKED_DOUBLENumber of SSE double precision FP packed uops executedSSE_FP_SCALAR_SINGLENumber of SSE single precision FP scalar uops executedSSE_PACKED_SINGLENumber of SSE single precision FP packed uops executedSSE_SCALAR_DOUBLENumber of SSE double precision FP scalar uops executedL1D_MISSHardware prefetch requests that misses the L1D cache. A request is counted each time it accesses the cache and misses it, including if a block is applicable or if it hits the full buffer, for example. This accounts for both L1 streamer and IP-based Hw prefetchersMISSESNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accessesHITNumber of Instruction Cache, Streaming Buffer and Victim Cache Reads. Includes cacheable and uncacheable accesses and uncacheable fetchesEMPTYCycles IDQ is emptyMITE_UOPSNumber of uops delivered to IDQ from MITE pathDSB_UOPSNumber of uops delivered to IDQ from DSB pathMS_DSB_UOPSNumber of uops delivered to IDQ when MS busy by DSBMS_MITE_UOPSNumber of uops delivered to IDQ when MS busy by MITEMS_UOPSNumber of uops were delivered to IDQ from MS by either DSB or MITEMITE_UOPS_CYCLESCycles where uops are delivered to IDQ from MITE (MITE active)MITE_UOPS:c=1MS_SWITCHESNumber of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITEMS_UOPS:c=1:eDSB_UOPS_CYCLESCycles where uops are delivered to IDQ from DSB (DSB active)MS_DSB_UOPS_CYCLESCycles where uops delivered to IDQ when MS busy by DSBMS_DSB_UOPS:c=1MS_MITE_UOPS_CYCLESCycles where uops delivered to IDQ when MS busy by MITEMS_MITE_UOPS:c=1MS_UOPS_CYCLESCycles where uops delivered to IDQ from MS by either BSD or MITEMS_UOPS:c=1ALL_DSB_UOPSNumber of uops deliver from either DSB pathsALL_DSB_CYCLESCycles MITE/MS deliver anythingALL_DSB_CYCLES_4_UOPSCycles Decode Stream Buffer (DSB) is delivering 4 UopsALL_MITE_UOPSNumber of uops delivered from either MITE pathsALL_MITE_CYCLESCycles DSB/MS deliver anythingALL_MITE_CYCLES_4_UOPSCycles MITE is delivering 4 UopsANY_UOPSNumber of uops delivered to IDQ from any pathMS_DSB_UOPS_OCCUROccurrences of DSB MS going activeMS_DSB_UOPS:c=1:e=1CORENumber of non-delivered uops to RAT (use cmask to qualify further)CYCLES_0_UOPS_DELIV_CORECycles per thread when 4 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalledCORE:c=4CYCLES_GE_1_UOP_DELIV_CORECycles per thread when 1 or more uops are delivered to the Resource Allocation Table (RAT) by the front endCORE:c=4:iCYCLES_LE_1_UOP_DELIV_CORECycles per thread when 3 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalledCORE:c=3CYCLES_LE_2_UOP_DELIV_CORECycles with less than 2 uops delivered by the front endCORE:c=2CYCLES_LE_3_UOP_DELIV_CORECycles with less than 3 uops delivered by the front endCORE:c=1CYCLES_FE_WAS_OKCycles Front-End (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling FECORE:c=1:iLCPStall caused by changing prefix length of the instructionIQ_FULLStall cycles due to IQ fullINSTSNumber of instructions written to IQ every cycleANY_PNumber of instructions retiredPREC_DISTPrecise instruction retired event to reduce effect of PEBS shadow IP distribution (Precise Event)RAT_STALL_CYCLESCycles RAT external stall is sent to IDQ for this threadRECOVERY_CYCLESCycles waiting to be recovered after Machine Clears due to all other cases except JEClearRECOVERY_STALLS_COUNTNumber of times need to wait after Machine Clears due to all other cases except JEClearRECOVERY_CYCLES_ANYCycles during which the allocator was stalled due to recovery from earlier clear event for any thread (e.g. misprediction or memory nuke)ITLB_FLUSHNumber of ITLB flushes, includes 4k/2M/4M pagesFLUSHALLOCATED_IN_MNumber of allocations of L1D cache lines in modified (M) stateALL_M_REPLACEMENTNumber of cache lines in M-state evicted of L1D due to snoop HITM or dirty line replacementM_EVICTNumber of modified lines evicted from L1D due to replacementREPLACEMENTNumber of cache lines brought into the L1D cacheBANK_CONFLICTNumber of dispatched loads cancelled due to L1D bank conflicts with other load portsBANK_CONFLICT_CYCLESCycles when dispatched loads are cancelled due to L1D bank conflicts with other load portsBANK_CONFLICT:c=1OCCURRENCESOccurrences of L1D_PEND_MISS going activePENDING:e=1:c=1EDGEPENDINGNumber of L1D load misses outstanding every cyclePENDING_CYCLESCycles with L1D load misses outstandingPENDING:c=1PENDING_CYCLES_ANYCycles with L1D load misses outstanding from any threadPENDING:c=1:tFB_FULLNumber of cycles a demand request was blocked due to Fill Buffer (FB) unavailabilityNon rejected writebacks from L1D to L2 cache lines in E stateHIT_EHIT_MNon rejected writebacks from L1D to L2 cache lines in M stateHIT_SNon rejected writebacks from L1D to L2 cache lines in S stateMISSNumber of modified lines evicted from L1 and missing L2 (non-rejected WB from DCU)L2 cache lines filling (counting does not cover rejects)EL2 cache lines in E state (counting does not cover rejects)IL2 cache lines in I state (counting does not cover rejects)SL2 cache lines in S state (counting does not cover rejects)DEMAND_CLEANL2 clean line evicted by a demandDEMAND_DIRTYL2 dirty line evicted by a demandPREFETCH_CLEANL2 clean line evicted by a prefetchPREFETCH_DIRTYL2 dirty line evicted by an MLC PrefetchDIRTY_ANYAny L2 dirty line evicted (does not cover rejects)ALL_CODE_RDAny ifetch request to L2 cacheCODE_RD_HITL2 cache hits when fetching instructionsCODE_RD_MISSL2 cache misses when fetching instructionsALL_DEMAND_DATA_RDDemand data read requests to L2 cacheALL_DEMAND_RD_HITDemand data read requests that hit L2ALL_PFAny L2 HW prefetch request to L2 cachePF_HITRequests from the L2 hardware prefetchers that hit L2 cachePF_MISSRequests from the L2 hardware prefetchers that miss L2 cacheRFO_ANYAny RFO requests to L2 cacheRFO_HITSRFO requests that hit L2 cacheRFO_MISSRFO requests that miss L2 cacheRFOs that hit cache lines in E stateRFOs that miss cache (I state)RFOs that hit cache lines in M stateRFOs that access cache lines in any stateTransactions accessing MLC pipeCODE_RDL2 cache accesses when fetching instructionsL1D_WBL1D writebacks that access L2 cacheLOADDemand Data Read* requests that access L2 cacheL2_FILLL2 fill requests that access L2 cacheL2_WBL2 writebacks that access L2 cacheALL_PREFETCHL2 or L3 HW prefetches that access L2 cache (including rejects)RFORFO requests that access L2 cacheDATA_UNKNOWNBlocked loads due to store buffer blocks with unknown dataSTORE_FORWARDLoads blocked by overlapping with store buffer that cannot be forwardedNO_SRNumber of split loads blocked due to resource not availableALL_BLOCKNumber of cases where any load is blocked but has not DCU missADDRESS_ALIASFalse dependencies in MOB due to partial compare on addressALL_STA_BLOCKNumber of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this typeHW_PFNon sw-prefetch load dispatches that hit the fill buffer allocated for HW prefetchSW_PFNon sw-prefetch load dispatches that hit the fill buffer allocated for SW prefetchCore-originated cacheable demand requests missed L3REFERENCECore-originated cacheable demand requests that refer to L3MASKMOVThe number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0MEMORY_ORDERINGNumber of Memory Ordering Machine Clears detectedSMCSelf-Modifying Code detectedNumber of machine clears (nukes) of any typeXSNP_HITLoad LLC Hit and a cross-core Snoop hits in on-pkg core cache (Precise Event)XSNP_HITMLoad had HitM Response from a core on same socket (shared LLC) (Precise Event)XSNP_MISSLoad LLC Hit and a cross-core Snoop missed in on-pkg core cache (Precise Event)XSNP_NONELoad hit in last-level (L3) cache with no snoop needed (Precise Event)LLC_MISSCounts load driven L3 misses and some non simd split loads (Precise Event)HIT_LFBA load missed L1D but hit the Fill Buffer (Precise Event)L1_HITLoad hit in nearest-level (L1D) cache (Precise Event)L2_HITLoad hit in mid-level (L2) cache (Precise Event)L3_HITL3_MISSRetired load uops which data sources were data missed LLC (excluding unknown data source)LATENCY_ABOVE_THRESHOLDMemory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)PRECISE_STORECapture where stores occur, must use with PEBS (Precise Event required)ALL_LOADSAny retired loads (Precise Event)ANY_LOADSALL_STORESAny retired stores (Precise Event)ANY_STORESLOCK_LOADSLocked retired loads (Precise Event)LOCK_STORESLocked retired stores (Precise Event)SPLIT_LOADSRetired loads causing cacheline splits (Precise Event)SPLIT_STORESRetired stores causing cacheline splits (Precise Event)STLB_MISS_LOADSSTLB misses dues to retired loads (Precise Event)STLB_MISS_STORESSTLB misses dues to retired stores (Precise Event)LOADSSpeculative cache-line split load uops dispatched to the L1DSTORESSpeculative cache-line split Store-address uops dispatched to L1DALL_DATA_RDDemand and prefetch read requests sent to uncoreALL_DATA_READDEMAND_CODE_RDOffcore code read requests, including cacheable and un-cacheablesDEMAND_DATA_RDDemand Data Read requests sent to uncoreDEMAND_RFOOffcore Demand RFOs, includes regular RFO, Locks, ItoMSQ_FULLOffcore requests buffer cannot take more entries for this thread coreALL_DATA_RD_CYCLESCycles with cacheable data read transactions in the superQALL_DATA_RD:c=1DEMAND_CODE_RD_CYCLESCycles with demand code reads transactions in the superQDEMAND_CODE_RD:c=1DEMAND_DATA_RD_CYCLESCycles with demand data read transactions in the superQDEMAND_DATA_RD:c=1Cacheable data read transactions in the superQ every cycleCode read transactions in the superQ every cycleDemand data read transactions in the superQ every cycleDEMAND_DATA_RD_GE_6Cycles with at lesat 6 offcore outstanding demand data read requests in the uncore queueDEMAND_DATA_RD:c=6Outstanding RFO (store) transactions in the superQ every cycleDEMAND_RFO_CYCLESCycles with outstanding RFO (store) transactions in the superQDEMAND_RFO:c=1ITLB_MISS_RETIREDNumber of instructions that experienced an ITLB missAVX_TO_SSENumber of transitions from AVX-256 to legacy SSE when penalty applicableSSE_TO_AVXNumber of transitions from legacy SSE to AVX-256 when penalty applicableAVX_STORENumber of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operationsFLAGS_MERGE_UOPNumber of flags-merge uops in flight in each cycleCYCLES_FLAGS_MERGE_UOPCycles in which flags-merge uops in flightFLAGS_MERGE_UOP:c=1MUL_SINGLE_UOPNumber of Multiply packed/scalar single precision uops allocatedSLOW_LEA_WINDOWNumber of cycles with at least one slow LEA uop allocatedCycles stalled due to Resource Related reasonLBCycles stalled due to lack of load buffersRSCycles stalled due to no eligible RS entry availableSBCycles stalled due to no store buffers available (not including draining from sync)ROBCycles stalled due to re-order buffer fullFCSWCycles stalled due to writing the FPU control wordMXCSRCycles stalled due to the MXCSR register ranme occurring too close to a previous MXCSR renameMEM_RSCycles stalled due to LB, SB or RS being completely in useLB:SB:RSLD_SBResource stalls due to load or store buffers all being in useOOO_SRCResource stalls due to Rob being full, FCSW, MXCSR and OTHERALL_FL_EMPTYCycles stalled due to free list emptyALL_PRF_CONTROLCycles stalls due to control structures full for physical registersANY_PRF_CONTROLBOB_FULLCycles Allocator is stalled due Branch Order BufferOOO_RSRCCycles stalled due to out of order resources fullLBR_INSERTSCount each time an new LBR record is saved by HWEMPTY_CYCLESCycles the RS is empty for this threadEMPTY_ENDCounts number of time the Reservation Station (RS) goes from empty to non-emptyEMPTY_CYCLES:c=1:e:iPACKED_SINGLECounts 256-bit packed single-precisionPACKED_DOUBLECounts 256-bit packed double-precisionSPLIT_LOCKSplit locks in SQDTLB_THREADNumber of DTLB flushes of thread-specific entriesSTLB_ANYNumber of STLB flushesPORT_0Cycles which a Uop is dispatched on port 0PORT_1Cycles which a Uop is dispatched on port 1PORT_2_LDCycles in which a load uop is dispatched on port 2PORT_2_STACycles in which a store uop is dispatched on port 2PORT_2Cycles in which a uop is dispatched on port 2PORT_3Cycles in which a uop is dispatched on port 3PORT_4Cycles which a uop is dispatched on port 4PORT_5Cycles which a Uop is dispatched on port 5PORT_0_CORECycles in which a uop is dispatched on port 0 for any threadPORT_0:tPORT_1_CORECycles in which a uop is dispatched on port 1 for any threadPORT_1:tPORT_2_CORECycles in which a uop is dispatched on port 2 for any threadPORT_2:tPORT_3_CORECycles in which a uop is dispatched on port 3 for any threadPORT_3:tPORT_4_CORECycles in which a uop is dispatched on port 4 for any threadPORT_4:tPORT_5_CORECycles in which a uop is dispatched on port 5 for any threadPORT_5:tNumber of uops issued by the RAT to the Reservation Station (RS)CORE_STALL_CYCLESCycles no uops issued on this core (by any thread)ANY:c=1:i=1:t=1STALL_CYCLESCycles no uops issued by this threadANY:c=1:i=1All uops that actually retired (Precise Event)RETIRE_SLOTSNumber of retirement slots used (Precise Event)Cycles no executable uop retired (Precise Event)ALL:c=1:iTOTAL_CYCLESTotal cycles using precise uop retired event (Precise Event)ALL:c=10:iDMND_DATA_RDRequest: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetchesDMND_IFETCHRequest: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesWBRequest: number of writebacks (modified to exclusive) transactionsPF_DATA_RDRequest: number of data cacheline reads generated by L2 prefetchersPF_RFORequest: number of RFO requests generated by L2 prefetchersPF_IFETCHRequest: number of code reads generated by L2 prefetchersPF_LLC_DATA_RDRequest: number of L3 prefetcher requests to L2 for loadsPF_LLC_RFORequest: number of RFO requests generated by L2 prefetcherPF_LLC_IFETCHRequest: number of L2 prefetcher requests to L3 for instruction fetchesBUS_LOCKSRequest: number bus lock and split lock requestsSTRM_STRequest: number of streaming store requestsOTHERRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockANY_IFETCHRequest: combination of PF_IFETCH | DMND_IFETCH | PF_LLC_IFETCHPF_IFETCH:DMND_IFETCH:PF_LLC_IFETCHANY_REQUESTRequest: combination of all request umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHERANY_DATARequest: combination of DMND_DATA | PF_DATA_RD | PF_LLC_DATA_RDDMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RDANY_RFORequest: combination of DMND_RFO | PF_RFO | PF_LLC_RFODMND_RFO:PF_RFO:PF_LLC_RFOANY_RESPONSEResponse: count any response typeNO_SUPPSupplier: counts number of times supplier information is not availableLLC_HITMSupplier: counts L3 hits in M-state (initial lookup)LLC_HITESupplier: counts L3 hits in E-stateLLC_HITSSupplier: counts L3 hits in S-stateLLC_HITFSupplier: counts L3 hits in F-stateLLC_MISS_LOCAL_DRAMSupplier: counts L3 misses to local DRAMLLC_MISS_LOCALLLC_MISS_REMOTESupplier: counts L3 misses to remote DRAMLLC_MISS_REMOTE_DRAMSupplier: counts L3 misses to local or remote DRAMLLC_MISS_LOCAL:LLC_MISS_REMOTELLC_HITMESFSupplier: counts L3 hits in any state (M, E, S, F)LLC_HITM:LLC_HITE:LLC_HITS:LLC_HITFSNP_NONESnoop: counts number of times no snoop-related information is availableSNP_NOT_NEEDEDSnoop: counts the number of times no snoop was needed to satisfy the requestNO_SNP_NEEDEDSNP_MISSSnoop: counts number of times a snoop was needed and it missed all snooped cachesSNP_NO_FWDSnoop: counts number of times a snoop was needed and it hit in at leas one snooped cacheSNP_FWDSnoop: counts number of times a snoop was needed and data was forwarded from a remote socketHITMSnoop: counts number of times a snoop was needed and it hitM-ed in local or remote cacheNON_DRAMSnoop: counts number of times target was a non-DRAM system address. This includes MMIO transactionsSNP_ANYSnoop: any snoop reasonSNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:HITM:NON_DRAMCounts the number of times the front end is re-steered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front endCYCLES_L2_PENDINGCycles with pending L2 miss loadsCYCLES_L1D_PENDINGCycles with pending L1D load cache missesCYCLES_NO_DISPATCHCycles of dispatch stallsSTALLS_L2_PENDINGExecution stalls due to L2 pending loadsSTALLS_L1D_PENDINGExecution stalls due to L1D pending loadsWALK_CYCLESCycles for an extended page table walkUOPSNumber of uops delivered by the Loop Stream Detector (LSD)ACTIVECycles with uops delivered by the LSD but which did not come from decoderUOPS:c=1CYCLES_4_UOPSCycles with 4 uops delivered by the LSD but which did not come from decoderUOPS:c=4Number of page walks with a LLC missCounts total number of uops executed from any thread per cycleTHREADCounts total number of uops executed per thread each cycleNumber of cycles with no uops executedCYCLES_GE_1_UOP_EXECCycles where at least 1 uop was executed per threadCYCLES_GE_2_UOPS_EXECCycles where at least 2 uops were executed per threadCYCLES_GE_3_UOPS_EXECCycles where at least 3 uops were executed per threadCYCLES_GE_4_UOPS_EXECCycles where at least 4 uops were executed per threadCORE_CYCLES_GE_1Cycles where at least 1 uop was executed from any threadCORE_CYCLES_GE_2Cycles where at least 2 uops were executed from any threadCORE_CYCLES_GE_3Cycles where at least 3 uops were executed from any threadCORE_CYCLES_GE_4Cycles where at least 4 uops were executed from any threadCORE_CYCLES_NONECycles where no uop is executed on any threadCORE:iLOCAL_DRAMLoad uops that miss in the L3 and hit local DRAMREMOTE_DRAMLoad uops that miss in the L3 and hit remote DRAMAGU_BYPASS_CANCELNumber of executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in another pageARITHCounts arithmetic multiply operationsBACLEARSBranch re-steeredBR_INST_EXECBranch instructions executedBR_INST_RETIREDRetired branch instructionsBR_MISP_EXECMispredicted branches executedBR_MISP_RETIREDMispredicted retired branchesBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instructionBR_INST_RETIRED:ALL_BRANCHESMISPREDICTED_BRANCH_RETIREDCount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwareBR_MISP_RETIRED:ALL_BRANCHESLOCK_CYCLESLocked cycles in L1D and L2CPL_CYCLESUnhalted core cycles at a specific ring levelCPU_CLK_UNHALTEDCycles when processor is not in halted stateDSB2MITE_SWITCHESDSB_FILLDSB fillsDTLB_LOAD_MISSESData TLB load missesDTLB_STORE_MISSESData TLB store missesFP_ASSISTX87 Floating point assistsFP_COMP_OPS_EXECounts number of floating point eventsHW_PRE_REQHardware prefetch requestsICACHEInstruction Cache accessesIDQIDQ operationsIDQ_UOPS_NOT_DELIVEREDUops not deliveredILD_STALLInstruction Length Decoder stallsINSTS_WRITTEN_TO_IQInstructions written to IQINST_RETIREDInstructions retiredINSTRUCTION_RETIREDNumber of instructions at retirementINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDINT_MISCMiscellaneous internalsITLBInstruction TLBITLB_MISSESInstruction TLB missesL1DL1D cacheL1D_BLOCKSL1D is blockingL1D_PEND_MISSL1D pending missesL2_L1D_WB_RQSTSWriteback requests from L1D to L2L2_LINES_INL2 lines allocatedL2_LINES_OUTL2 lines evictedL2_RQSTSL2 requestsL2_STORE_LOCK_RQSTSL2 store lock requestsL2_TRANSL2 transactionsLAST_LEVEL_CACHE_MISSESThis is an alias for L3_LAT_CACHE:MISSL3_LAT_CACHE:MISSLLC_MISSESAlias for LAST_LEVEL_CACHE_MISSESLAST_LEVEL_CACHE_REFERENCESThis is an alias for L3_LAT_CACHE:REFERENCEL3_LAT_CACHE:REFERENCELLC_REFERENCESAlias for LAST_LEVEL_CACHE_REFERENCESLD_BLOCKSBlocking loadsLD_BLOCKS_PARTIALPartial load blocksLOAD_HIT_PRELoad dispatches that hit fill bufferL3_LAT_CACHECore-originated cacheable demand requests to L3MACHINE_CLEARSMachine clear assertedMEM_LOAD_UOPS_LLC_HIT_RETIREDL3 hit loads uops retiredMEM_LOAD_LLC_HIT_RETIREDL3 hit loads uops retired (deprecated use MEM_LOAD_UOPS_LLC_HIT_RETIRED)MEM_LOAD_UOPS_MISC_RETIREDLoads and some non simd split loads uops retiredMEM_LOAD_MISC_RETIREDLoads and some non simd split loads uops retired (deprecated use MEM_LOAD_UOPS_MISC_RETIRED)MEM_LOAD_UOPS_RETIREDMemory loads uops retiredMEM_LOAD_RETIREDMemory loads uops retired (deprecated use MEM_LOAD_UOPS_RETIRED)MEM_TRANS_RETIREDMemory transactions retiredMEM_UOPS_RETIREDMemory uops retiredMEM_UOP_RETIREDMemory uops retired (deprecated use MEM_UOPS_RETIRED)MISALIGN_MEM_REFMisaligned memory referencesOFFCORE_REQUESTSOffcore requestsOFFCORE_REQUESTS_BUFFEROffcore requests bufferOFFCORE_REQUESTS_OUTSTANDINGOutstanding offcore requestsOTHER_ASSISTSCount hardware assistsPARTIAL_RAT_STALLSPartial Register Allocation Table stallsRESOURCE_STALLSResource related stall cyclesRESOURCE_STALLS2ROB_MISC_EVENTSReorder buffer eventsRS_EVENTSReservation station eventsSIMD_FP_256Counts 256-bit packed floating point instructionsSQ_MISCSuperQ eventsTLB_FLUSHTLB flushesUNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted)UNHALTED_REFERENCE_CYCLESUnhalted reference cyclesUOPS_EXECUTEDUops executedUOPS_DISPATCHED_PORTUops dispatch to specific portsUOPS_ISSUEDUops issuedUOPS_RETIREDUops retiredCYCLE_ACTIVITYStalled cyclesEPTExtended page tableLSDLoop stream detectorPAGE_WALKSpage walkerMEM_LOAD_UOPS_LLC_MISS_RETIREDLoad uops retired which miss the L3 cacheOFFCORE_RESPONSE_0Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)OFFCORE_RESPONSE_1*-Intel Sandy BridgesnbIntel Sandy Bridge EPsnb_epMISSNumber of snoop missesINVALNumber of snoop invalidates of a non-modified lineHITNumber of snoop hits of a non-modified lineHITMNumber of snoop hits of a modified lineINVAL_MNumber of snoop invalidates of a modified lineANY_SNPNumber of snoopsEXTERNAL_FILTERFilter on cross-core snoops initiated by this Cbox due to external snoop requestXCORE_FILTERFilter on cross-core snoops initiated by this Cbox due to processor core memory requestEVICTION_FILTERFilter on cross-core snoops initiated by this Cbox due to LLC evictionSTATE_MNumber of LLC lookup requests for a line in modified stateSTATE_ENumber of LLC lookup requests for a line in exclusive stateSTATE_SNumber of LLC lookup requests for a line in shared stateSTATE_INumber of LLC lookup requests for a line in invalid stateSTATE_MESINumber of LLC lookup requests for a lineREAD_FILTERFilter on processor core initiated cacheable read requestsWRITE_FILTERFilter on processor core initiated cacheable write requestsEXTSNP_FILTERFilter on external snoop requestsANY_FILTERFilter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requestsUNC_CLOCKTICKSuncore clock ticksUNC_CBO_XSNP_RESPONSESnoop responsesUNC_CBO_CACHE_LOOKUPLLC cache lookupsSnoop responses (must provide a snoop type and filter)*Intel Sandy Bridge C-box0 uncoresnb_unc_cbo0uncore_cbox_0Intel Sandy Bridge C-box1 uncoresnb_unc_cbo1uncore_cbox_1Intel Sandy Bridge C-box2 uncoresnb_unc_cbo2uncore_cbox_2Intel Sandy Bridge C-box3 uncoresnb_unc_cbo3uncore_cbox_3FPU_DIV_ACTIVECycles that the divider is active, includes integer and floating pointFPU_DIVNumber of cycles the divider is activated, includes integer and floating pointNONTAKEN_CONDAll macro conditional non-taken branch instructionsTAKEN_CONDAll macro conditional taken branch instructionsTAKEN_DIRECT_JUMPAll macro unconditional taken branch instructions, excluding calls and indirectsTAKEN_INDIRECT_JUMP_NON_CALL_RETAll taken indirect branches that are not calls nor returnsTAKEN_NEAR_RETURNAll taken indirect branches that have a return mnemonicTAKEN_DIRECT_NEAR_CALLAll taken non-indirect callsTAKEN_INDIRECT_NEAR_CALLAll taken indirect calls, including both register and memory indirectALL_BRANCHESAll near executed branches instructions (not necessarily retired)ALL_CONDAll macro conditional branch instructionsANY_CONDANY_INDIRECT_JUMP_NON_CALL_RETAll indirect branches that are not calls nor returnsANY_DIRECT_NEAR_CALLAll non-indirect callsANY_DIRECT_JUMPAll direct jumpsANY_INDIRECT_NEAR_RETAll indirect near returnsAll taken and not taken macro branches including far branches (Precise Event)CONDAll taken and not taken macro conditional branch instructions (Precise Event)FAR_BRANCHNumber of far branch instructions retired (Precise Event)NEAR_CALLAll macro direct and indirect near calls, does not count far calls (Precise Event)NEAR_RETURNNumber of near ret instructions retired (Precise Event)NEAR_TAKENNumber of near branch taken instructions retired (Precise Event)NOT_TAKENAll not taken macro branch instructions retired (Precise Event)All non-taken mispredicted macro conditional branch instructionsAll taken mispredicted macro conditional branch instructionsAll taken mispredicted indirect branches that are not calls nor returnsAll taken mispredicted indirect branches that have a return mnemonicTAKEN_RETURN_NEARAll taken mispredicted indirect calls, including both register and memory indirectAll mispredicted macro conditional branch instructionsAll mispredicted indirect branches that are not calls nor returnsAll mispredicted branch instructionsAll mispredicted macro branches (Precise Event)All mispredicted macro conditional branch instructions (Precise Event)CONDITIONALNumber of branch instructions retired that were mispredicted and taken (Precise Event)SPLIT_LOCK_UC_LOCK_DURATIONCycles in which the L1D and L2 are locked, due to a UC lock or split lockCACHE_LOCK_DURATIONCycles in which the L1D is lockedRING0Unhalted core cycles the thread was in ring 0RING0_TRANSTransitions from rings 1, 2, or 3 to ring 0RING0:c=1:e=1RING123Unhalted core cycles the thread was in rings 1, 2, or 3REF_PCycles when the core is unhalted (count at 100 Mhz)REF_XCLKCount Xclk pulses (100Mhz) when the core is unhaltedREF_XCLK_ANYCount Xclk pulses (100Mhz) when the at least one thread on the physical core is unhaltedREF_XCLK:tTHREAD_PCycles when thread is not haltedONE_THREAD_ACTIVECounts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is haltedCOUNTNumber of DSB to MITE switchesPENALTY_CYCLESNumber of DSB to MITE switch true penalty cyclesEXCEED_DSB_LINESDSB Fill encountered > 3 DSB linesMISS_CAUSES_A_WALKDemand load miss in all TLB levels which causes a page walk of any page sizeWALK_COMPLETEDDemand load miss in all TLB levels which causes a page walk that completes for any page sizeWALK_DURATIONCycles PMH is busy with a walk due to demand loadsDEMAND_LD_MISS_CAUSES_A_WALKDEMAND_LD_WALK_COMPLETEDDEMAND_LD_WALK_DURATIONSTLB_HITNumber of load operations that missed L1TLB but hit L2TLBLARGE_WALK_COMPLETEDNumber of large page walks completed for demand loadsMiss in all TLB levels that causes a page walk of any page size (4K/2M/4M/1G)CAUSES_A_WALKFirst level miss but second level hit; no page walk. Only relevant if multiple levelsMiss in all TLB levels that causes a page walk that completes of any page size (4K/2M/4M/1G)Cycles PMH is busy with this walkLARGE_PAGE_WALK_COMPLETEDNumber of completed page walks in ITLB due to STLB load misses for large pagesANYCycles with any input/output SSE or FP assistsSIMD_INPUTNumber of SIMD FP assists due to input valuesSIMD_OUTPUTNumber of SIMD FP assists due to output valuesX87_INPUTNumber of X87 assists due to input valueX87_OUTPUTNumber of X87 assists due to output valueMISSESNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accessesIFETCH_STALLNumber of cycles wher a code-fetch stalled due to L1 instruction cache miss or iTLB missHITNumber of Instruction Cache, Streaming Buffer and Victim Cache Reads. Includes cacheable and uncacheable accesses and uncacheable fetchesEMPTYCycles IDQ is emptyMITE_UOPSNumber of uops delivered to IDQ from MITE pathDSB_UOPSNumber of uops delivered to IDQ from DSB pathMS_DSB_UOPSNumber of uops delivered to IDQ when MS busy by DSBMS_MITE_UOPSNumber of uops delivered to IDQ when MS busy by MITEMS_UOPSNumber of uops were delivered to IDQ from MS by either DSB or MITEMITE_UOPS_CYCLESCycles where uops are delivered to IDQ from MITE (MITE active)MITE_UOPS:c=1DSB_UOPS_CYCLESCycles where uops are delivered to IDQ from DSB (DSB active)MS_DSB_UOPS_CYCLESCycles where uops delivered to IDQ when MS busy by DSBMS_DSB_UOPS:c=1MS_MITE_UOPS_CYCLESCycles where uops delivered to IDQ when MS busy by MITEMS_MITE_UOPS:c=1MS_UOPS_CYCLESCycles where uops delivered to IDQ from MS by either BSD or MITEMS_UOPS:c=1MS_SWITCHESNumber of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITEMS_UOPS:c=1:eALL_DSB_UOPSNumber of uops delivered from either DSB pathsALL_DSB_CYCLESCycles MITE/MS delivered anythingALL_DSB_CYCLES_4_UOPSCycles MITE/MS delivered 4 uopsALL_MITE_UOPSNumber of uops delivered from either MITE pathsALL_MITE_CYCLESCycles DSB/MS delivered anythingALL_MITE_CYCLES_4_UOPSCycles MITE is delivering 4 uopsANY_UOPSNumber of uops delivered to IDQ from any pathMS_DSB_UOPS_OCCUROccurrences of DSB MS going activeMS_DSB_UOPS:c=1:e=1CORENumber of non-delivered uops to RAT (use cmask to qualify further)CYCLES_0_UOPS_DELIV_CORECycles per thread when 4 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalledCORE:c=4CYCLES_LE_1_UOP_DELIV_CORECycles per thread when 3 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalledCORE:c=3CYCLES_LE_2_UOP_DELIV_CORECycles with less than 2 uops delivered by the front endCORE:c=2CYCLES_LE_3_UOP_DELIV_CORECycles with less than 3 uops delivered by the front endCORE:c=1CYCLES_FE_WAS_OKCycles Front-End (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling FECORE:c=1:iLCPStall caused by changing prefix length of the instructionIQ_FULLStall cycles due to IQ fullANY_PNumber of instructions retiredALLPrecise instruction retired event to reduce effect of PEBS shadow IP distribution (Precise Event)PREC_DISTITLB_FLUSHNumber of ITLB flushes, includes 4k/2M/4M pagesFLUSHREPLACEMENTNumber of cache lines brought into the L1D cacheINT_NOT_ELIMINATEDNumber of integer Move Elimination candidate uops that were not eliminatedSIMD_NOT_ELIMINATEDNumber of SIMD Move Elimination candidate uops that were not eliminatedINT_ELIMINATEDNumber of integer Move Elimination candidate uops that were eliminatedSIMD_ELIMINATEDNumber of SIMD Move Elimination candidate uops that were eliminatedOCCURRENCESOccurrences of L1D_PEND_MISS going activePENDING:e=1:c=1EDGEPENDINGNumber of L1D load misses outstanding every cyclePENDING_CYCLESCycles with L1D load misses outstandingPENDING:c=1PENDING_CYCLES_ANYCycles with L1D load misses outstanding from any thread on the physical corePENDING:c=1:tFB_FULLNumber of cycles a demand request was blocked due to Fill Buffer (FB) unavailabilityHIT_ENon rejected writebacks from L1D to L2 cache lines in E stateHIT_MNon rejected writebacks from L1D to L2 cache lines in M stateMISSNot rejected writebacks that missed LLCNot rejected writebacks from L1D to L2 cache lines in any stateL2 cache lines filling (counting does not cover rejects)EL2 cache lines in E state (counting does not cover rejects)IL2 cache lines in I state (counting does not cover rejects)SL2 cache lines in S state (counting does not cover rejects)DEMAND_CLEANL2 clean line evicted by a demandDEMAND_DIRTYL2 dirty line evicted by a demandPREFETCH_CLEANL2 clean line evicted by a prefetchPF_CLEANPREFETCH_DIRTYL2 dirty line evicted by an MLC PrefetchPF_DIRTYDIRTY_ANYAny L2 dirty line evicted (does not cover rejects)DIRTY_ALLALL_CODE_RDAny code request to L2 cacheCODE_RD_HITL2 cache hits when fetching instructionsCODE_RD_MISSL2 cache misses when fetching instructionsALL_DEMAND_DATA_RDDemand data read requests to L2 cacheDEMAND_DATA_RD_HITDemand data read requests that hit L2ALL_PFAny L2 HW prefetch request to L2 cachePF_HITRequests from the L2 hardware prefetchers that hit L2 cachePF_MISSRequests from the L2 hardware prefetchers that miss L2 cacheALL_RFOAny RFO requests to L2 cacheRFO_HITStore RFO requests that hit L2 cacheRFO_MISSRFO requests that miss L2 cacheRFOs that miss cache (I state)RFOs that hit cache lines in M stateRFOs that access cache lines in any stateTransactions accessing the L2 pipeCODE_RDL2 cache accesses when fetching instructionsL1D_WBL1D writebacks that access the L2 cacheDMND_DATA_RDDemand Data Read requests that access the L2 cacheL2_FILLL2 fill requests that access the L2 cacheL2_WBL2 writebacks that access the L2 cacheALL_PREFETCHL2 or L3 HW prefetches that access the L2 cache (including rejects)RFORFO requests that access the L2 cacheSTORE_FORWARDLoads blocked by overlapping with store buffer that cannot be forwardedNO_SRNumber of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useADDRESS_ALIASFalse dependencies in MOB due to partial compare on addressHW_PFNon sw-prefetch load dispatches that hit the fill buffer allocated for HW prefetchSW_PFNon sw-prefetch load dispatches that hit the fill buffer allocated for SW prefetchCore-originated cacheable demand requests missed L3REFERENCECore-originated cacheable demand requests that refer to L3MASKMOVThe number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0MEMORY_ORDERINGNumber of Memory Ordering Machine Clears detectedSMCSelf-Modifying Code detectedNumber of machine clears (nukes) of any typeXSNP_HITLoad LLC Hit and a cross-core Snoop hits in on-pkg core cache (Precise Event)XSNP_HITMLoad had HitM Response from a core on same socket (shared LLC) (Precise Event)XSNP_MISSLoad LLC Hit and a cross-core Snoop missed in on-pkg core cache (Precise Event)XSNP_NONELoad hit in last-level (L3) cache with no snoop needed (Precise Event)LOCAL_DRAMNumber of retired load uops that missed L3 but were service by local RAM. Does not count hardware prefetches (Precise Event)REMOTE_DRAMNumber of retired load uops that missed L3 but were service by remote RAM, snoop not needed, snoop miss, snoop hit data not forwarded (Precise Event)REMOTE_HITMNumber of retired load uops whose data sources was remote HITM (Precise Event)REMOTE_FWDLoad uops that miss in the L3 whose data source was forwarded from a remote cache (Precise Event)HIT_LFBA load missed L1D but hit the Fill Buffer (Precise Event)L1_MISSLoad miss in nearest-level (L1D) cache (Precise Event)L1_HITLoad hit in nearest-level (L1D) cache (Precise Event)L2_HITLoad hit in mid-level (L2) cache (Precise Event)L2_MISSLoad misses in mid-level (L2) cache (Precise Event)L3_HITL3_MISSLoad miss in last-level (L3) cache (Precise Event)LATENCY_ABOVE_THRESHOLDMemory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)PRECISE_STORECapture where stores occur, must use with PEBS (Precise Event required)ALL_LOADSAny retired loads (Precise Event)ANY_LOADSALL_STORESAny retired stores (Precise Event)LOCK_LOADSLocked retired loads (Precise Event)ANY_STORESSPLIT_LOADSRetired loads causing cacheline splits (Precise Event)SPLIT_STORESRetired stores causing cacheline splits (Precise Event)STLB_MISS_LOADSSTLB misses dues to retired loads (Precise Event)STLB_MISS_STORESSTLB misses dues to retired stores (Precise Event)LOADSSpeculative cache-line split load uops dispatched to the L1DSTORESSpeculative cache-line split Store-address uops dispatched to L1DALL_DATA_RDDemand and prefetch read requests sent to uncoreALL_DATA_READDEMAND_CODE_RDOffcore code read requests, including cacheable and un-cacheablesDEMAND_DATA_RDDemand Data Read requests sent to uncoreDEMAND_RFOOffcore Demand RFOs, includes regular RFO, Locks, ItoMALL_DATA_RD_CYCLESCycles with cacheable data read transactions in the superQALL_DATA_RD:c=1DEMAND_CODE_RD_CYCLESCycles with demand code reads transactions in the superQDEMAND_CODE_RD:c=1DEMAND_DATA_RD_CYCLESCycles with demand data read transactions in the superQDEMAND_DATA_RD:c=1Cacheable data read transactions in the superQ every cycleCode read transactions in the superQ every cycleDemand data read transactions in the superQ every cycleDEMAND_DATA_RD_GE_6Cycles with at lesat 6 offcore outstanding demand data read requests in the uncore queueDEMAND_DATA_RD:c=6Outstanding RFO (store) transactions in the superQ every cycleDEMAND_RFO_CYCLESCycles with outstanding RFO (store) transactions in the superQDEMAND_RFO:c=1AVX_TO_SSENumber of transitions from AVX-256 to legacy SSE when penalty applicableSSE_TO_AVXNumber of transitions from legacy SSE to AVX-256 when penalty applicableAVX_STORENumber of assists associated with 256-bit AVX storesWBNumber of times the microcode assist is invoked by hardware upon uop writebackCycles stalled due to Resource Related reasonRSCycles stalled due to no eligible RS entry availableSBCycles stalled due to no store buffers available (not including draining from sync)ROBCycles stalled due to re-order buffer fullLBR_INSERTSCount each time an new LBR record is saved by HWEMPTY_CYCLESCycles the RS is empty for this threadEMPTY_ENDCounts number of time the Reservation Station (RS) goes from empty to non-emptyEMPTY_CYCLES:c=1:e:iLOAD_STLB_HITDTLB_THREADNumber of DTLB flushes of thread-specific entriesSTLB_ANYNumber of STLB flushesCounts total number of uops executed from any thread per cycleTHREADCounts total number of uops executed per thread each cycleSTALL_CYCLESNumber of cycles with no uops executedCYCLES_GE_1_UOP_EXECCycles where at least 1 uop was executed per threadCYCLES_GE_2_UOPS_EXECCycles where at least 2 uops were executed per threadCYCLES_GE_3_UOPS_EXECCycles where at least 3 uops were executed per threadCYCLES_GE_4_UOPS_EXECCycles where at least 4 uops were executed per threadCORE_CYCLES_GE_1Cycles where at least 1 uop was executed from any threadCORE_CYCLES_GE_2Cycles where at least 2 uops were executed from any threadCORE_CYCLES_GE_3Cycles where at least 3 uops were executed from any threadCORE_CYCLES_GE_4Cycles where at least 4 uops were executed from any threadCORE_CYCLES_NONECycles where no uop is executed on any threadCORE:iPORT_0Cycles in which a uop is dispatched on port 0PORT_1Cycles in which a uop is dispatched on port 1PORT_2Cycles in which a uop is dispatched on port 2PORT_3Cycles in which a uop is dispatched on port 3PORT_4Cycles in which a uop is dispatched on port 4PORT_5Cycles in which a uop is dispatched on port 5PORT_0_CORECycles in which a uop is dispatched on port 0 for any threadPORT_0:tPORT_1_CORECycles in which a uop is dispatched on port 1 for any threadPORT_1:tPORT_2_CORECycles in which a uop is dispatched on port 2 for any threadPORT_2:tPORT_3_CORECycles in which a uop is dispatched on port 3 for any threadPORT_3:tPORT_4_CORECycles in which a uop is dispatched on port 4 for any threadPORT_4:tPORT_5_CORECycles in which a uop is dispatched on port 5 for any threadPORT_5:tNumber of uops issued by the RAT to the Reservation Station (RS)CORE_STALL_CYCLESCycles no uops issued on this core (by any thread)ANY:c=1:i=1:t=1Cycles no uops issued by this threadANY:c=1:i=1FLAGS_MERGENumber of flags-merge uops allocated. Such uops adds delaySLOW_LEANumber of slow LEA or similar uops allocatedSINGLE_MULNumber of multiply packed/scalar single precision uops allocatedAll uops that actually retired (Precise Event)RETIRE_SLOTSNumber of retirement slots used (Precise Event)Cycles no executable uop retired (Precise Event)ALL:c=1:i=1TOTAL_CYCLESTotal cycles using precise uop retired event (Precise Event)ALL:c=10:iRequest: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetchesDMND_IFETCHRequest: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesRequest: number of writebacks (modified to exclusive) transactionsPF_DATA_RDRequest: number of data cacheline reads generated by L2 prefetchersPF_RFORequest: number of RFO requests generated by L2 prefetchersPF_IFETCHRequest: number of code reads generated by L2 prefetchersPF_LLC_DATA_RDRequest: number of L3 prefetcher requests to L2 for loadsPF_LLC_RFORequest: number of RFO requests generated by L2 prefetcherPF_LLC_IFETCHRequest: number of L2 prefetcher requests to L3 for instruction fetchesBUS_LOCKSRequest: number bus lock and split lock requestsSTRM_STRequest: number of streaming store requestsOTHERRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockANY_IFETCHRequest: combination of PF_IFETCH | DMND_IFETCH | PF_LLC_IFETCHPF_IFETCH:DMND_IFETCH:PF_LLC_IFETCHANY_REQUESTRequest: combination of all request umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHERANY_DATARequest: combination of DMND_DATA | PF_DATA_RD | PF_LLC_DATA_RDDMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RDANY_RFORequest: combination of DMND_RFO | PF_RFO | PF_LLC_RFODMND_RFO:PF_RFO:PF_LLC_RFOANY_RESPONSEResponse: count any response typeNO_SUPPSupplier: counts number of times supplier information is not availableLLC_HITMSupplier: counts L3 hits in M-state (initial lookup)LLC_HITESupplier: counts L3 hits in E-stateLLC_HITSSupplier: counts L3 hits in S-stateLLC_HITFSupplier: counts L3 hits in F-stateLLC_MISS_LOCALSupplier: counts L3 misses to local DRAMLLC_MISS_REMOTESupplier: counts L3 misses to remote DRAMLLC_MISS_REMOTE_DRAMSupplier: counts L3 misses to local or remote DRAMLLC_MISS_LOCAL:LLC_MISS_REMOTELLC_HITMESFSupplier: counts L3 hits in any state (M, E, S, F)LLC_HITM:LLC_HITE:LLC_HITS:LLC_HITFSNP_NONESnoop: counts number of times no snoop-related information is availableSNP_NOT_NEEDEDSnoop: counts the number of times no snoop was needed to satisfy the requestSNP_MISSSnoop: counts number of times a snoop was needed and it missed all snooped cachesSNP_NO_FWDSnoop: counts number of times a snoop was needed and it hit in at leas one snooped cacheSNP_FWDSnoop: counts number of times a snoop was needed and data was forwarded from a remote socketHITMSnoop: counts number of times a snoop was needed and it hitM-ed in local or remote cacheNON_DRAMSnoop: counts number of times target was a non-DRAM system address. This includes MMIO transactionsSNP_ANYSnoop: any snoop reasonSNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:HITM:NON_DRAMCounts the number of times the front end is re-steered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front endCYCLES_L2_PENDINGCycles with pending L2 miss loadsCYCLES_LDM_PENDINGCycles with pending memory loadsCYCLES_L1D_PENDINGCycles with pending L1D load cache missesCYCLES_NO_EXECUTECycles of dispatch stallsSTALLS_L2_PENDINGExecution stalls due to L2 pending loadsSTALLS_L1D_PENDINGExecution stalls due to L1D pending loadsSTALLS_LDM_PENDINGExecution stalls due to memory loadsX87Number of X87 uops executedSSE_FP_PACKED_DOUBLENumber of SSE or AVX-128 double precision FP packed uops executedSSE_FP_SCALAR_SINGLENumber of SSE or AVX-128 single precision FP scalar uops executedSSE_PACKED_SINGLENumber of SSE or AVX-128 single precision FP packed uops executedSSE_SCALAR_DOUBLENumber of SSE or AVX-128 double precision FP scalar uops executedPACKED_SINGLECounts 256-bit packed single-precisionPACKED_DOUBLECounts 256-bit packed double-precisionUOPSNumber of uops delivered by the Loop Stream Detector (LSD)ACTIVECycles with uops delivered by the LSD but which did not come from decoderUOPS:c=1CYCLES_4_UOPSCycles with 4 uops delivered by the LSD but which did not come from decoderUOPS:c=4RECOVERY_CYCLESCycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)RECOVERY_CYCLES_ANYCore cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)RECOVERY_CYCLES:tRECOVERY_STALLS_COUNTNumber of occurrences waiting for Machine ClearsWALK_CYCLESCycles for an extended page table walkLLC_MISSNumber of page walks with a LLC missSQ_FULLNumber of cycles the offcore requests buffer is fullSPLIT_LOCKNumber of split locks in the super queue (SQ)ARITHCounts arithmetic multiply operationsBACLEARSBranch re-steeredBR_INST_EXECBranch instructions executedBR_INST_RETIREDRetired branch instructionsBR_MISP_EXECMispredicted branches executedBR_MISP_RETIREDMispredicted retired branchesBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instructionBR_INST_RETIRED:ALL_BRANCHESMISPREDICTED_BRANCH_RETIREDCount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwareBR_MISP_RETIRED:ALL_BRANCHESLOCK_CYCLESLocked cycles in L1D and L2CPL_CYCLESUnhalted core cycles at a specific ring levelCPU_CLK_UNHALTEDCycles when processor is not in halted stateDSB2MITE_SWITCHESDSB_FILLDSB fillsDTLB_LOAD_MISSESData TLB load missesDTLB_STORE_MISSESData TLB store missesFP_ASSISTX87 Floating point assistsICACHEInstruction Cache accessesIDQIDQ operationsIDQ_UOPS_NOT_DELIVEREDUops not deliveredILD_STALLInstruction Length Decoder stallsINST_RETIREDInstructions retiredINSTRUCTION_RETIREDNumber of instructions at retirementINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDITLBInstruction TLBITLB_MISSESInstruction TLB missesL1DL1D cacheMOVE_ELIMINATIONMove EliminationL1D_PEND_MISSL1D pending missesL2_L1D_WB_RQSTSWriteback requests from L1D to L2L2_LINES_INL2 lines allocatedL2_LINES_OUTL2 lines evictedL2_RQSTSL2 requestsL2_STORE_LOCK_RQSTSL2 store lock requestsL2_TRANSL2 transactionsLAST_LEVEL_CACHE_MISSESThis is an alias for L3_LAT_CACHE:MISSL3_LAT_CACHE:MISSLLC_MISSESAlias for LAST_LEVEL_CACHE_MISSESLAST_LEVEL_CACHE_REFERENCESThis is an alias for L3_LAT_CACHE:REFERENCEL3_LAT_CACHE:REFERENCELLC_REFERENCESAlias for LAST_LEVEL_CACHE_REFERENCESLD_BLOCKSBlocking loadsLD_BLOCKS_PARTIALPartial load blocksLOAD_HIT_PRELoad dispatches that hit fill bufferL3_LAT_CACHECore-originated cacheable demand requests to L3LONGEST_LAT_CACHEMACHINE_CLEARSMachine clear assertedMEM_LOAD_UOPS_LLC_HIT_RETIREDL3 hit loads uops retiredMEM_LOAD_LLC_HIT_RETIREDL3 hit loads uops retired (deprecated use MEM_LOAD_UOPS_LLC_HIT_RETIRED)MEM_LOAD_UOPS_LLC_MISS_RETIREDLoad uops retired that missed the LLCMEM_LOAD_UOPS_RETIREDMemory loads uops retiredMEM_LOAD_RETIREDMemory loads uops retired (deprecated use MEM_LOAD_UOPS_RETIRED)MEM_TRANS_RETIREDMemory transactions retiredMEM_UOPS_RETIREDMemory uops retiredMEM_UOP_RETIREDMemory uops retired (deprecated use MEM_UOPS_RETIRED)MISALIGN_MEM_REFMisaligned memory referencesOFFCORE_REQUESTSOffcore requestsOFFCORE_REQUESTS_OUTSTANDINGOutstanding offcore requestsOTHER_ASSISTSCount hardware assistsRESOURCE_STALLSResource related stall cyclesCYCLE_ACTIVITYStalled cyclesROB_MISC_EVENTSReorder buffer eventsRS_EVENTSReservation station eventsDTLB_LOAD_ACCESSTLB accessTLB_ACCESSTLB_FLUSHTLB flushesUNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted)UNHALTED_REFERENCE_CYCLESUnhalted reference cyclesUOPS_EXECUTEDUops executedUOPS_DISPATCHED_PORTUops dispatch to specific portsUOPS_ISSUEDUops issuedUOPS_RETIREDUops retiredFP_COMP_OPS_EXECounts number of floating point eventsSIMD_FP_256Counts 256-bit packed floating point instructionsLSDLoop stream detectorEPTExtended page tablePAGE_WALKSpage walkerINT_MISCMiscellaneous interruptionsOFFCORE_REQUESTS_BUFFEROffcore reqest bufferSQ_MISCSuperQueue miscellaneousOFFCORE_RESPONSE_0Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)OFFCORE_RESPONSE_1:>Intel Ivy BridgeivbIntel Ivy Bridge EPivb_epMISSNumber of snoop missesINVALNumber of snoop invalidates of a non-modified lineHITNumber of snoop hits of a non-modified lineHITMNumber of snoop hits of a modified lineINVAL_MNumber of snoop invalidates of a modified lineANY_SNPNumber of snoopsEXTERNAL_FILTERFilter on cross-core snoops initiated by this Cbox due to external snoop requestXCORE_FILTERFilter on cross-core snoops initiated by this Cbox due to processor core memory requestEVICTION_FILTERFilter on cross-core snoops initiated by this Cbox due to LLC evictionSTATE_MNumber of LLC lookup requests for a line in modified stateSTATE_ENumber of LLC lookup requests for a line in exclusive stateSTATE_SNumber of LLC lookup requests for a line in shared stateSTATE_INumber of LLC lookup requests for a line in invalid stateSTATE_MESINumber of LLC lookup requests for a lineREAD_FILTERFilter on processor core initiated cacheable read requestsWRITE_FILTERFilter on processor core initiated cacheable write requestsEXTSNP_FILTERFilter on external snoop requestsANY_FILTERFilter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requestsUNC_CLOCKTICKSuncore clock ticksUNC_CBO_XSNP_RESPONSESnoop responsesUNC_CBO_CACHE_LOOKUPLLC cache lookupsSnoop responses (must provide a snoop type and filter)Intel Ivy Bridge C-box0 uncoreivb_unc_cbo0uncore_cbox_0Intel Ivy Bridge C-box1 uncoreivb_unc_cbo1uncore_cbox_1Intel Ivy Bridge C-box2 uncoreivb_unc_cbo2uncore_cbox_2Intel Ivy Bridge C-box3 uncoreivb_unc_cbo3uncore_cbox_3ANYCounts the number of times the front end is re-steered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front endNONTAKEN_CONDITIONALAll macro conditional nontaken branch instructionsNONTAKEN_CONDTAKEN_CONDITIONALTaken speculative and retired macro-conditional branchesTAKEN_CONDTAKEN_DIRECT_JUMPTaken speculative and retired macro-conditional branch instructions excluding calls and indirectsTAKEN_INDIRECT_JUMP_NON_CALL_RETTaken speculative and retired indirect branches excluding calls and returnsTAKEN_INDIRECT_NEAR_RETURNTaken speculative and retired indirect branches with return mnemonicTAKEN_DIRECT_NEAR_CALLTaken speculative and retired direct near callsALL_CONDITIONALSpeculative and retired macro-conditional branchesALL_CONDANY_CONDALL_DIRECT_JMPSpeculative and retired macro-unconditional branches excluding calls and indirectsALL_INDIRECT_JUMP_NON_CALL_RETSpeculative and retired indirect branches excluding calls and returnsALL_INDIRECT_NEAR_RETURNSpeculative and retired indirect return branchesALL_DIRECT_NEAR_CALLSpeculative and retired direct near callsTAKEN_INDIRECT_NEAR_CALLAll indirect calls, including both register and memory indirectALL_BRANCHESAll branch instructions executedCONDITIONALCounts all taken and not taken macro conditional branch instructionsCONDNEAR_CALLCounts all macro direct and indirect near callsCounts all taken and not taken macro branches including far branches (architectural event)NEAR_RETURNCounts the number of near ret instructions retiredNOT_TAKENCounts all not taken macro branch instructions retiredNEAR_TAKENCounts the number of near branch taken instructions retiredFAR_BRANCHCounts the number of far branch instructions retiredNot taken speculative and retired mispredicted macro conditional branchesTaken speculative and retired mispredicted macro conditional branchesTaken speculative and retired mispredicted indirect branches excluding calls and returnsTAKEN_RETURN_NEARTaken speculative and retired mispredicted indirect branches with return mnemonicSpeculative and retired mispredicted macro conditional branchesAll mispredicted indirect branches that are not calls nor returnsTaken speculative and retired mispredicted indirect callsAll mispredicted macro conditional branch instructionsAll mispredicted macro branches (architectural event)number of near branch instructions retired that were mispredicted and takenRING0Unhalted core cycles when the thread is in ring 0RING123Unhalted core cycles when thread is in rings 1, 2, or 3RING0_TRANSNumber of intervals between processor halts while thread is in ring 0REF_XCLKCount Xclk pulses (100Mhz) when the core is unhaltedREF_XCLK_ANYCount Xclk pulses 100Mhz) when the at least one thread on the physical core is unhaltedREF_XCLK:tREF_PCycles when the core is unhalted (count at 100 Mhz)THREAD_PCycles when thread is not haltedONE_THREAD_ACTIVECounts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is haltedCYCLES_L2_PENDINGCycles with pending L2 miss loads (must use with HT off only)CYCLES_LDM_PENDINGCycles with pending memory loadsCYCLES_L1D_PENDINGCycles with pending L1D load cache missesSTALLS_L1D_PENDINGExecutions stalls due to pending L1D load cache missesSTALLS_L2_PENDINGExecution stalls due to L2 pending loads (must use with HT off only)STALLS_LDM_PENDINGExecution stalls due to memory subsystemCYCLES_NO_EXECUTECycles during which no instructions were executed in the execution stage of the pipelineMISS_CAUSES_A_WALKMisses in all DTLB levels that cause page walksWALK_COMPLETED_4KMisses in all TLB levels causes a page walk that completes (4K)WALK_COMPLETED_2M_4MMisses in all TLB levels causes a page walk that completes (2M/4M)WALK_COMPLETEDMisses in all TLB levels causes a page walk of any page size that completesWALK_DURATIONCycles when PMH is busy with page walksSTLB_HIT_4KMisses that miss the DTLB and hit the STLB (4K)STLB_HIT_2MMisses that miss the DTLB and hit the STLB (2M)STLB_HITNumber of cache load STLB hits. No page walkPDE_CACHE_MISSDTLB misses with low part of linear-to-physical address translation missedX87_OUTPUTNumber of X87 FP assists due to output valuesX87_INPUTNumber of X87 FP assists due to input valuesSIMD_OUTPUTNumber of SIMD FP assists due to output valuesSIMD_INPUTNumber of SIMD FP assists due to input valuesCycles with any input/output SEE or FP assistsALLCycles with any input and output SSE or FP assistMISSESNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accessesHITNumber of Instruction Cache, Streaming Buffer and Victim Cache Reads. Includes cacheable and uncacheable accesses and uncacheable fetchesIFETCH_STALLNumber of cycles where a code-fetch stalled due to L1 instruction cache miss or an iTLB missEMPTYCycles the Instruction Decode Queue (IDQ) is emptyMITE_UOPSNumber of uops delivered to Instruction Decode Queue (IDQ) from MITE pathDSB_UOPSNumber of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) pathMS_DSB_UOPSUops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyMS_MITE_UOPSUops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyMS_UOPSNumber of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITEMS_UOPS_CYCLESNumber of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITEMS_UOPS:c=1MS_SWITCHESMS_UOPS:c=1:eMITE_UOPS_CYCLESCycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE pathMITE_UOPS:c=1DSB_UOPS_CYCLESCycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) pathDSB_UOPS:c=1MS_DSB_UOPS_CYCLESCycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyMS_DSB_UOPS:c=1MS_DSB_OCCURDeliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busyMS_DSB_UOPS:c=1:e=1ALL_DSB_CYCLES_4_UOPSCycles Decode Stream Buffer (DSB) is delivering 4 UopsALL_DSB_CYCLES_ANY_UOPSCycles Decode Stream Buffer (DSB) is delivering any UopALL_MITE_CYCLES_4_UOPSCycles MITE is delivering 4 UopsALL_MITE_CYCLES_ANY_UOPSCycles MITE is delivering any UopALL_MITE_UOPSNumber of uops delivered to Instruction Decode Queue (IDQ) from any pathCORECount number of non-delivered uops to Resource Allocation Table (RAT)CYCLES_0_UOPS_DELIV_CORECycles per thread when 4 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalledCORE:c=4CYCLES_LE_1_UOP_DELIV_CORECycles per thread when 3 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalledCORE:c=3CYCLES_LE_2_UOP_DELIV_CORECycles with less than 2 uops delivered by the front endCORE:c=2CYCLES_LE_3_UOP_DELIV_CORECycles with less than 3 uops delivered by the front endCORE:c=1CYCLES_FE_WAS_OKCycles Front-End (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling FECORE:c=1:iANY_PNumber of instructions retired. General Counter - architectural eventPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise Event)TOTAL_CYCLESNumber of cycles using always true conditionALL:i=1:c=10PREC_DISTPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distributionX87X87 FP operations retired with no exceptions. Also counts flows that have several X87 or flows that use X87 uops in the exception handlingRECOVERY_CYCLESCycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)RECOVERY_CYCLES_ANYCore cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)RECOVERY_CYCLES:tRECOVERY_STALLS_COUNTNumber of occurrences waiting for Machine ClearsITLB_FLUSHFlushing of the Instruction TLB (ITLB) pages independent of page sizeREPLACEMENTL1D Data line replacementsPENDINGCycles with L1D load misses outstandingPENDING_CYCLESPENDING:c=1OCCURRENCESNumber L1D miss outstandingPENDING:c=1:e=1EDGEREQUEST_FB_FULLNumber of times a demand request was blocked due to Fill Buffer (FB) unavailabilityFB_FULLNumber of cycles a demand request was blocked due to Fill Buffer (FB) unavailabilityREQUEST_FB_FULL:c=1WB_HITWB requests that hit L2 cacheIL2 cache lines in I state filling L2SL2 cache lines in S state filling L2EL2 cache lines in E state filling L2L2 cache lines filling L2DEMAND_CLEANNumber of clean L2 cachelines evicted by demandDEMAND_DIRTYNumber of dirty L2 cachelines evicted by demandDEMAND_DATA_RD_MISSDemand Data Read requests that miss L2 cacheDEMAND_DATA_RD_HITDemand Data Read requests that hit L2 cacheDEMAND_RFO_MISSRFO requests that miss L2 cacheRFO_MISSDEMAND_RFO_HITRFO requests that hit L2 cacheRFO_HITCODE_RD_MISSL2 cache misses when fetching instructionsALL_DEMAND_MISSAll demand requests that miss the L2 cacheCODE_RD_HITL2 cache hits when fetching instructions, code readsL2_PF_MISSRequests from the L2 hardware prefetchers that miss L2 cachePF_MISSRequests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cacheMISSAll requests that miss the L2 cacheL2_PF_HITRequests from the L2 hardware prefetchers that hit L2 cachePF_HITALL_DEMAND_DATA_RDAny data read request to L2 cacheALL_RFOAny data RFO request to L2 cacheALL_CODE_RDAny code read request to L2 cacheALL_DEMAND_REFERENCESAll demand requests to L2 cache ALL_PFAny L2 HW prefetch request to L2 cacheREFERENCESAll requests to L2 cacheDEMAND_DATA_RDDemand Data Read requests that access L2 cacheRFORFO requests that access L2 cacheCODE_RDL2 cache accesses when fetching instructionsL2 or L3 HW prefetches that access L2 cache, including rejectsL1D_WBL1D writebacks that access L2 cacheL2_FILLL2 fill requests that access L2 cacheL2_WBL2 writebacks that access L2 cacheALL_REQUESTSTransactions accessing L2 pipeSTORE_FORWARDCounts the number of loads blocked by overlapping with store buffer entries that cannot be forwardedNO_SRnumber of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useADDRESS_ALIASFalse dependencies in MOB due to partial compare on addressSW_PFNon software-prefetch load dispatches that hit FB allocated for software prefetchHW_PFNon software-prefetch load dispatches that hit FB allocated for hardware prefetchSPLIT_LOCK_UC_LOCK_DURATIONCycles in which the L1D and L2 are locked, due to a UC lock or split lockCACHE_LOCK_DURATIONcycles that the L1D is lockedCore-originated cacheable demand requests missed LLC - architectural eventREFERENCECore-originated cacheable demand requests that refer to LLC - architectural eventCYCLESCycles there was a Nuke. Account for both thread-specific and All Thread NukesMEMORY_ORDERINGNumber of Memory Ordering Machine Clears detectedSMCNumber of Self-modifying code (SMC) Machine Clears detectedMASKMOVThis event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0COUNTNumber of machine clears (nukes) of any typeCYCLES:c=1:eXSNP_MISSRetired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cacheXSNP_HITRetired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cacheXSNP_HITMLoad had HitM Response from a core on same socket (shared L3). (Non PEBSXSNP_NONERetired load uops which data sources were hits in L3 without snoops requiredLOCAL_DRAMRetired load uops missing L3 cache but hitting local memoryREMOTE_DRAMNumber of retired load uops that missed L3 but were service by remote RAM, snoop not needed, snoop miss, snoop hit data not forwarded (Precise Event)REMOTE_HITMNumber of retired load uops whose data sources was remote HITM (Precise Event)REMOTE_FWDLoad uops that miss in the L3 whose data source was forwarded from a remote cache (Precise Event)L1_HITRetired load uops with L1 cache hits as data sourceL2_HITRetired load uops with L2 cache hits as data sourceL3_HITRetired load uops with L3 cache hits as data sourceL1_MISSRetired load uops which missed the L1DL2_MISSRetired load uops which missed the L2. Unknown data source excludedL3_MISSRetired load uops which missed the L3HIT_LFBRetired load uops which missed L1 but hit line fill buffer (LFB)LOAD_LATENCYMemory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)LATENCY_ABOVE_THRESHOLDSTLB_MISS_LOADSLoad uops with true STLB miss retired to architected pathSTLB_MISS_STORESStore uops with true STLB miss retired to architected pathLOCK_LOADSLoad uops with locked access retiredSPLIT_LOADSLine-splitted load uops retiredSPLIT_STORESLine-splitted store uops retiredALL_LOADSAll load uops retiredALL_STORESAll store uops retiredLOADSSpeculative cache-line split load uops dispatched to the L1DSTORESSpeculative cache-line split store-address uops dispatched to L1DINT_ELIMINATEDNumber of integer Move Elimination candidate uops that were eliminatedSIMD_ELIMINATEDNumber of SIMD Move Elimination candidate uops that were eliminatedINT_NOT_ELIMINATEDNumber of integer Move Elimination candidate uops that were not eliminatedSIMD_NOT_ELIMINATEDNumber of SIMD Move Elimination candidate uops that were not eliminatedDemand data read requests sent to uncore (use with HT off only)DEMAND_CODE_RDDemand code read requests sent to uncore (use with HT off only)DEMAND_RFODemand RFOs requests sent to uncore (use with HT off only)ALL_DATA_RDData read requests sent to uncore (use with HT off only)AVX_TO_SSENumber of transitions from AVX-256 to legacy SSE when penalty applicableSSE_TO_AVXNumber of transitions from legacy SSE to AVX-256 when penalty applicableANY_WB_ASSISTNumber of times any microcode assist is invoked by HW upon uop writebackCycles Allocation is stalled due to Resource Related reasonRSStall cycles caused by absence of eligible entries in Reservation Station (RS)SBCycles Allocator is stalled due to Store Buffer full (not including draining from synch)ROBROB full stall cyclesLBR_INSERTSCount each time an new Last Branch Record (LBR) is insertedEMPTY_CYCLESCycles the Reservation Station (RS) is empty for this threadEMPTY_ENDCounts number of time the Reservation Station (RS) goes from empty to non-emptyEMPTY_CYCLES:c=1:e:iDTLB_THREADCount number of DTLB flushes of thread-specific entriesSTLB_ANYCount number of any STLB flushesNumber of uops executed from any threadSTALL_CYCLESNumber of cycles with no uops executedCYCLES_GE_1_UOP_EXECCycles where at least 1 uop was executed per threadCYCLES_GE_2_UOPS_EXECCycles where at least 2 uops were executed per threadCYCLES_GE_3_UOPS_EXECCycles where at least 3 uops were executed per threadCYCLES_GE_4_UOPS_EXECCycles where at least 4 uops were executed per threadCORE_CYCLES_GE_1Cycles where at least 1 uop was executed from any threadCORE_CYCLES_GE_2Cycles where at least 2 uops were executed from any threadCORE_CYCLES_GE_3Cycles where at least 3 uops were executed from any threadCORE_CYCLES_GE_4Cycles where at least 4 uops were executed from any threadCORE_CYCLES_NONECycles where no uop is executed on any threadCORE:iPORT_0Cycles which a Uop is executed on port 0PORT_1Cycles which a Uop is executed on port 1PORT_2Cycles which a Uop is executed on port 2PORT_3Cycles which a Uop is executed on port 3PORT_4Cycles which a Uop is executed on port 4PORT_5Cycles which a Uop is executed on port 5PORT_6Cycles which a Uop is executed on port 6PORT_7Cycles which a Uop is executed on port 7PORT_0_COREtbdPORT_0:t=1PORT_1_COREPORT_1:t=1PORT_2_COREPORT_2:t=1PORT_3_COREPORT_3:t=1PORT_4_COREPORT_4:t=1PORT_5_COREPORT_5:t=1PORT_6_COREPORT_6:t=1PORT_7_COREPORT_7:t=1Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)FLAGS_MERGENumber of flags-merge uops being allocated. Such uops adds delaySLOW_LEANumber of slow LEA or similar uops allocated. Such uop has 3 sources regardless if result of LEA instruction or notSINGLE_MULNumber of Multiply packed/scalar single precision uops allocatedCounts the number of cycles no uops issued by this threadANY:c=1:i=1CORE_STALL_CYCLESCounts the number of cycles no uops issued on this coreANY:c=1:i=1:t=1All uops that actually retiredRETIRE_SLOTSnumber of retirement slots used non PEBSCycles no executable uops retired (Precise Event)ALL:i=1:c=1Number of cycles using always true condition applied to PEBS uops retired eventCycles no executable uops retired on core (Precise Event)ALL:i=1:c=1:t=1STALL_OCCURRENCESNumber of transitions from stalled to unstalled execution (Precise Event)ALL:c=1:i=1:e=1DMND_DATA_RDRequest: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetchesDMND_CODE_RDRequest: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesDMND_IFETCHWBRequest: number of writebacks (modified to exclusive) transactionsPF_DATA_RDRequest: number of data cacheline reads generated by L2 prefetchersPF_RFORequest: number of RFO requests generated by L2 prefetchersPF_CODE_RDRequest: number of code reads generated by L2 prefetchersPF_IFETCHPF_L3_DATA_RDRequest: number of L2 prefetcher requests to L3 for loadsPF_L3_RFORequest: number of RFO requests generated by L2 prefetcherPF_L3_CODE_RDRequest: number of L2 prefetcher requests to L3 for instruction fetchesPF_L3_IFETCHSPLIT_LOCK_UC_LOCKRequest: number of bus lock and split lock requestsBUS_LOCKSSTRM_STRequest: number of streaming store requestsOTHERRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockANY_CODE_RDRequest: combination of PF_CODE_RD | DMND_CODE_RD | PF_L3_CODE_RDPF_CODE_RD:DMND_CODE_RD:PF_L3_CODE_RDANY_IFETCHRequest: combination of PF_CODE_RD | PF_L3_CODE_RDANY_REQUESTRequest: combination of all request umasksDMND_DATA_RD:DMND_RFO:DMND_CODE_RD:WB:PF_DATA_RD:PF_RFO:PF_CODE_RD:PF_L3_DATA_RD:PF_L3_RFO:PF_L3_CODE_RD:SPLIT_LOCK_UC_LOCK:STRM_ST:OTHERANY_DATARequest: combination of DMND_DATA | PF_DATA_RD | PF_L3_DATA_RDDMND_DATA_RD:PF_DATA_RD:PF_L3_DATA_RDANY_RFORequest: combination of DMND_RFO | PF_RFO | PF_L3_RFODMND_RFO:PF_RFO:PF_L3_RFOANY_RESPONSEResponse: count any response typeNO_SUPPSupplier: counts number of times supplier information is not availableL3_HITMSupplier: counts L3 hits in M-state (initial lookup)L3_HITESupplier: counts L3 hits in E-stateL3_HITSSupplier: counts L3 hits in S-stateL3_HITFSupplier: counts L3 hits in F-stateSupplier: counts L3 hits in any state (M, E, S)L3_HITM:L3_HITE:L3_HITSSupplier: counts L3 hits in any state (M, E, S, F)L3_HITM:L3_HITE:L3_HITS:L3_HITFL3_MISS_LOCALSupplier: counts L3 misses to local DRAML3_MISS_REMOTE_HOP0Supplier: counts L3 misses to remote DRAM with 0 hopL3_MISS_REMOTE_HOP1Supplier: counts L3 misses to remote DRAM with 1 hopL3_MISS_REMOTE_HOP2PSupplier: counts L3 misses to remote DRAM with 2P hopsSupplier: counts L3 misses to local or remote DRAML3_MISS_LOCAL:L3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2PL3_MISS_REMOTESupplier: counts L3 misses to remote nodeL3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2PL3_MISS_REMOTE_DRAMSPL_HITSupplier: counts L3 supplier hitSNP_NONESnoop: counts number of times no snoop-related information is availableSNP_NOT_NEEDEDSnoop: counts the number of times no snoop was needed to satisfy the requestSNP_MISSSnoop: counts number of times a snoop was needed and it missed all snooped cachesSNP_NO_FWDSnoop: counts number of times a snoop was needed and it hit in at leas one snooped cacheSNP_FWDSnoop: counts number of times a snoop was needed and data was forwarded from a remote socketSNP_HITMSnoop: counts number of times a snoop was needed and it hitM-ed in local or remote cacheSNP_NON_DRAMSnoop: counts number of times target was a non-DRAM system address. This includes MMIO transactionsSNP_ANYSnoop: any snoop reasonSNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:SNP_HITM:SNP_NON_DRAMSTARTNumber of times an HLE execution startedCOMMITNumber of times an HLE execution successfully committedABORTEDNumber of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise Event)ABORTED_MISC1Number of times an HLE execution aborted due to various memory eventsABORTED_MISC2Number of times an HLE execution aborted due to uncommon conditionsABORTED_MISC3Number of times an HLE execution aborted due to HLE-unfriendly instructionsABORTED_MISC4Number of times an HLE execution aborted due to incompatible memory typeABORTED_MISC5Number of times an HLE execution aborted due to none of the other 4 reasons (e.g., interrupt)Number of times an RTM execution startedNumber of times an RTM execution successfully committedNumber of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise Event)Number of times an RTM execution aborted due to various memory eventsNumber of times an RTM execution aborted due to uncommon conditionsNumber of times an RTM execution aborted due to RTM-unfriendly instructionsNumber of times an RTM execution aborted due to incompatible memory typeNumber of times an RTM execution aborted due to none of the other 4 reasons (e.g., interrupt)ABORT_CONFLICTNumber of times a transactional abort was signaled due to data conflict on a transactionally accessed addressABORT_CAPACITY_WRITENumber of times a transactional abort was signaled due to data capacity limitation for transactional writesABORT_HLE_STORE_TO_ELIDED_LOCKNumber of times a HLE transactional execution aborted due to a non xrelease prefixed instruction writing to an elided lock in the elision bufferABORT_HLE_ELISION_BUFFER_NOT_EMPTYNumber of times a HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zeroABORT_HLE_ELISION_BUFFER_MISMATCHNumber of times a HLE transaction execution aborted due to xrelease lock not satisfying the address and value requirements in the elision bufferABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENTNumber of times a HLE transaction execution aborted due to an unsupported read alignment from the elision bufferABORT_HLE_ELISION_BUFFER_FULLNumber of times a HLE clock could not be elided due to ElisionBufferAvailable being zeroMISC1Number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abortMISC2Number of times a class of instructions that may cause a transactional abort was executed inside a transactional regionMISC3Number of times an instruction execution caused the supported nest count to be exceededMISC4Number of times an instruction with HLE xbegin prefix was executed inside a RTM transactional regionMISC5Number of times an instruction with HLE xacquire prefix was executed inside a RTM transactional regionALL_DATA_RD_CYCLESCycles with cacheable data read transactions in the superQ (use with HT off only)ALL_DATA_RD:c=1DEMAND_CODE_RD_CYCLESCycles with demand code reads transactions in the superQ (use with HT off only)DEMAND_CODE_RD:c=1DEMAND_DATA_RD_CYCLESCycles with demand data read transactions in the superQ (use with HT off only)DEMAND_DATA_RD:c=1Cacheable data read transactions in the superQ every cycle (use with HT off only)Code read transactions in the superQ every cycle (use with HT off only)Demand data read transactions in the superQ every cycle (use with HT off only)DEMAND_DATA_RD_GE_6Cycles with at lesat 6 offcore outstanding demand data read requests in the uncore queueDEMAND_DATA_RD:c=6Outstanding RFO (store) transactions in the superQ every cycle (use with HT off only)DEMAND_RFO_CYCLESCycles with outstanding RFO (store) transactions in the superQ (use with HT off only)DEMAND_RFO:c=1LCPStall caused by changing prefix length of the instructionIQ_FULLStall cycles due to IQ fullDTLB_L1Number of DTLB page walker loads that hit in the L1D and line fill bufferITLB_L1Number of ITLB page walker loads that hit in the L1I and line fill bufferDTLB_L2Number of DTLB page walker loads that hit in the L2ITLB_L2Number of ITLB page walker loads that hit in the L2DTLB_L3Number of DTLB page walker loads that hit in the L3ITLB_L3Number of ITLB page walker loads that hit in the L3EPT_DTLB_L1Number of extended page table walks from the DTLB that hit in the L1D and line fill bufferEPT_ITLB_L1Number of extended page table walks from the ITLB that hit in the L1D and line fill bufferEPT_DTLB_L2Number of extended page table walks from the DTLB that hit in the L2EPT_ITLB_L2Number of extended page table walks from the ITLB that hit in the L2EPT_DTLB_L3Number of extended page table walks from the DTLB that hit in the L3EPT_ITLB_L3Number of extended page table walks from the ITLB that hit in the L3DTLB_MEMORYNumber of DTLB page walker loads that hit memoryITLB_MEMORYNumber of ITLB page walker loads that hit memoryEPT_DTLB_MEMORYNumber of extended page table walks from the DTLB that hit memoryEPT_ITLB_MEMORYNumber of extended page table walks from the ITLB that hit memoryUOPSNumber of uops delivered by the Loop Stream Detector (LSD)ACTIVECycles with uops delivered by the LSD but which did not come from decoderUOPS:c=1CYCLES_4_UOPSCycles with 4 uops delivered by the LSD but which did not come from decoderUOPS:c=4PENALTY_CYCLESNumber of DSB to MITE switch true penalty cyclesWALK_CYCLESCycles for an extended page table walkDIVIDER_UOPSNumber of uops executed by dividerSQ_FULLNumber of cycles the offcore requests buffer is fullApproximate counts of AVX and AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions using 256-bit operationsSPLIT_LOCKNumber of split locks in the super queue (SQ)UNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted)UNHALTED_REFERENCE_CYCLESUnhalted reference cyclesINSTRUCTION_RETIREDNumber of instructions at retirementINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instructionBR_INST_RETIRED:ALL_BRANCHESMISPREDICTED_BRANCH_RETIREDCount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwareBR_MISP_RETIRED:ALL_BRANCHESBACLEARSBranch re-steeredBR_INST_EXECBranch instructions executedBR_INST_RETIREDBranch instructions retired (Precise Event)BR_MISP_EXECMispredicted branches executedBR_MISP_RETIREDMispredicted retired branches (Precise Event)CPL_CYCLESUnhalted core cycles at a specific ring levelCPU_CLK_THREAD_UNHALTEDCPU_CLK_UNHALTEDCYCLE_ACTIVITYStalled cyclesDTLB_LOAD_MISSESData TLB load missesDTLB_STORE_MISSESData TLB store missesFP_ASSISTX87 floating-point assistsHLE_RETIREDHLE execution (Precise Event)ICACHEInstruction CacheIDQIDQ operationsIDQ_UOPS_NOT_DELIVEREDUops not deliveredINST_RETIREDNumber of instructions retired (Precise Event)INT_MISCMiscellaneous interruptionsITLBInstruction TLBITLB_MISSESInstruction TLB missesL1DL1D cacheL1D_PEND_MISSL1D pending missesL2_DEMAND_RQSTSDemand Data Read requests to L2L2_LINES_INL2 lines allocatedL2_LINES_OUTL2 lines evictedL2_RQSTSL2 requestsL2_TRANSL2 transactionsLD_BLOCKSBlocking loadsLD_BLOCKS_PARTIALPartial load blocksLOAD_HIT_PRELoad dispatchesLOCK_CYCLESLocked cycles in L1D and L2LONGEST_LAT_CACHEL3 cacheMACHINE_CLEARSMachine clear assertedMEM_LOAD_UOPS_L3_HIT_RETIREDL3 hit load uops retired (Precise Event)MEM_LOAD_UOPS_LLC_HIT_RETIREDMEM_LOAD_UOPS_L3_MISS_RETIREDLoad uops retired that missed the L3 (Precise Event)MEM_LOAD_UOPS_LLC_MISS_RETIREDMEM_LOAD_UOPS_RETIREDRetired load uops (Precise Event)MEM_TRANS_RETIREDMemory transactions retired (Precise Event)MEM_UOPS_RETIREDMemory uops retired (Precise Event)MISALIGN_MEM_REFMisaligned memory referencesMOVE_ELIMINATIONMove EliminationOFFCORE_REQUESTSDemand Data Read requests sent to uncoreOTHER_ASSISTSSoftware assistRESOURCE_STALLSROB_MISC_EVENTSROB miscellaneous eventsRS_EVENTSReservation StationRTM_RETIREDRestricted Transaction Memory execution (Precise Event)TLB_FLUSHTLB flushesUOPS_EXECUTEDUops executedLSDLoop stream detectorUOPS_EXECUTED_PORTUops dispatched to specific portsUOPS_DISPATCHED_PORTUOPS_ISSUEDUops issuedUOPS_RETIREDUops retired (Precise Event)TX_MEMTransactional memory abortsTX_EXECTransactional executionOFFCORE_REQUESTS_OUTSTANDINGOutstanding offcore requestsILD_STALLInstruction Length Decoder stallsPAGE_WALKER_LOADSPage walker loadsDSB2MITE_SWITCHESNumber of DSB to MITE switchesEPTExtended page tableARITHCounts arithmetic multiply operationsAVXCounts AVX instructionsSQ_MISCSuperQueue miscellaneousOFFCORE_REQUESTS_BUFFEROffcore reqest bufferOFFCORE_RESPONSE_0Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)OFFCORE_RESPONSE_1<EF?Intel HaswellhswIntel Haswell EPhsw_epANYNumber of front-end re-steers due to BPU mispredictionNONTAKEN_CONDITIONALAll macro conditional nontaken branch instructionsNONTAKEN_CONDTAKEN_CONDITIONALTaken speculative and retired macro-conditional branchesTAKEN_CONDTAKEN_DIRECT_JUMPTaken speculative and retired macro-conditional branch instructions excluding calls and indirectsTAKEN_INDIRECT_JUMP_NON_CALL_RETTaken speculative and retired indirect branches excluding calls and returnsTAKEN_INDIRECT_NEAR_RETURNTaken speculative and retired indirect branches with return mnemonicTAKEN_DIRECT_NEAR_CALLTaken speculative and retired direct near callsALL_CONDITIONALSpeculative and retired macro-conditional branchesALL_CONDANY_CONDALL_DIRECT_JMPSpeculative and retired macro-unconditional branches excluding calls and indirectsALL_INDIRECT_JUMP_NON_CALL_RETSpeculative and retired indirect branches excluding calls and returnsALL_INDIRECT_NEAR_RETURNSpeculative and retired indirect return branchesALL_DIRECT_NEAR_CALLSpeculative and retired direct near callsTAKEN_INDIRECT_NEAR_CALLAll indirect calls, including both register and memory indirectALL_BRANCHESAll branch instructions executedCONDITIONALCounts all taken and not taken macro conditional branch instructionsCONDNEAR_CALLCounts all macro direct and indirect near callsCounts all taken and not taken macro branches including far branches (architectural event)NEAR_RETURNCounts the number of near ret instructions retiredNOT_TAKENCounts all not taken macro branch instructions retiredNEAR_TAKENCounts the number of near branch taken instructions retiredFAR_BRANCHCounts the number of far branch instructions retiredNot taken speculative and retired mispredicted macro conditional branchesTaken speculative and retired mispredicted macro conditional branchesTaken speculative and retired mispredicted indirect branches excluding calls and returnsSpeculative and retired mispredicted macro conditional branchesAll mispredicted indirect branches that are not calls nor returnsTaken speculative and retired mispredicted indirect callsTAKEN_RETURN_NEARTaken speculative and retired mispredicted direct returnsAll mispredicted macro conditional branch instructionsAll mispredicted macro branches (architectural event)Number of near branch instructions retired that were mispredicted and takenRETNumber of mispredicted ret instructions retiredRING0Unhalted core cycles when the thread is in ring 0RING123Unhalted core cycles when thread is in rings 1, 2, or 3RING0_TRANSNumber of intervals between processor halts while thread is in ring 0REF_XCLKCount Xclk pulses (100Mhz) when the core is unhaltedREF_XCLK_ANYCount Xclk pulses (100Mhz) when the at least one thread on the physical core is unhaltedREF_XCLK:tREF_PCycles when the core is unhalted (count at 100 Mhz)THREAD_PCycles when thread is not haltedONE_THREAD_ACTIVECounts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is haltedCYCLES_L2_PENDINGCycles with pending L2 miss loads (must use with HT off only)CYCLES_LDM_PENDINGCycles with pending memory loadsCYCLES_MEM_ANYCYCLES_L1D_PENDINGCycles with pending L1D load cache missesSTALLS_LDM_PENDINGExecutions stalls when there is at least one pending demand load requestSTALLS_L1D_PENDINGExecutions stalls while there is at least one L1D demand load outstandingSTALLS_L2_PENDINGExecution stalls while there is at least one L2 demand load pending outstandingSTALLS_TOTALCycles during which no instructions were executed in the execution stage of the pipelineCYCLES_NO_EXECUTEMISS_CAUSES_A_WALKMisses in all DTLB levels that cause page walksWALK_COMPLETED_4KMisses in all TLB levels causes a page walk that completes (4K)WALK_COMPLETED_2M_4MMisses in all TLB levels causes a page walk of 2MB/4MB page sizes that completesWALK_COMPLETED_1GMisses in all TLB levels causes a page walk of 1GB page sizes that completesWALK_COMPLETEDMisses in all TLB levels causes a page walk of any page size that completesWALK_DURATIONCycles when PMH is busy with page walksSTLB_HIT_4KMisses that miss the DTLB and hit the STLB (4KB)STLB_HIT_2MMisses that miss the DTLB and hit the STLB (2MB)STLB_HITNumber of cache load STLB hits. No page walkMisses in all TLB levels causes a page walk that completes (4KB)Misses in all TLB levels causes a page walk that completes (2MB/4MB)Misses in all TLB levels causes a page walk that completes (1GB)X87_OUTPUTNumber of X87 FP assists due to output valuesX87_INPUTNumber of X87 FP assists due to input valuesSIMD_OUTPUTNumber of SIMD FP assists due to output valuesSIMD_INPUTNumber of SIMD FP assists due to input valuesCycles with any input/output SEE or FP assistsALLCycles with any input and output SSE or FP assistMISSESNumber of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accessesIFDATA_STALLNumber of cycles where a code fetch is stalled due to L1 missHITNumber of Instruction Cache, Streaming Buffer and Victim Cache Reads. Includes cacheable and uncacheable accesses and uncacheable fetchesEMPTYCycles the Instruction Decode Queue (IDQ) is emptyMITE_UOPSNumber of uops delivered to Instruction Decode Queue (IDQ) from MITE pathDSB_UOPSNumber of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) pathMS_DSB_UOPSUops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyMS_MITE_UOPSUops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyMS_UOPSNumber of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITEMS_UOPS_CYCLESNumber of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITEMS_UOPS:c=1MS_SWITCHESMS_UOPS:c=1:eMITE_UOPS_CYCLESCycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE pathMITE_UOPS:c=1DSB_UOPS_CYCLESCycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) pathDSB_UOPS:c=1MS_DSB_UOPS_CYCLESCycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyMS_DSB_UOPS:c=1MS_DSB_OCCURDeliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busyMS_DSB_UOPS:c=1:e=1ALL_DSB_CYCLES_4_UOPSCycles Decode Stream Buffer (DSB) is delivering 4 UopsALL_DSB_CYCLES_ANY_UOPSCycles Decode Stream Buffer (DSB) is delivering any UopALL_MITE_CYCLES_4_UOPSCycles MITE is delivering 4 UopsALL_MITE_CYCLES_ANY_UOPSCycles MITE is delivering any UopALL_MITE_UOPSNumber of uops delivered to Instruction Decode Queue (IDQ) from any pathCORECount number of non-delivered uops to Resource Allocation Table (RAT)CYCLES_0_UOPS_DELIV_CORECycles per thread when 4 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalledCORE:c=4CYCLES_LE_1_UOP_DELIV_CORECycles per thread when 3 or more uops are not delivered to the Resource Allocation Table (RAT) when backend is not stalledCORE:c=3CYCLES_LE_2_UOP_DELIV_CORECycles with less than 2 uops delivered by the front endCORE:c=2CYCLES_LE_3_UOP_DELIV_CORECycles with less than 3 uops delivered by the front endCORE:c=1CYCLES_FE_WAS_OKCycles Front-End (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling FECORE:c=1:iANY_PNumber of instructions retired. General Counter - architectural eventPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise Event)PREC_DISTTOTAL_CYCLESNumber of cycles using always true conditionPREC_DIST:i=1:c=10Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise event)X87Number of FPU operations retired (instructions with no exceptions)RECOVERY_CYCLESCycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)RECOVERY_CYCLES_ANYCore cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)RECOVERY_CYCLES:tRECOVERY_STALLS_COUNTNumber of occurrences waiting for Machine ClearsRAT_STALL_CYCLESCycles when the Resource Allocation Table (RAT) external stall event is sent to the Instruction Decode Queue (IDQ) for the thread. Also includes cycles when the allocator is serving another threadITLB_FLUSHFlushing of the Instruction TLB (ITLB) pages independent of page sizeREPLACEMENTL1D Data line replacementsSPLIT_LOCKNumber of split locks in the super queue (SQ)PENDINGCycles with L1D load misses outstandingPENDING_CYCLESPENDING:c=1PENDING_CYCLES_ANYCycles with L1D load misses outstanding from any threadPENDING:c=1:tOCCURRENCESNumber L1D miss outstandingPENDING:c=1:e=1EDGEFB_FULLNumber of cycles a demand request was blocked due to Fill Buffer (FB) unavailabilityWB_HITWB requests that hit L2 cacheIL2 cache lines in I state filling L2SL2 cache lines in S state filling L2EL2 cache lines in E state filling L2L2 cache lines filling L2DEMAND_CLEANNumber of clean L2 cachelines evicted by demandDEMAND_DATA_RD_MISSDemand Data Read requests that miss L2 cacheDEMAND_DATA_RD_HITDemand Data Read requests that hit L2 cacheDEMAND_RFO_MISSRFO requests that miss L2 cacheRFO_MISSDEMAND_RFO_HITRFO requests that hit L2 cacheRFO_HITCODE_RD_MISSL2 cache misses when fetching instructionsALL_DEMAND_MISSAll demand requests that miss the L2 cacheCODE_RD_HITL2 cache hits when fetching instructions, code readsL2_PF_MISSRequests from the L2 hardware prefetchers that miss L2 cachePF_MISSMISSAll requests that miss the L2 cacheL2_PF_HITRequests from the L2 hardware prefetchers that hit L2 cachePF_HITALL_DEMAND_DATA_RDAny data read request to L2 cacheALL_RFOAny data RFO request to L2 cacheALL_CODE_RDAny code read request to L2 cacheALL_DEMAND_REFERENCESAll demand requests to L2 cache ALL_PFAny L2 HW prefetch request to L2 cacheREFERENCESAll requests to L2 cacheDEMAND_DATA_RDDemand Data Read requests that access L2 cacheRFORFO requests that access L2 cacheCODE_RDL2 cache accesses when fetching instructionsL2 or L3 HW prefetches that access L2 cache, including rejectsL1D_WBL1D writebacks that access L2 cacheL2_FILLL2 fill requests that access L2 cacheL2_WBL2 writebacks that access L2 cacheALL_REQUESTSTransactions accessing L2 pipeSTORE_FORWARDCounts the number of loads blocked by overlapping with store buffer entries that cannot be forwardedNO_SRnumber of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useADDRESS_ALIASFalse dependencies in MOB due to partial compare on addressHW_PFNon software-prefetch load dispatches that hit FB allocated for hardware prefetchSW_PFNon software-prefetch load dispatches that hit FB allocated for software prefetchSPLIT_LOCK_UC_LOCK_DURATIONCycles in which the L1D and L2 are locked, due to a UC lock or split lockCACHE_LOCK_DURATIONcycles that the L1D is lockedCore-originated cacheable demand requests missed LLC - architectural eventREFERENCECore-originated cacheable demand requests that refer to LLC - architectural eventCYCLESCycles there was a Nuke. Account for both thread-specific and All Thread NukesMEMORY_ORDERINGNumber of Memory Ordering Machine Clears detectedSMCNumber of Self-modifying code (SMC) Machine Clears detectedMASKMOVThis event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0COUNTNumber of machine clears (nukes) of any typeCYCLES:c=1:eXSNP_MISSRetired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cacheXSNP_HITRetired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cacheXSNP_HITMLoad had HitM Response from a core on same socket (shared L3). (Non PEBSXSNP_NONERetired load uops which data sources were hits in L3 without snoops requiredLOCAL_DRAMRetired load uops missing L3 cache but hitting local memory (Precise Event)REMOTE_DRAMNumber of retired load uops that missed L3 but were service by remote RAM, snoop not needed, snoop miss, snoop hit data not forwarded (Precise Event)REMOTE_HITMNumber of retired load uops whose data sources was remote HITM (Precise Event)REMOTE_FWDLoad uops that miss in the L3 whose data source was forwarded from a remote cache (Precise Event)L1_HITRetired load uops with L1 cache hits as data sourceL2_HITRetired load uops with L2 cache hits as data sourceL3_HITRetired load uops with L3 cache hits as data sourceL1_MISSRetired load uops which missed the L1DL2_MISSRetired load uops which missed the L2. Unknown data source excludedL3_MISSRetired load uops which missed the L3HIT_LFBRetired load uops which missed L1 but hit line fill buffer (LFB)LOAD_LATENCYMemory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)LATENCY_ABOVE_THRESHOLDSTLB_MISS_LOADSLoad uops with true STLB miss retired to architected pathSTLB_MISS_STORESStore uops with true STLB miss retired to architected pathLOCK_LOADSLoad uops with locked access retiredSPLIT_LOADSLine-splitted load uops retiredSPLIT_STORESLine-splitted store uops retiredALL_LOADSAll load uops retiredALL_STORESAll store uops retiredLOADSSpeculative cache-line split load uops dispatched to the L1DSTORESSpeculative cache-line split store-address uops dispatched to L1DINT_ELIMINATEDNumber of integer Move Elimination candidate uops that were eliminatedSIMD_ELIMINATEDNumber of SIMD Move Elimination candidate uops that were eliminatedINT_NOT_ELIMINATEDNumber of integer Move Elimination candidate uops that were not eliminatedSIMD_NOT_ELIMINATEDNumber of SIMD Move Elimination candidate uops that were not eliminatedDemand data read requests sent to uncore (use with HT off only)DEMAND_CODE_RDDemand code read requests sent to uncore (use with HT off only)DEMAND_RFODemand RFOs requests sent to uncore (use with HT off only)ALL_DATA_RDData read requests sent to uncore (use with HT off only)AVX_TO_SSENumber of transitions from AVX-256 to legacy SSE when penalty applicableSSE_TO_AVXNumber of transitions from legacy SSE to AVX-256 when penalty applicableANY_WB_ASSISTNumber of times any microcode assist is invoked by HW upon uop writebackCycles Allocation is stalled due to Resource Related reasonRSStall cycles caused by absence of eligible entries in Reservation Station (RS)SBCycles Allocator is stalled due to Store Buffer full (not including draining from synch)ROBROB full stall cyclesLBR_INSERTSCount each time an new Last Branch Record (LBR) is insertedEMPTY_CYCLESCycles the Reservation Station (RS) is empty for this threadEMPTY_ENDNumber of times the reservation station (RS) was emptyDTLB_THREADCount number of DTLB flushes of thread-specific entriesSTLB_ANYCount number of any STLB flushesNumber of uops executed from any threadTHREADNumber of uops executed per thread each cycleSTALL_CYCLESNumber of cycles with no uops executedTHREAD:c=1:iCYCLES_GE_1_UOP_EXECCycles where at least 1 uop was executed per threadTHREAD:c=1CYCLES_GE_2_UOPS_EXECCycles where at least 2 uops were executed per threadTHREAD:c=2CYCLES_GE_3_UOPS_EXECCycles where at least 3 uops were executed per threadTHREAD:c=3CYCLES_GE_4_UOPS_EXECCycles where at least 4 uops were executed per threadTHREAD:c=4CORE_CYCLES_GE_1Cycles where at least 1 uop was executed from any threadCORE_CYCLES_GE_2Cycles where at least 2 uops were executed from any threadCORE_CYCLES_GE_3Cycles where at least 3 uops were executed from any threadCORE_CYCLES_GE_4Cycles where at least 4 uops were executed from any threadCORE_CYCLES_NONECycles where no uop is executed on any threadCORE:iPORT_0Cycles which a Uop is executed on port 0PORT_1Cycles which a Uop is executed on port 1PORT_2Cycles which a Uop is executed on port 2PORT_3Cycles which a Uop is executed on port 3PORT_4Cycles which a Uop is executed on port 4PORT_5Cycles which a Uop is executed on port 5PORT_6Cycles which a Uop is executed on port 6PORT_7Cycles which a Uop is executed on port 7PORT_0_COREtbdPORT_0:t=1PORT_1_COREPORT_1:t=1PORT_2_COREPORT_2:t=1PORT_3_COREPORT_3:t=1PORT_4_COREPORT_4:t=1PORT_5_COREPORT_5:t=1PORT_6_COREPORT_6:t=1PORT_7_COREPORT_7:t=1Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)FLAGS_MERGENumber of flags-merge uops being allocated. Such uops adds delaySLOW_LEANumber of slow LEA or similar uops allocated. Such uop has 3 sources regardless if result of LEA instruction or notSINGLE_MULNumber of Multiply packed/scalar single precision uops allocatedCounts the number of cycles no uops issued by this threadANY:c=1:i=1CORE_STALL_CYCLESCounts the number of cycles no uops issued on this coreANY:c=1:i=1:t=1All uops that actually retiredRETIRE_SLOTSnumber of retirement slots used non PEBSCycles no executable uops retired (Precise Event)ALL:i=1:c=1Number of cycles using always true condition applied to PEBS uops retired eventALL:i=1:c=10Cycles no executable uops retired on core (Precise Event)ALL:i=1:c=1:t=1STALL_OCCURRENCESNumber of transitions from stalled to unstalled execution (Precise Event)ALL:c=1:i=1:e=1DMND_DATA_RDRequest: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetchesDMND_IFETCHRequest: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesWBRequest: number of writebacks (modified to exclusive) transactionsPF_DATA_RDRequest: number of data cacheline reads generated by L2 prefetchersPF_RFORequest: number of RFO requests generated by L2 prefetchersPF_IFETCHRequest: number of code reads generated by L2 prefetchersPF_LLC_DATA_RDRequest: number of L3 prefetcher requests to L2 for loadsPF_LLC_RFORequest: number of RFO requests generated by L2 prefetcherPF_LLC_IFETCHRequest: number of L2 prefetcher requests to L3 for instruction fetchesBUS_LOCKSRequest: number bus lock and split lock requestsSTRM_STRequest: number of streaming store requestsOTHERRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockANY_IFETCHRequest: combination of PF_IFETCH | DMND_IFETCH | PF_LLC_IFETCHPF_IFETCH:DMND_IFETCH:PF_LLC_IFETCHANY_REQUESTRequest: combination of all request umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_DATA_RD:PF_RFO:PF_IFETCH:PF_LLC_DATA_RD:PF_LLC_RFO:PF_LLC_IFETCH:BUS_LOCKS:STRM_ST:OTHERANY_DATARequest: combination of DMND_DATA | PF_DATA_RD | PF_LLC_DATA_RDDMND_DATA_RD:PF_DATA_RD:PF_LLC_DATA_RDANY_RFORequest: combination of DMND_RFO | PF_RFO | PF_LLC_RFODMND_RFO:PF_RFO:PF_LLC_RFOANY_RESPONSEResponse: count any response typeNO_SUPPSupplier: counts number of times supplier information is not availableL3_HITMSupplier: counts L3 hits in M-state (initial lookup)LLC_HITML3_HITESupplier: counts L3 hits in E-stateLLC_HITEL3_HITSSupplier: counts L3 hits in S-stateLLC_HITSL3_HITFSupplier: counts L3 hits in F-stateLLC_HITFL3_HITMESFSupplier: counts L3 hits in any state (M, E, S, F)L3_HITM:L3_HITE:L3_HITS:L3_HITFLLC_HITMESFAlias for L3_HITMESFLLC_HITAlias for LLC_HITMESFL3_MISS_LOCALSupplier: counts L3 misses to local DRAMLLC_MISS_LOCALLLC_MISS_LOCAL_DRAMSupplier: counts L3 misses to local or remote DRAML3_MISS_LOCAL:L3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2PL3_MISS_REMOTE_HOP0Supplier: counts L3 misses to remote DRAM with 0 hopL3_MISS_REMOTE_HOP0_DRAML3_MISS_REMOTE_HOP1Supplier: counts L3 misses to remote DRAM with 1 hopL3_MISS_REMOTE_HOP1_DRAML3_MISS_REMOTE_HOP2PSupplier: counts L3 misses to remote DRAM with 2P hopsL3_MISS_REMOTE_HOP2P_DRAML3_MISS_REMOTESupplier: counts L3 misses to remote nodeL3_MISS_REMOTE_HOP0:L3_MISS_REMOTE_HOP1:L3_MISS_REMOTE_HOP2PL3_MISS_REMOTE_DRAMSPL_HITSupplier: counts L3 supplier hitSNP_NONESnoop: counts number of times no snoop-related information is availableSNP_NOT_NEEDEDSnoop: counts the number of times no snoop was needed to satisfy the requestSNP_MISSSnoop: counts number of times a snoop was needed and it missed all snooped cachesSNP_NO_FWDSnoop: counts number of times a snoop was needed and it hit in at leas one snooped cacheSNP_FWDSnoop: counts number of times a snoop was needed and data was forwarded from a remote socketHITMSnoop: counts number of times a snoop was needed and it hitM-ed in local or remote cacheSNP_HITMNON_DRAMSnoop: counts number of times target was a non-DRAM system address. This includes MMIO transactionsSNP_ANYSnoop: any snoop reasonSNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_NO_FWD:SNP_FWD:HITM:NON_DRAMSTARTNumber of times an HLE execution startedCOMMITNumber of times an HLE execution successfully committedABORTEDNumber of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise Event)ABORTED_MISC1Number of times an HLE execution aborted due to various memory eventsABORTED_MISC2Number of times an HLE execution aborted due to uncommon conditionsABORTED_MISC3Number of times an HLE execution aborted due to HLE-unfriendly instructionsABORTED_MISC4Number of times an HLE execution aborted due to incompatible memory typeABORTED_MISC5Number of times an HLE execution aborted due to none of the other 4 reasons (e.g., interrupt)Number of times an RTM execution startedNumber of times an RTM execution successfully committedNumber of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise Event)Number of times an RTM execution aborted due to various memory eventsNumber of times an RTM execution aborted due to uncommon conditionsNumber of times an RTM execution aborted due to RTM-unfriendly instructionsNumber of times an RTM execution aborted due to incompatible memory typeNumber of times an RTM execution aborted due to none of the other 4 reasons (e.g., interrupt)ABORT_CONFLICTNumber of times a transactional abort was signaled due to data conflict on a transactionally accessed addressABORT_CAPACITYNumber of times a transactional abort was signaled due to data capacity limitationABORT_HLE_STORE_TO_ELIDED_LOCKNumber of times a HLE transactional execution aborted due to a non xrelease prefixed instruction writing to an elided lock in the elision bufferABORT_HLE_ELISION_BUFFER_NOT_EMPTYNumber of times a HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zeroABORT_HLE_ELISION_BUFFER_MISMATCHNumber of times a HLE transaction execution aborted due to xrelease lock not satisfying the address and value requirements in the elision bufferABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENTNumber of times a HLE transaction execution aborted due to an unsupported read alignment from the elision bufferABORT_HLE_ELISION_BUFFER_FULLNumber of times a HLE clock could not be elided due to ElisionBufferAvailable being zeroMISC1Number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abortMISC2Number of times a class of instructions that may cause a transactional abort was executed inside a transactional regionMISC3Number of times an instruction execution caused the supported nest count to be exceededMISC4Number of times an instruction a xbegin instruction was executed inside HLE transactional regionMISC5Number of times an instruction with HLE xacquire prefix was executed inside a RTM transactional regionALL_DATA_RD_CYCLESCycles with cacheable data read transactions in the superQ (use with HT off only)ALL_DATA_RD:c=1DEMAND_CODE_RD_CYCLESCycles with demand code reads transactions in the superQ (use with HT off only)DEMAND_CODE_RD:c=1DEMAND_DATA_RD_CYCLESCycles with demand data read transactions in the superQ (use with HT off only)DEMAND_DATA_RD:c=1Cacheable data read transactions in the superQ every cycle (use with HT off only)Code read transactions in the superQ every cycle (use with HT off only)Demand data read transactions in the superQ every cycle (use with HT off only)DEMAND_DATA_RD_GE_6Cycles with at lesat 6 offcore outstanding demand data read requests in the uncore queueDEMAND_DATA_RD:c=6Outstanding RFO (store) transactions in the superQ every cycle (use with HT off only)DEMAND_RFO_CYCLESCycles with outstanding RFO (store) transactions in the superQ (use with HT off only)DEMAND_RFO:c=1LCPStall caused by changing prefix length of the instructionDTLB_L1Number of DTLB page walker loads that hit in the L1D and line fill bufferITLB_L1Number of ITLB page walker loads that hit in the L1I and line fill bufferDTLB_L2Number of DTLB page walker loads that hit in the L2ITLB_L2Number of ITLB page walker loads that hit in the L2DTLB_L3Number of DTLB page walker loads that hit in the L3ITLB_L3Number of ITLB page walker loads that hit in the L3DTLB_MEMORYNumber of DTLB page walker loads that hit memoryUOPSNumber of uops delivered by the Loop Stream Detector (LSD)ACTIVECycles with uops delivered by the LSD but which did not come from decoderUOPS:c=1CYCLES_4_UOPSCycles with 4 uops delivered by the LSD but which did not come from decoderUOPS:c=4PENALTY_CYCLESNumber of DSB to MITE switch true penalty cyclesWALK_CYCLESCycles for an extended page table walkFPU_DIV_ACTIVECycles when divider is busy execuing divide operationsSCALAR_DOUBLENumber of scalar double precision floating-point arithmetic instructions (multiply by 1 to get flops)SCALAR_SINGLENumber of scalar single precision floating-point arithmetic instructions (multiply by 1 to get flops)SCALARNumber of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementSCALAR_DOUBLE:SCALAR_SINGLE128B_PACKED_DOUBLENumber of scalar 128-bit packed double precision floating-point arithmetic instructions (multiply by 2 to get flops)128B_PACKED_SINGLENumber of scalar 128-bit packed single precision floating-point arithmetic instructions (multiply by 4 to get flops)256B_PACKED_DOUBLENumber of scalar 256-bit packed double precision floating-point arithmetic instructions (multiply by 4 to get flops)256B_PACKED_SINGLENumber of scalar 256-bit packed single precision floating-point arithmetic instructions (multiply by 8 to get flops)PACKEDNumber of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element128B_PACKED_DOUBLE:128B_PACKED_SINGLE:256B_PACKED_SINGLE:256B_PACKED_DOUBLESINGLENumber of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element256B_PACKED_SINGLE:128B_PACKED_SINGLE:SCALAR_SINGLEDOUBLENumber of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementSCALAR_DOUBLE:128B_PACKED_DOUBLE:256B_PACKED_DOUBLESQ_FULLNumber of cycles the offcore requests buffer is fullSIMD_PRFNumber of uops cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports exceeds the read bandwidth of the register file. This umask applies to instructions: DPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*UNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted)UNHALTED_REFERENCE_CYCLESUnhalted reference cyclesINSTRUCTION_RETIREDNumber of instructions at retirementINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instructionBR_INST_RETIRED:ALL_BRANCHESMISPREDICTED_BRANCH_RETIREDCount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwareBR_MISP_RETIRED:ALL_BRANCHESBACLEARSBranch re-steeredBR_INST_EXECBranch instructions executedBR_INST_RETIREDBranch instructions retired (Precise Event)BR_MISP_EXECMispredicted branches executedBR_MISP_RETIREDMispredicted retired branches (Precise Event)CPL_CYCLESUnhalted core cycles at a specific ring levelCPU_CLK_THREAD_UNHALTEDCPU_CLK_UNHALTEDCYCLE_ACTIVITYStalled cyclesDTLB_LOAD_MISSESData TLB load missesDTLB_STORE_MISSESData TLB store missesFP_ASSISTX87 floating-point assistsHLE_RETIREDHLE execution (Precise Event)ICACHEInstruction CacheIDQIDQ operationsIDQ_UOPS_NOT_DELIVEREDUops not deliveredINST_RETIREDNumber of instructions retired (Precise Event)INT_MISCMiscellaneous interruptionsITLBInstruction TLBITLB_MISSESInstruction TLB missesL1DL1D cacheL1D_PEND_MISSL1D pending missesL2_DEMAND_RQSTSDemand Data Read requests to L2L2_LINES_INL2 lines allocatedL2_LINES_OUTL2 lines evictedL2_RQSTSL2 requestsL2_TRANSL2 transactionsLD_BLOCKSBlocking loadsLD_BLOCKS_PARTIALPartial load blocksLOAD_HIT_PRELoad dispatchesLOCK_CYCLESLocked cycles in L1D and L2LONGEST_LAT_CACHEL3 cacheMACHINE_CLEARSMachine clear assertedMEM_LOAD_UOPS_L3_HIT_RETIREDL3 hit load uops retired (Precise Event)MEM_LOAD_UOPS_LLC_HIT_RETIREDMEM_LOAD_UOPS_L3_MISS_RETIREDLoad uops retired that missed the L3 (Precise Event)MEM_LOAD_UOPS_LLC_MISS_RETIREDMEM_LOAD_UOPS_RETIREDRetired load uops (Precise Event)MEM_TRANS_RETIREDMemory transactions retired (Precise Event)MEM_UOPS_RETIREDMemory uops retired (Precise Event)MISALIGN_MEM_REFMisaligned memory referencesMOVE_ELIMINATIONMove EliminationOFFCORE_REQUESTSDemand Data Read requests sent to uncoreOTHER_ASSISTSSoftware assistRESOURCE_STALLSROB_MISC_EVENTSROB miscellaneous eventsRS_EVENTSReservation StationRTM_RETIREDRestricted Transaction Memory execution (Precise Event)TLB_FLUSHTLB flushesUOPS_EXECUTEDUops executedLSDLoop stream detectorUOPS_EXECUTED_PORTUops dispatch to specific portsUOPS_ISSUEDUops issuedARITHArithmetic uopUOPS_RETIREDUops retired (Precise Event)TX_MEMTransactional memory abortsTX_EXECTransactional executionOFFCORE_REQUESTS_OUTSTANDINGOutstanding offcore requestsILD_STALLInstruction Length Decoder stallsPAGE_WALKER_LOADSPage walker loadsDSB2MITE_SWITCHESNumber of DSB to MITE switchesEPTExtended page tableFP_ARITHFloating-point instructions retiredFP_ARITH_INST_RETIREDOFFCORE_REQUESTS_BUFFEROffcore reqest bufferUOPS_DISPATCHES_CANCELLEDMicro-ops cancelledSQ_MISCSuperQueue miscellaneousOFFCORE_RESPONSE_0Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)OFFCORE_RESPONSE_1=GOVIntel BroadwellbdwIntel Broadwell EPbdw_epANYNumber of front-end re-steers due to BPU mispredictionCONDITIONALCounts all taken and not taken macro conditional branch instructionsCONDNEAR_CALLCounts all macro direct and indirect near callsALL_BRANCHESCounts all taken and not taken macro branches including far branches (architectural event)NEAR_RETURNCounts the number of near ret instructions retiredNOT_TAKENCounts all not taken macro branch instructions retiredNEAR_TAKENCounts the number of near branch taken instructions retiredFAR_BRANCHCounts the number of far branch instructions retiredAll mispredicted macro conditional branch instructionsAll mispredicted macro branches (architectural event)Number of near branch instructions retired that were mispredicted and takenCounts both taken and not taken retired mispredicted direct and indirect near calls, including both register and memory indirect.REF_XCLKCount Xclk pulses (100Mhz) when the core is unhaltedREF_XCLK_ANYCount Xclk pulses (100Mhz) when the at least one thread on the physical core is unhaltedREF_XCLK:tREF_PCycles when the core is unhalted (count at 100 Mhz)THREAD_PCycles when thread is not haltedONE_THREAD_ACTIVECounts Xclk (100Mhz) pulses when this thread is unhalted and the other thread is haltedRING0_TRANSCounts when the current privilege level transitions from ring 1, 2 or 3 to ring 0 (kernel)THREAD_P:e:c=1CYCLES_L2_MISSCycles with pending L2 miss demand loads outstandingCYCLES_L2_PENDINGCYCLES_L3_MISSCycles with L3 cache miss demand loads outstandingCYCLES_LDM_PENDINGCYCLES_L1D_MISSCycles with pending L1D load cache missesCYCLES_L1D_PENDINGCYCLES_MEM_ANYCycles when memory subsystem has at least one outstanding loadSTALLS_L1D_MISSExecution stalls while at least one L1D demand load cache miss is outstandingSTALLS_L2_MISSExecution stalls while at least one L2 demand load is outstandingSTALLS_L3_MISSExecution stalls while at least one L3 demand load is outstandingSTALLS_MEM_ANYExecution stalls while at least one demand load is outstanding in the memory subsystemSTALLS_TOTALTotal execution stalls in cyclesMISS_CAUSES_A_WALKMisses in all DTLB levels that cause page walksWALK_COMPLETEDNumber of misses in all TLB levels causing a page walk of any page size that completesWALK_COMPLETED_4KNumber of misses in all TLB levels causing a page walk of 4KB page size that completesWALK_COMPLETED_2M_4MNumber of misses in all TLB levels causing a page walk of 2MB/4MB page size that completesWALK_COMPLETED_1GNumber of misses in all TLB levels causing a page walk of 1GB page size that completesWALK_ACTIVECycles with at least one hardware walker active for a loadWALK_DURATIONCycles when hardware page walker is busy with page walksWALK_PENDINGSTLB_HITNumber of cache load STLB hits. No page walkCycles when PMH is busy with page walksCycles with any input/output SEE or FP assistsIFDATA_STALLCycles where a code fetch is stalled due to L1 instruction cache missIFTAG_HITNumber of instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularityIFTAG_MISSNumber of instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularityIFTAG_STALLCycles where a code fetch is stalled due to L1 instruction cache tag missMITE_UOPSNumber of uops delivered to Instruction Decode Queue (IDQ) from MITE pathDSB_UOPSNumber of uops delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) pathMS_DSB_UOPSUops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyMS_MITE_UOPSUops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyMS_UOPSNumber of Uops were delivered into Instruction Decode Queue (IDQ) from MS, initiated by Decode Stream Buffer (DSB) or MITEMS_UOPS_CYCLESNumber of cycles that Uops were delivered into Instruction Decode Queue (IDQ) when MS_Busy, initiated by Decode Stream Buffer (DSB) or MITEMS_UOPS:c=1MS_SWITCHESNumber of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode SequencerMS_UOPS:c=1:eMITE_UOPS_CYCLESCycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE pathMITE_UOPS:c=1DSB_UOPS_CYCLESCycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) pathDSB_UOPS:c=1MS_DSB_UOPS_CYCLESCycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busyMS_DSB_UOPS:c=1MS_DSB_OCCURDeliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busyMS_DSB_UOPS:c=1:e=1ALL_DSB_CYCLES_4_UOPSCycles Decode Stream Buffer (DSB) is delivering 4 UopsALL_DSB_CYCLES_ANY_UOPSCycles Decode Stream Buffer (DSB) is delivering any UopALL_MITE_CYCLES_4_UOPSCycles MITE is delivering 4 UopsALL_MITE_CYCLES_ANY_UOPSCycles MITE is delivering any UopALL_MITE_UOPSNumber of uops delivered to Instruction Decode Queue (IDQ) from any pathCORECount number of non-delivered uops to Resource Allocation Table (RAT)CYCLES_0_UOPS_DELIV_CORENumber of uops not delivered to Resource Allocation Table (RAT) per thread when backend is not stalledCYCLES_FE_WAS_OKCount cycles front-end (FE) delivered 4 uops or Resource Allocation Table (RAT) was stalling front-endCORE:c=1:iCYCLES_LE_1_UOPS_DELIV_CORECount cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend is not stalledCYCLES_LE_2_UOPS_DELIV_CORECount cycles with less than 2 uops delivered by the front-endCYCLES_LE_3_UOPS_DELIV_CORECount cycles with less then 3 uops delivered by the front-endANY_PNumber of instructions retired. General Counter - architectural eventALLPrecise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise Event)PREC_DISTTOTAL_CYCLESNumber of cycles using always true conditionPREC_DIST:i=1:c=10Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution (Precise event)RECOVERY_CYCLESCycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)RECOVERY_CYCLES_ANYCore cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)RECOVERY_CYCLES:tRECOVERY_STALLS_COUNTNumber of occurrences waiting for Machine ClearsRECOVERY_CYCLES:e:c=1CLEAR_RESTEER_CYCLESNumber of cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear eventsITLB_FLUSHFlushing of the Instruction TLB (ITLB) pages independent of page sizeREPLACEMENTL1D Data line replacementsSPLIT_LOCKNumber of split locks in the super queue (SQ)PENDINGCycles with L1D load misses outstandingFB_FULLNumber of times a request needed a fill buffer (FB) entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands load, store or SW prefetchPENDING_CYCLESPENDING:c=1PENDING_CYCLES_ANYCycles with L1D load misses outstanding from any threadPENDING:c=1:tOCCURRENCESNumber L1D miss outstandingPENDING:c=1:e=1EDGEL2 cache lines filling L2NON_SILENTCounts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped USELESS_HWPREFCounts the number of lines that have been hardware prefetched but not used and now evicted by L2 cacheUSELESS_HWPFSILENTCounts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. This is a per-core event.DEMAND_DATA_RD_MISSDemand Data Read requests that miss L2 cacheDEMAND_DATA_RD_HITDemand Data Read requests, initiated by load instructions, that hit L2 cacheDEMAND_RFO_MISSRFO requests that miss L2 cacheRFO_MISSDEMAND_RFO_HITRFO requests that hit L2 cacheRFO_HITCODE_RD_MISSL2 cache misses when fetching instructionsALL_DEMAND_MISSAll demand requests that miss the L2 cacheCODE_RD_HITL2 cache hits when fetching instructions, code readsMISSAll requests that miss the L2 cachePF_MISSRequests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cachePF_HITRequests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cacheALL_DEMAND_DATA_RDAny data read request to L2 cacheALL_RFOAny data RFO request to L2 cacheALL_CODE_RDAny code read request to L2 cacheALL_DEMAND_REFERENCESAll demand requests to L2 cache ALL_PFAny L2 HW prefetch request to L2 cacheREFERENCESAll requests to L2 cacheL2_WBL2 writebacks that access L2 cacheSTORE_FORWARDCounts the number of loads blocked by overlapping with store buffer entries that cannot be forwardedNO_SRnumber of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useADDRESS_ALIASFalse dependencies in MOB due to partial compare on addressSW_PFDemand load dispatches that hit L1D fill buffer (FB) allocated for software prefetchCACHE_LOCK_DURATIONcycles that the L1D is lockedCore-originated cacheable demand requests missed LLC - architectural eventREFERENCECore-originated cacheable demand requests that refer to LLC - architectural eventCOUNTNumber of machine clears (Nukes) of any typeMEMORY_ORDERINGNumber of Memory Ordering Machine Clears detectedSMCNumber of Self-modifying code (SMC) Machine Clears detectedXSNP_MISSRetired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cacheXSNP_HITRetired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cacheXSNP_HITMLoad had HitM Response from a core on same socket (shared L3). (Non PEBSXSNP_NONERetired load uops which data sources were hits in L3 without snoops requiredLOCAL_DRAMRetired load instructions which data sources missed L3 but serviced from local dramREMOTE_DRAMRetired load instructions which data sources missed L3 but serviced from remote dramREMOTE_HITMRetired load instructions whose data sources was remote HITMREMOTE_FWDRetired load instructions whose data sources was forwarded from a remote cacheL1_HITRetired load uops with L1 cache hits as data sourceL2_HITRetired load uops with L2 cache hits as data sourceL3_HITRetired load uops with L3 cache hits as data sourceL1_MISSRetired load uops which missed the L1DL2_MISSRetired load uops which missed the L2. Unknown data source excludedL3_MISSRetired load uops which missed the L3HIT_LFBRetired load uops which missed L1 but hit line fill buffer (LFB)FB_HITLOAD_LATENCYMemory load instructions retired above programmed clocks, minimum threshold value is 3 (Precise Event and ldlat required)LATENCY_ABOVE_THRESHOLDSTLB_MISS_LOADSLoad uops with true STLB miss retired to architected pathSTLB_MISS_STORESStore uops with true STLB miss retired to architected pathLOCK_LOADSLoad uops with locked access retiredSPLIT_LOADSLine-splitted load uops retiredSPLIT_STORESLine-splitted store uops retiredALL_LOADSAll load uops retiredALL_STORESAll store uops retiredLOADSSpeculative cache-line split load uops dispatched to the L1DSTORESSpeculative cache-line split store-address uops dispatched to L1DINT_ELIMINATEDNumber of integer Move Elimination candidate uops that were eliminatedSIMD_ELIMINATEDNumber of SIMD Move Elimination candidate uops that were eliminatedINT_NOT_ELIMINATEDNumber of integer Move Elimination candidate uops that were not eliminatedSIMD_NOT_ELIMINATEDNumber of SIMD Move Elimination candidate uops that were not eliminatedDEMAND_DATA_RDDemand data read requests sent to uncore (use with HT off only)DEMAND_CODE_RDDemand code read requests sent to uncore (use with HT off only)DEMAND_RFODemand RFOs requests sent to uncore (use with HT off only)ALL_DATA_RDData read requests sent to uncore (use with HT off only)ALL_REQUESTSNumber of memory transactions that reached the superqueue (SQ)L3_MISS_DEMAND_DATA_RDNumber of demand data read requests which missed the L3 cacheNumber of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assistsCycles Allocation is stalled due to Resource Related reasonRSStall cycles caused by absence of eligible entries in Reservation Station (RS)SBCycles Allocator is stalled due to Store Buffer full (not including draining from synch)ROBROB full stall cyclesLBR_INSERTSCount each time an new Last Branch Record (LBR) is insertedPAUSE_INSTCount number of retired PAUSE instructions (that do not end up with a VMEXIT to the VMM; TSX aborted instructions may be counted). This event is not supported on first SKL and KBL processorsEMPTY_CYCLESCycles the Reservation Station (RS) is empty for this threadEMPTY_ENDNumber of times the reservation station (RS) was emptyDTLB_THREADCount number of DTLB flushes of thread-specific entriesSTLB_ANYCount number of any STLB flushesTHREADNumber of uops executed per thread in each cycleTHREAD_CYCLES_GE_1Number of cycles with at least 1 uop is executed per threadTHREAD_CYCLES_GE_2Number of cycles with at least 2 uops are executed per threadTHREAD_CYCLES_GE_3Number of cycles with at least 3 uops are executed per threadTHREAD_CYCLES_GE_4Number of cycles with at least 4 uops are executed per threadNumber of uops executed from any thread in each cycleCORE_CYCLES_GE_1Number of cycles with at least 1 uop is executed for any threadCORE_CYCLES_GE_2Number of cycles with at least 2 uops are executed for any threadCORE_CYCLES_GE_3Number of cycles with at least 3 uops are executed for any threadCORE_CYCLES_GE_4Number of cycles with at least 4 uops are executed for any threadSTALL_CYCLESNumber of cycles with no uops executed by threadTHREAD:c=1:iCORE_CYCLES_NONENumber of cycles with no uops executed from any threadX87Number of x87 uops executed per threadPORT_0Cycles which a Uop is executed on port 0PORT_1Cycles which a Uop is executed on port 1PORT_2Cycles which a Uop is executed on port 2PORT_3Cycles which a Uop is executed on port 3PORT_4Cycles which a Uop is executed on port 4PORT_5Cycles which a Uop is executed on port 5PORT_6Cycles which a Uop is executed on port 6PORT_7Cycles which a Uop is executed on port 7PORT_0_COREtbdPORT_0:t=1PORT_1_COREPORT_1:t=1PORT_2_COREPORT_2:t=1PORT_3_COREPORT_3:t=1PORT_4_COREPORT_4:t=1PORT_5_COREPORT_5:t=1PORT_6_COREPORT_6:t=1PORT_7_COREPORT_7:t=1Number of Uops issued by the Resource Allocation Table (RAT) to the Reservation Station (RS)VECTOR_WIDTH_MISMATCHNumber of blend uops issued by the Resource Allocation table (RAT) to the Reservation Station (RS) in order to preserve upper bits of vector registersFLAGS_MERGENumber of flags-merge uops being allocated. Such uops adds delaySLOW_LEANumber of slow LEA or similar uops allocated. Such uop has 3 sources regardless if result of LEA instruction or notSINGLE_MULNumber of Multiply packed/scalar single precision uops allocatedCounts the number of cycles no uops issued by this threadANY:c=1:i=1CORE_STALL_CYCLESCounts the number of cycles no uops issued on this coreANY:c=1:i=1:t=1All uops that actually retiredRETIRE_SLOTSnumber of retirement slots used non PEBSCycles no executable uops retired (Precise Event)ALL:c=1:iNumber of cycles using always true condition applied to PEBS uops retired eventALL:c=10:iCycles no executable uops retired on core (Precise Event)ALL:c=1:i:t=1STALL_OCCURRENCESNumber of transitions from stalled to unstalled execution (Precise Event)ALL:c=1:i=1:e=1DMND_DATA_RDRequest: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetchesDMND_CODE_RDRequest: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesPF_L2_DATA_RDRequest: number of data prefetch requests to L2PF_L2_RFORequest: number of RFO prefetch requests to L2PF_L3_DATA_RDRequest: number of data prefetch requests for loads that end up in L3PF_L3_RFORequest: number of RFO prefetch requests that end up in L3PF_L1D_AND_SWRequest: number of L1 data cache hardware prefetch requests and software prefetch requestsOTHERRequest: counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lockANY_REQUESTRequest: combination of all request umasksDMND_DATA_RD:DMND_RFO:DMND_CODE_RD:OTHERDMND_DATA_RD:DMND_RFO:DMND_CODE_RD:PF_L2_DATA_RD:PF_L2_RFO:PF_L3_DATA_RD:PF_L3_RFO:PF_L1D_AND_SW:OTHERANY_DATA_RDRequest: combination of DMND_DATA_RD | PF_L2_DATA_RD | PF_L3_DATA_RD | PF_L1D_AND_SWDMND_DATA_RD:PF_L2_DATA_RD:PF_L3_DATA_RD:PF_L1D_AND_SWANY_DATARequest: combination of ANY_DATA_RD | PF_L2_RFO | PF_L3_RFO | DMND_RFOANY_DATA_RD:DMND_RFO:PF_L2_RFO:PF_L3_RFOANY_DATA_PFRequest: combination of PF_L2_DATA_RD | PF_L3_DATA_RD | PF_L1D_AND_SWPF_L2_DATA_RD:PF_L3_DATA_RD:PF_L1D_AND_SWANY_RFORequest: combination of DMND_RFO | PF_L2_RFO | PF_L3_RFODMND_RFO:PF_L2_RFO:PF_L3_RFOANY_RESPONSEResponse: count any response typeSUPPLIER_NONESupplier: counts number of times supplier information is not availableNO_SUPPL3_HITMSupplier: counts L3 hits in M-state (initial lookup)L3_HITESupplier: counts L3 hits in E-stateL3_HITSSupplier: counts L3 hits in S-stateL3_HITFSupplier: counts L3 hits in F-stateL3_HITMESSupplier: counts L3 hits in any state (M, E, S)L3_HITM:L3_HITE:L3_HITSAlias for L3_HITMESL3_HITMESFSupplier: counts L3 hits in any state (M, E, S, F)L3_HITM:L3_HITE:L3_HITS:L3_HITFL4_HIT_LOCAL_L4Supplier: L4 local hitL3_MISS_LOCALSupplier: counts L3 misses to local DRAML3_MISS_MISS_REMOTE_HOP1_DRAMSupplier: counts L3 misses to remote DRAM with 1 hopSupplier: counts L3 missesSupplier: counts L3 misses (local or remote)SPL_HITSnoop: counts L3 supplier hitSNP_NONESnoop: counts number of times no snoop-related information is availableSNP_NOT_NEEDEDSnoop: counts the number of times no snoop was needed to satisfy the requestSNP_MISSSnoop: counts number of times a snoop was needed and it missed all snooped cachesSNP_HIT_NO_FWDSnoop: counts number of times a snoop was needed and it hit in at leas one snooped cacheSNP_HIT_WITH_FWDSnoop: counts number of times a snoop was needed and data was forwarded from a remote socketSNP_HITMSnoop: counts number of times a snoop was needed and it hitM-ed in local or remote cacheSNP_NON_DRAMSnoop: counts number of times target was a non-DRAM system address. This includes MMIO transactionsSNP_ANYSnoop: any snoop reasonSNP_NONE:SNP_NOT_NEEDED:SNP_MISS:SNP_HIT_NO_FWD:SNP_HIT_WITH_FWD:SNP_HITM:SNP_NON_DRAMSTARTNumber of times an HLE execution startedCOMMITNumber of times an HLE execution successfully committedABORTEDNumber of times an HLE execution aborted due to any reasons (multiple categories may count as one) (Precise Event)ABORTED_MEMNumber of times an HLE execution aborted due to various memory eventsABORTED_TMRNumber of times an HLE execution aborted due to hardware timer expirationABORTED_UNFRIENDLYNumber of times an HLE execution aborted due to HLE-unfriendly instructions and certain events such as AD-assistsABORTED_MEMTYPENumber of times an HLE execution aborted due to incompatible memory typeABORTED_EVENTSNumber of times an HLE execution aborted due to none of the other 4 reasons (e.g., interrupt)Number of times an RTM execution startedNumber of times an RTM execution successfully committedNumber of times an RTM execution aborted due to any reasons (multiple categories may count as one) (Precise Event)Number of times an RTM execution aborted due to various memory eventsNumber of times an RTM execution aborted due to uncommon conditionsNumber of times an RTM execution aborted due to RTM-unfriendly instructionsNumber of times an RTM execution aborted due to incompatible memory typeNumber of times an RTM execution aborted due to none of the other 4 reasons (e.g., interrupt)ABORT_CONFLICTNumber of times a transactional abort was signaled due to data conflict on a transactionally accessed addressABORT_CAPACITYNumber of times a transactional abort was signaled due to data capacity limitationABORT_HLE_STORE_TO_ELIDED_LOCKNumber of times a HLE transactional execution aborted due to a non xrelease prefixed instruction writing to an elided lock in the elision bufferABORT_HLE_ELISION_BUFFER_NOT_EMPTYNumber of times a HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zeroABORT_HLE_ELISION_BUFFER_MISMATCHNumber of times a HLE transaction execution aborted due to xrelease lock not satisfying the address and value requirements in the elision bufferABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENTNumber of times a HLE transaction execution aborted due to an unsupported read alignment from the elision bufferABORT_HLE_ELISION_BUFFER_FULLNumber of times a HLE clock could not be elided due to ElisionBufferAvailable being zeroMISC1Number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abortMISC2Number of times a class of instructions that may cause a transactional abort was executed inside a transactional regionMISC3Number of times an instruction execution caused the supported nest count to be exceededMISC4Number of times an instruction a xbegin instruction was executed inside HLE transactional regionMISC5Number of times an instruction with HLE xacquire prefix was executed inside a RTM transactional regionALL_DATA_RD_CYCLESCycles with cacheable data read transactions in the superQ (use with HT off only)ALL_DATA_RD:c=1DEMAND_CODE_RD_CYCLESCycles with demand code reads transactions in the superQ (use with HT off only)DEMAND_CODE_RD:c=1CYCLES_WITH_DEMAND_CODE_RDDEMAND_DATA_RD_CYCLESCycles with demand data read transactions in the superQ (use with HT off only)DEMAND_DATA_RD:c=1CYCLES_WITH_DEMAND_DATA_RDCacheable data read transactions in the superQ every cycle (use with HT off only)Code read transactions in the superQ every cycle (use with HT off only)Demand data read transactions in the superQ every cycle (use with HT off only)DEMAND_DATA_RD_GE_6Cycles with at lesat 6 offcore outstanding demand data read requests in the uncore queueDEMAND_DATA_RD:c=6Outstanding RFO (store) transactions in the superQ every cycle (use with HT off only)DEMAND_RFO_CYCLESCycles with outstanding RFO (store) transactions in the superQ (use with HT off only)DEMAND_RFO:c=1CYCLES_WITH_DEMAND_RFONumber of offcore outstanding demand data read requests missing the L3 cache every cycleL3_MISS_DEMAND_DATA_RD_GE_6Number of cycles in which at least 6 demand data read requests missing the L3CYCLES_WITH_L3_MISS_DEMAND_DATA_RDCycles with at least 1 Demand Data Read requests who miss L3 cache in the superQLCPStall caused by changing prefix length of the instructionUOPSNumber of uops delivered by the Loop Stream Detector (LSD)CYCLES_4_UOPSNumber of cycles the LSD delivered 4 uops which did not come from the decoderCYCLES_ACTIVENumber of cycles the LSD delivered uops which did not come from the decoderPENALTY_CYCLESNumber of DSB to MITE switch true penalty cyclesCycles for an extended page table walk of any typeDIVIDER_ACTIVECycles when divider is busy executing divide or square root operations on integers or floating-pointsFPU_DIV_ACTIVESCALAR_DOUBLENumber of scalar double precision floating-point arithmetic instructions (multiply by 1 to get flops)SCALAR_SINGLENumber of scalar single precision floating-point arithmetic instructions (multiply by 1 to get flops)128B_PACKED_DOUBLENumber of scalar 128-bit packed double precision floating-point arithmetic instructions (multiply by 2 to get flops)128B_PACKED_SINGLENumber of scalar 128-bit packed single precision floating-point arithmetic instructions (multiply by 4 to get flops)256B_PACKED_DOUBLENumber of scalar 256-bit packed double precision floating-point arithmetic instructions (multiply by 4 to get flops)256B_PACKED_SINGLENumber of scalar 256-bit packed single precision floating-point arithmetic instructions (multiply by 8 to get flops)512B_PACKED_DOUBLENumber of scalar 512-bit packed double precision floating-point arithmetic instructions (multiply by 8 to get flops)512B_PACKED_SINGLENumber of scalar 512-bit packed single precision floating-point arithmetic instructions (multiply by 16 to get flops)1_PORTS_UTILCycles with 1 uop executing across all ports and Reservation Station is not empty2_PORTS_UTILCycles with 2 uops executing across all ports and Reservation Station is not empty3_PORTS_UTILCycles with 3 uops executing across all ports and Reservation Station is not empty4_PORTS_UTILCycles with 4 uops executing across all ports and Reservation Station is not emptyBOUND_ON_STORESCycles where the store buffer is full and no outstanding loadEXE_BOUND_0_PORTSCycles where no uop is executed and the Reservation Station was not emptyDSB_MISSRetired instructions experiencing decode stream buffer (DSB) missITLB_MISSRetired instructions experiencing ITLB true missL1I_MISSRetired instructions experiencing L1I cache true missRetired instructions experiencing instruction L2 cache true missSTLB_MISSRetired instructions experiencing STLB (2nd level TLB) true missIDQ_4_BUBBLESRetired instructions after an interval where the front-end did not deliver any uops (4 bubbles) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stallIDQ_3_BUBBLESCounts instructions retired after an interval where the front-end did not deliver more than 1 uop (3 bubbles) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stallIDQ_2_BUBBLESCounts instructions retired after an interval where the front-end did not deliver more than 2 uops (2 bubbles) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stallIDQ_1_BUBBLECounts instructions retired after an interval where the front-end did not deliver more than 3 uops (1 bubble) for a period determined by the fe_thres modifier and which was not interrupted by a back-end stallRECEIVEDNumber of hardware interrupts received by the processorSQ_FULLNumber of requests for which the offcore buffer (SQ) is fullUCNumber of uncached load retiredWB_UPGRADECounts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortlyWB_DOWNGRADECounts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortlyLVL0_TURBO_LICENSENumber of core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.LVL1_TURBO_LICENSENumber of core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.LVL2_TURBO_LICENSENumber of core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.THROTTLENumber of core cycles where the core was throttled due to a pending power level request.NTANumber of prefetch.nta instructions executedT0Number of prefetch.t0 instructions executedT1_T2Number prefetch.t1 or prefetch.t2 instructions executedPREFETCHWNumber prefetch.w instructions executedRSP_IHITITBDRSP_IHITFSERSP_SHITFSERSP_SFWDMRSP_IFWDMRSP_IFWDFERSP_SFWDFESCOREBOARDCount core cycles where the pipeline is stalled due to serialization operationsUNHALTED_CORE_CYCLESCount core clock cycles whenever the clock signal on the specific core is running (not halted)UNHALTED_REFERENCE_CYCLESUnhalted reference cyclesINSTRUCTION_RETIREDNumber of instructions at retirementINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDBRANCH_INSTRUCTIONS_RETIREDCount branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instructionBR_INST_RETIRED:ALL_BRANCHESMISPREDICTED_BRANCH_RETIREDCount mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardwareBR_MISP_RETIRED:ALL_BRANCHESBACLEARSBranch re-steeredBR_INST_RETIREDBranch instructions retired (Precise Event)BR_MISP_RETIREDMispredicted retired branches (Precise Event)CPU_CLK_THREAD_UNHALTEDCPU_CLK_UNHALTEDCYCLE_ACTIVITYStalled cyclesDTLB_LOAD_MISSESData TLB load missesDTLB_STORE_MISSESData TLB store missesFP_ASSISTX87 floating-point assistsHLE_RETIREDHLE execution (Precise Event)ICACHE_16BInstruction CacheICACHE_64BIDQIDQ operationsIDQ_UOPS_NOT_DELIVEREDUops not deliveredINST_RETIREDNumber of instructions retired (Precise Event)INT_MISCMiscellaneous interruptionsITLBInstruction TLBITLB_MISSESInstruction TLB missesL1DL1D cacheL1D_PEND_MISSL1D pending missesL2_LINES_INL2 lines allocatedL2_LINES_OUTL2 lines evictedL2_RQSTSL2 requestsL2_TRANSL2 transactionsLD_BLOCKSBlocking loadsLD_BLOCKS_PARTIALPartial load blocksLOAD_HIT_PRELoad dispatchesLOCK_CYCLESLocked cycles in L1D and L2LONGEST_LAT_CACHEL3 cacheMACHINE_CLEARSMachine clear assertedMEM_LOAD_L3_HIT_RETIREDL3 hit load uops retired (Precise Event)MEM_LOAD_UOPS_L3_HIT_RETIREDMEM_LOAD_UOPS_LLC_HIT_RETIREDMEM_LOAD_L3_MISS_RETIREDL3 miss load uops retired (Precise Event)MEM_LOAD_UOPS_L3_MISS_RETIREDMEM_LOAD_UOPS_LLC_MISS_RETIREDMEM_LOAD_RETIREDRetired load uops (Precise Event)MEM_LOAD_UOPS_RETIREDMEM_TRANS_RETIREDMemory transactions retired (Precise Event)MEM_INST_RETIREDMemory instructions retired (Precise Event)MEM_UOPS_RETIREDMISALIGN_MEM_REFMisaligned memory referencesMOVE_ELIMINATIONMove EliminationOFFCORE_REQUESTSDemand Data Read requests sent to uncoreOTHER_ASSISTSSoftware assistRESOURCE_STALLSROB_MISC_EVENTSROB miscellaneous eventsRS_EVENTSReservation StationRTM_RETIREDRestricted Transaction Memory execution (Precise Event)TLB_FLUSHTLB flushesUOPS_EXECUTEDUops executedLSDLoop stream detectorUOPS_DISPATCHED_PORTUops dispatched to specific portsUOPS_DISPATCHEDUOPS_ISSUEDUops issuedARITHArithmetic uopUOPS_RETIREDUops retired (Precise Event)TX_MEMTransactional memory abortsTX_EXECTransactional executionOFFCORE_REQUESTS_OUTSTANDINGOutstanding offcore requestsILD_STALLInstruction Length Decoder stallsDSB2MITE_SWITCHESNumber of DSB to MITE switchesEPTExtended page tableFP_ARITHFloating-point instructions retiredFP_ARITH_INST_RETIREDEXE_ACTIVITYExecution activityFRONTEND_RETIREDPrecise Front-End activityHW_INTERRUPTSSQ_MISCSuperQueue miscellaneousMEM_LOAD_MISC_RETIREDLoad retired miscellaneousIDI_MISCMiscellaneousCORE_POWERPower power cyclesSW_PREFETCHSoftware prefetchesSW_PREFETCH_ACCESSCORE_SNOOP_RESPONSEAggregated core snoopsPARTIAL_RAT_STALLSRAT stallsOFFCORE_REQUESTS_BUFFEROffcore requests bufferOFFCORE_RESPONSE_0Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)OFFCORE_RESPONSE_1N^UIntel SkylakesklIntel Skylake XskxRAPL_ENERGY_CORESNumber of Joules consumed by all cores on the package. Unit is 2^-32 JoulesRAPL_ENERGY_PKGNumber of Joules consumed by all cores and Last level cache on the package. Unit is 2^-32 JoulesRAPL_ENERGY_GPUNumber of Joules consumed by the builtin GPU. Unit is 2^-32 JoulesRAPL_ENERGY_PSYSNumber of Joules consumed by the builtin PSYS. Unit is 2^-32 JoulesRAPL_ENERGY_DRAMNumber of Joules consumed by the DRAM. Unit is 2^-32 Joules    է  է է է%s[0x%lx event=0x%x] %s Intel RAPLraplpowereedge detectiinverttthreshold in range [0-255]threshold in range [0-31]tfthread id filter [0-1]cfcore id filter, includes non-thread data in bit 4 [0-15]nfnode id bitmask filter [0-255]fffrequency >= 100Mhz * [0-255]addrphysical address matcher [40 bits]isocmatch isochronous requestsncmatch non-coherent requestscore id filter, includes non-thread data in bit 5 [0-63]thread id filter [0-3]source id filter [0-63]locmatch on local node targetremmatch on remote node targetlmemlocal memory cacheablermemremote memory cacheabledniddestination node id [0-15]rcsniddestination RCS Node id [0-15][UNC=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s pfmlib_intel_snbep_unc.c%s (%s.%d): added default %s for group %d j=%d idx=%d ucode=0x%lx %s (%s.%d): two max_grpid, old=%d new=%d %s (%s.%d): no default found for event %s unit mask group %d (max_grpid=%d, i=%d) %s (%s.%d): max_grpid=%d nattrs=%d k=%d umask=0x%lx %s (%s.%d): exclusive unit mask group error %s (%s.%d): event requires grpid %d %s (%s.%d): max_req_grpid=%d %s (%s.%d): umask %s does not support unit mask combination within group %d :%s%s (%s.%d): raw umask is 8-bit wide %s (%s.%d): invalid thread id, must be < 1%s (%s.%d): invalid nf, 0 < nf < 256 %s (%s.%d): address filter 40bits max %s (%s.%d): dnid must be [0-15] %s (%s.%d): rcsnid must be [0-15] %s (%s.%d): event %s invalid attribute %d %s (%s.%d): required grpid %d umask missing %s (%s.%d): event has umasks but none specified %s (%s.%d): using nf= on an umask which does not require it %s (%s.%d): required modifiers missing: 0x%x %s:0x%x%s (%s.%d): umask2=0x%lx umask1=0x%lx :%s=%lu:%s=0x%lx%s (%s.%d): unknown attribute %d for event %s C-]{6s޹|׷ ͺDnܻ{>fz 4Mqsnbep_unc_add_defaultspfm_intel_snbep_unc_get_encodingANYAny requestDATA_READData read requestsWRITEWrite requests. Includes all write transactions (cached, uncached)REMOTE_SNOOPExternal snoop requestNIDMatch a given RTID destination NID (must provide nf=X modifier)STATE_IInvalid cacheline stateSTATE_SShared cacheline stateSTATE_EExclusive cacheline stateSTATE_MModified cacheline stateSTATE_FForward cacheline stateSTATE_MESIFAny cache line stateM_STATELines in M stateE_STATELines in E stateS_STATELines in S stateMISSTBDVictimized Lines matching the NID filter (must provide nf=X modifier)RSPI_WAS_FSESilent snoop evictionWC_ALIASINGWrite combining aliasingSTARTEDRFO_HIT_SRFO hits in S stateUP_EVENUp and Even ring polarity filterUP_ODDUp and odd ring polarity filterDOWN_EVENDown and even ring polarity filterDOWN_ODDDown and odd ring polarity filterAK_COREAcknowledgment to coreBL_COREData response to coreIV_CORESnoops of processor cacheAny filterIRQIrq externally starved, therefore blocking the IPQIPQIPQ externally starved, therefore blocking the IRQISMQISMQ externally starved, therefore blocking both IRQ and IPQISMQ_BIDSNumber of time the ISMQ bidsIRQ_REJECTEDIRQ rejectedVFIFOCounts the number of allocated into the IRQ ordering FIFOADDR_CONFLICTAddress conflictAny RejectFULLNo Egress creditsQPI_CREDITSNo QPI creditsAny rejectRTIDNo RTIDsIIO_CREDITSNo IIO creditsNO QPI creditsEVICTIONNumber of Evictions transactions inserted into TORMISS_ALLNumber of miss requests inserted into the TORMISS_OPCODENumber of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)NID_ALLNumber of NID-matched transactions inserted into the TOR (must provide nf=X modifier)NID_EVICTIONNumber of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)NID_MISS_ALLNumber of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)NID_MISS_OPCODENumber of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)NID_OPCODENumber of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)NID_WBNumber of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)OPCODENumber of transactions inserted into the TOR that match an opcode (must provide opc_* umask)WBNumber of write transactions inserted into the TOROPC_RFODemand data RFO (combine with any OPCODE umask)OPC_CRDDemand code read (combine with any OPCODE umask)OPC_DRDDemand data read (combine with any OPCODE umask)OPC_PRDPartial reads (UC) (combine with any OPCODE umask)OPC_WCILFFull Stream store (combine with any OPCODE umask)OPC_WCILPartial Stream store (combine with any OPCODE umask)OPC_PF_RFOPrefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PF_CODEPrefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PF_DATAPrefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PCIWILFPCIe write (non-allocating) (combine with any OPCODE umask)OPC_PCIPRDPCIe UC read (combine with any OPCODE umask)OPC_PCIITOMPCIe write (allocating) (combine with any OPCODE umask)OPC_PCIRDCURPCIe read current (combine with any OPCODE umask)OPC_WBMTOIRequest writeback modified invalidate line (combine with any OPCODE umask)OPC_WBMTOERequest writeback modified set to exclusive (combine with any OPCODE umask)OPC_ITOMRequest invalidate line (combine with any OPCODE umask)OPC_PCINSRDPCIe non-snoop read (combine with any OPCODE umask)OPC_PCINSWRPCIe non-snoop write (partial) (combine with any OPCODE umask)OPC_PCINSWRFPCIe non-snoop write (full) (combine with any OPCODE umask)ALLAll valid TOR entriesNumber of outstanding eviction transactions in the TORNumber of outstanding miss requests in the TORNumber of TOR entries that match a NID and an opcode (must provide opc_* umask)Number of NID-matched outstanding requests in the TOR (must provide nf=X modifier)Number of NID-matched outstanding requests in the TOR (must provide a nf=X modifier)Number of NID-matched outstanding miss requests in the TOR (must provide a nf=X modifier)Number of NID-matched outstanding miss requests in the TOR that an opcode (must provide nf=X modifier and opc_* umask)Number of NID-matched TOR entries that an opcode (must provide nf=X modifier and opc_* umask)Number of TOR entries that match an opcode (must provide opc_* umask)AD_CACHECounts the number of ring transactions from Cachebo to AD ringAK_CACHECounts the number of ring transactions from Cachebo to AK ringBL_CACHECounts the number of ring transactions from Cachebo to BL ringIV_CACHECounts the number of ring transactions from Cachebo to IV ringAD_CORECounts the number of ring transactions from Corebo to AD ringCounts the number of ring transactions from Corebo to AK ringCounts the number of ring transactions from Corebo to BL ringUNC_C_CLOCKTICKSC-box Uncore clockticksUNC_C_COUNTER0_OCCUPANCYCounter 0 occupancy. Counts the occupancy related information by filtering CB0 occupancy count captured in counter 0.UNC_C_ISMQ_DRD_MISS_OCCUNC_C_LLC_LOOKUPCache lookups. Counts number of times the LLC is accessed from L2 for code, data, prefetches (Must set filter mask bit 0 and select )UNC_C_LLC_VICTIMSLines victimizedUNC_C_MISCMiscellaneous C-Box eventsUNC_C_RING_AD_USEDAddress ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_AK_USEDAcknowledgment ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_BL_USEDBus or Data ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_BOUNCESNumber of LLC responses that bounced in the ringUNC_C_RING_IV_USEDInvalidate ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_SRC_THRTLTDBUNC_C_RXR_EXT_STARVEDIngress arbiter blocking cyclesUNC_C_RXR_INSERTSIngress AllocationsUNC_C_RXR_IPQ_RETRYProbe Queue RetriesUNC_C_RXR_IRQ_RETRYIngress Request Queue RejectsUNC_C_RXR_ISMQ_RETRYISMQ RetriesUNC_C_RXR_OCCUPANCYIngress OccupancyUNC_C_TOR_INSERTSTOR InsertsUNC_C_TOR_OCCUPANCYTOR OccupancyUNC_C_TXR_ADS_USEDEgress eventsUNC_C_TXR_INSERTSEgress allocations[UNC_CBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d tid_en=%d] %s [UNC_CBOX_FILTER=0x%lx tid=%d core=0x%x nid=0x%x state=0x%x opc=0x%x] Intel Sandy Bridge-EP C-Box 0 uncoresnbep_unc_cbo0uncore_cbox_0Intel Sandy Bridge-EP C-Box 1 uncoresnbep_unc_cbo1uncore_cbox_1Intel Sandy Bridge-EP C-Box 2 uncoresnbep_unc_cbo2uncore_cbox_2Intel Sandy Bridge-EP C-Box 3 uncoresnbep_unc_cbo3uncore_cbox_3Intel Sandy Bridge-EP C-Box 4 uncoresnbep_unc_cbo4uncore_cbox_4Intel Sandy Bridge-EP C-Box 5 uncoresnbep_unc_cbo5uncore_cbox_5Intel Sandy Bridge-EP C-Box 6 uncoresnbep_unc_cbo6uncore_cbox_6Intel Sandy Bridge-EP C-Box 7 uncoresnbep_unc_cbo7uncore_cbox_7CONFLICTNumber of cycles that we are handling conflictsNO_CONFLICTNumber of cycles that we are not handling conflictsNO_SNPSnoop not neededSNPSnoop neededANYCounts any directory updateCLEARDirectory clearsSETDirectory setAD_QPI0AD to QPI link 0AD_QPI1AD to QPI link 1BL_QPI0BL to QPI link 0BL_QPI1BL to QPI link 1ALLCounts all writesFULLCounts full line non ISOCHFULL_ISOCHCounts ISOCH full linePARTIALCounts partial non-ISOCHPARTIAL_ISOCHCounts ISOCH partialREADSCounts incoming read requests. Good proxy for LLC read misses, incl. RFOsWRITESCounts incoming writesCHN0Channel 0CHN1Channel 1CHN2channel 2CHN3Chanell 3REGION0Counts for TAD Region 0REGION1Counts for TAD Region 1REGION2Counts for TAD Region 2REGION3Counts for TAD Region 3REGION4Counts for TAD Region 4REGION5Counts for TAD Region 5REGION6Counts for TAD Region 6REGION7Counts for TAD Region 7REGION8Counts for TAD Region 8REGION9Counts for TAD Region 9REGION10Counts for TAD Region 10REGION11Counts for TAD Region 11Counts all requestsNDRCounts non-data responsesCounts outbound snoops send on the ringCounts cycles full from both schedulersSCHED0Counts cycles full from scheduler bank 0SCHED1Counts cycles full from scheduler bank 1Counts cycles from both schedulersCounts cycles from scheduler bank 0Counts cycles from scheduler bank 1DRS_CACHECounts data being sent to the cacheDRS_CORECounts data being sent directly to the requesting coreDRS_QPICounts data being sent to a remote socket over QPIUNC_H_CLOCKTICKSHA Uncore clockticksUNC_H_CONFLICT_CYCLESConflict ChecksUNC_H_DIRECT2CORE_COUNTDirect2Core Messages SentUNC_H_DIRECT2CORE_CYCLES_DISABLEDCycles when Direct2Core was DisabledUNC_H_DIRECT2CORE_TXN_OVERRIDENumber of Reads that had Direct2Core OverriddenUNC_H_DIRECTORY_LOOKUPDirectory LookupsUNC_H_DIRECTORY_UPDATEDirectory UpdatesUNC_H_IGR_NO_CREDIT_CYCLESCycles without QPI Ingress CreditsUNC_H_IMC_RETRYRetry EventsUNC_H_IMC_WRITESHA to iMC Full Line Writes IssuedUNC_H_REQUESTSRead and Write RequestsUNC_H_RPQ_CYCLES_NO_REG_CREDITSiMC RPQ Credits Empty - RegularUNC_H_TAD_REQUESTS_G0HA Requests to a TAD Region - Group 0UNC_H_TAD_REQUESTS_G1HA Requests to a TAD Region - Group 1UNC_H_TRACKER_INSERTSTracker AllocationsUNC_H_TXR_ADOutbound NDR Ring TransactionsUNC_H_TXR_AD_CYCLES_FULLAD Egress FullUNC_H_TXR_AK_CYCLES_FULLAK Egress FullUNC_H_TXR_AK_NDRUNC_H_TXR_BLOutbound DRS Ring Transactions to CacheUNC_H_TXR_BL_CYCLES_FULLBL Egress FullUNC_H_WPQ_CYCLES_NO_REG_CREDITSHA iMC CHN0 WPQ Credits Empty - Regular[UNC_HA=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s [UNC_HA_ADDR=0x%lx lo_addr=0x%x hi_addr=0x%x] [UNC_HA_OPC=0x%lx opc=0x%x] Intel Sandy Bridge-EP HA uncoresnbep_unc_hauncore_haALLCounts total number of DRAM CAS commands issued on this channelRDCounts all DRAM reads on this channel, incl. underfillsRD_REGCounts number of DRAM read CAS commands issued on this channel, incl. regular read CAS and those with implicit prechargeRD_UNDERFILLCounts number of underfill reads issued by the memory controllerWRCounts number of DRAM write CAS commands on this channelWR_RMMCounts Number of opportunistic DRAM write CAS commands issued on this channelWR_WMMCounts number of DRAM write CAS commands issued on this channel while in Write-Major modeHIGHTBDPANICISOCHCounts cycles in ISOCH Major modePARTIALCounts cycles in Partial Major modeREADCounts cycles in Read Major modeWRITECounts cycles in Write Major modeRANK0Count cycles for rank 0RANK1Count cycles for rank 1RANK2Count cycles for rank 2RANK3Count cycles for rank 3RANK4Count cycles for rank 4RANK5Count cycles for rank 5RANK6Count cycles for rank 6RANK7Count cycles for rank 7RD_PREEMPT_RDCounts read over read preemptionsRD_PREEMPT_WRCounts read over write preemptionsPAGE_CLOSECounts number of DRAM precharge commands sent on this channel as a result of the page close counter expiringPAGE_MISSCounts number of DRAM precharge commands sent on this channel as a result of page missesUNC_M_CLOCKTICKSIMC Uncore clockticksUNC_M_ACT_COUNTDRAM Activate CountUNC_M_CAS_COUNTDRAM RD_CAS and WR_CAS Commands.UNC_M_DRAM_PRE_ALLDRAM Precharge All CommandsUNC_M_DRAM_REFRESHNumber of DRAM Refreshes IssuedUNC_M_ECC_CORRECTABLE_ERRORSECC Correctable ErrorsUNC_M_MAJOR_MODESCycles in a Major ModeUNC_M_POWER_CHANNEL_DLLOFFChannel DLLOFF CyclesUNC_M_POWER_CHANNEL_PPDChannel PPD CyclesUNC_M_POWER_CKE_CYCLESCKE_ON_CYCLES by RankUNC_M_POWER_CRITICAL_THROTTLE_CYCLESCritical Throttle CyclesUNC_M_POWER_SELF_REFRESHClock-Enabled Self-RefreshUNC_M_POWER_THROTTLE_CYCLESThrottle Cycles for Rank 0UNC_M_PREEMPTIONRead Preemption CountUNC_M_PRE_COUNTDRAM Precharge commands.UNC_M_RPQ_CYCLES_FULLRead Pending Queue Full CyclesUNC_M_RPQ_CYCLES_NERead Pending Queue Not EmptyUNC_M_RPQ_INSERTSRead Pending Queue AllocationsUNC_M_RPQ_OCCUPANCYRead Pending Queue OccupancyUNC_M_WPQ_CYCLES_FULLWrite Pending Queue Full CyclesUNC_M_WPQ_CYCLES_NEWrite Pending Queue Not EmptyUNC_M_WPQ_INSERTSWrite Pending Queue AllocationsUNC_M_WPQ_OCCUPANCYWrite Pending Queue OccupancyUNC_M_WPQ_READ_HITWrite Pending Queue CAM MatchUNC_M_WPQ_WRITE_HITIntel Sandy Bridge-EP IMC0 uncoresnbep_unc_imc0uncore_imc_0Intel Sandy Bridge-EP IMC1 uncoresnbep_unc_imc1uncore_imc_1Intel Sandy Bridge-EP IMC2 uncoresnbep_unc_imc2uncore_imc_2Intel Sandy Bridge-EP IMC3 uncoresnbep_unc_imc3uncore_imc_3CORES_C0Counts number of cores in C0CORES_C3Counts number of cores in C3CORES_C6Counts number of cores in C6C0C3C6UNC_P_CLOCKTICKSPCU Uncore clockticksUNC_P_CORE0_TRANSITION_CYCLESCore C State Transition CyclesUNC_P_CORE1_TRANSITION_CYCLESUNC_P_CORE2_TRANSITION_CYCLESUNC_P_CORE3_TRANSITION_CYCLESUNC_P_CORE4_TRANSITION_CYCLESUNC_P_CORE5_TRANSITION_CYCLESUNC_P_CORE6_TRANSITION_CYCLESUNC_P_CORE7_TRANSITION_CYCLESUNC_P_DEMOTIONS_CORE0Core C State DemotionsUNC_P_DEMOTIONS_CORE1UNC_P_DEMOTIONS_CORE2UNC_P_DEMOTIONS_CORE3UNC_P_DEMOTIONS_CORE4UNC_P_DEMOTIONS_CORE5UNC_P_DEMOTIONS_CORE6UNC_P_DEMOTIONS_CORE7UNC_P_FREQ_BAND0_CYCLESFrequency ResidencyUNC_P_FREQ_BAND1_CYCLESUNC_P_FREQ_BAND2_CYCLESUNC_P_FREQ_BAND3_CYCLESUNC_P_FREQ_MAX_CURRENT_CYCLESCurrent Strongest Upper Limit CyclesUNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLESThermal Strongest Upper Limit CyclesUNC_P_FREQ_MAX_OS_CYCLESOS Strongest Upper Limit CyclesUNC_P_FREQ_MAX_POWER_CYCLESPower Strongest Upper Limit CyclesUNC_P_FREQ_MIN_IO_P_CYCLESIO P Limit Strongest Lower Limit CyclesUNC_P_FREQ_MIN_PERF_P_CYCLESPerf P Limit Strongest Lower Limit CyclesUNC_P_FREQ_TRANS_CYCLESCycles spent changing FrequencyUNC_P_MEMORY_PHASE_SHEDDING_CYCLESMemory Phase Shedding CyclesUNC_P_POWER_STATE_OCCUPANCYNumber of cores in C0UNC_P_PROCHOT_EXTERNAL_CYCLESExternal ProchotUNC_P_PROCHOT_INTERNAL_CYCLESInternal ProchotUNC_P_TOTAL_TRANSITION_CYCLESTotal Core C State Transition CyclesUNC_P_VOLT_TRANS_CYCLES_CHANGECycles Changing VoltageUNC_P_VOLT_TRANS_CYCLES_DECREASECycles Decreasing VoltageUNC_P_VOLT_TRANS_CYCLES_INCREASECycles Increasing VoltageUNC_P_VR_HOT_CYCLESVR Hot[UNC_PCU=0x%lx event=0x%x occ_sel=0x%x en=%d inv=%d edge=%d thres=%d occ_inv=%d occ_edge=%d] %s [UNC_PCU_FILTER=0x%lx band0=%u band1=%u band2=%u band3=%u] Intel Sandy Bridge-EP PCU uncoresnbep_unc_pcuuncore_pcuFAILURE_CREDITSNumber of spawn failures due to lack of Egress creditsFAILURE_CREDITS_RBTNumber of spawn failures due to lack of Egress credit and route-back table (RBT) bit was not setFAILURE_RBTNumber of spawn failures because route-back table (RBT) specified that the transaction should not trigger a direct2core transactionSUCCESSNumber of spawn successesDRSNumber of times VN0 consumed for DRS message classHOMNumber of times VN0 consumed for HOM message classNCBNumber of times VN0 consumed for NCB message classNCSNumber of times VN0 consumed for NCS message classNDRNumber of times VN0 consumed for NDR message classSNPNumber of times VN0 consumed for SNP message classDATANumber of data flits over QPIIDLENumber of flits over QPI that do not hold protocol payloadNON_DATANumber of non-NULL non-data flits over QPINumber of flits over QPI on the Data Response (DRS) channelDRS_DATANumber of data flits over QPI on the Data Response (DRS) channelDRS_NONDATANumber of protocol flits over QPI on the Data Response (DRS) channelNumber of flits over QPI on the home channelHOM_NONREQNumber of non-request flits over QPI on the home channelHOM_REQNumber of data requests over QPI on the home channelNumber of snoop requests flits over QPINumber of non-coherent bypass flitsNCB_DATANumber of non-coherent data flitsNCB_NONDATANumber of bypass non-data flitsNumber of non-coherent standard (NCS) flitsNDR_ADNumber of flits received over Non-data response (NDR) channelNDR_AKNumber of flits received on the Non-data response (NDR) channel)UNC_Q_CLOCKTICKSNumber of qfclksUNC_Q_CTO_COUNTCount of CTO EventsUNC_Q_DIRECT2COREDirect 2 Core SpawningUNC_Q_L1_POWER_CYCLESCycles in L1UNC_Q_RXL0P_POWER_CYCLESCycles in L0pUNC_Q_RXL0_POWER_CYCLESCycles in L0UNC_Q_RXL_BYPASSEDRx Flit Buffer BypassedUNC_Q_RXL_CREDITS_CONSUMED_VN0VN0 Credit ConsumedUNC_Q_RXL_CREDITS_CONSUMED_VNAVNA Credit ConsumedUNC_Q_RXL_CYCLES_NERxQ Cycles Not EmptyUNC_Q_RXL_FLITS_G0Flits Received - Group 0UNC_Q_RXL_FLITS_G1Flits Received - Group 1UNC_Q_RXL_FLITS_G2Flits Received - Group 2UNC_Q_RXL_INSERTSRx Flit Buffer AllocationsUNC_Q_RXL_INSERTS_DRSRx Flit Buffer Allocations - DRSUNC_Q_RXL_INSERTS_HOMRx Flit Buffer Allocations - HOMUNC_Q_RXL_INSERTS_NCBRx Flit Buffer Allocations - NCBUNC_Q_RXL_INSERTS_NCSRx Flit Buffer Allocations - NCSUNC_Q_RXL_INSERTS_NDRRx Flit Buffer Allocations - NDRUNC_Q_RXL_INSERTS_SNPRx Flit Buffer Allocations - SNPUNC_Q_RXL_OCCUPANCYRxQ Occupancy - All PacketsUNC_Q_RXL_OCCUPANCY_DRSRxQ Occupancy - DRSUNC_Q_RXL_OCCUPANCY_HOMRxQ Occupancy - HOMUNC_Q_RXL_OCCUPANCY_NCBRxQ Occupancy - NCBUNC_Q_RXL_OCCUPANCY_NCSRxQ Occupancy - NCSUNC_Q_RXL_OCCUPANCY_NDRRxQ Occupancy - NDRUNC_Q_RXL_OCCUPANCY_SNPRxQ Occupancy - SNPUNC_Q_TXL0P_POWER_CYCLESUNC_Q_TXL0_POWER_CYCLESUNC_Q_TXL_BYPASSEDTx Flit Buffer BypassedUNC_Q_TXL_CYCLES_NETx Flit Buffer Cycles not EmptyUNC_Q_TXL_FLITS_G0Flits Transferred - Group 0UNC_Q_TXL_FLITS_G1Flits Transferred - Group 1UNC_Q_TXL_FLITS_G2Flits Transferred - Group 2UNC_Q_TXL_INSERTSTx Flit Buffer AllocationsUNC_Q_TXL_OCCUPANCYTx Flit Buffer OccupancyUNC_Q_VNA_CREDIT_RETURNSVNA Credits ReturnedUNC_Q_VNA_CREDIT_RETURN_OCCUPANCYVNA Credits Pending Return - Occupancy[UNC_QPI=0x%lx event=0x%x sel_ext=%d umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel Sandy Bridge-EP QPI0 uncoresnbep_unc_qpi0uncore_qpi_0Intel Sandy Bridge-EP QPI1 uncoresnbep_unc_qpi1uncore_qpi_1DOORBELL_RCVDTBDINT_PRIOIPI_RCVDMSI_RCVDVLW_RCVDUNC_U_EVENT_MSGVLW ReceivedUNC_U_LOCK_CYCLESIDI Lock/SplitLock CyclesIntel Sandy Bridge-EP U-Box uncoresnbep_unc_ubouncore_uboxCCW_EVENCounter-clockwise and even ring polarityCCW_ODDCounter-clockwise and odd ring polarityCW_EVENClockwise and even ring polarityCW_ODDClockwise and odd ring polarityCW_ANYClockwise with any polarityCCW_ANYCounter-clockwise with any polarityANYany direction and any polarityR2 IV Ring in UseDRSDRS Ingress queueNCBNCB Ingress queueNCSNCS Ingress queueADAD Egress queueAKAK Egress queueBLBL Egress queueUNC_R2_CLOCKTICKSNumber of uclks in domainUNC_R2_RING_AD_USEDR2 AD Ring in UseUNC_R2_RING_AK_USEDR2 AK Ring in UseUNC_R2_RING_BL_USEDR2 BL Ring in UseUNC_R2_RING_IV_USEDUNC_R2_RXR_AK_BOUNCESAK Ingress BouncedUNC_R2_RXR_CYCLES_NEIngress Cycles Not EmptyUNC_R2_TXR_CYCLES_FULLEgress Cycles FullUNC_R2_TXR_CYCLES_NEEgress Cycles Not EmptyUNC_R2_TXR_INSERTSEgress allocationsIntel Sandy Bridge-EP R2PCIe uncoresnbep_unc_r2pcieuncore_r2pcieDRSNCBNCSCCW_EVENCounter-Clockwise and even ring polarityCCW_ODDCounter-Clockwise and odd ring polarityCW_EVENClockwise and even ring polarityCW_ODDClockwise and odd ring polarityANYAny polarityADIngress BypassedDRS Ingress queueHOMHOM Ingress queueNCB Ingress queueNCS Ingress queueNDRNDR Ingress queueSNPSNP Ingress queueFilter DRS message classFilter HOM message classFilter NCB message classFilter NCS message classFilter NDR message classFilter SNP message classUNC_R3_CLOCKTICKSNumber of uclks in domainUNC_R3_IIO_CREDITS_ACQUIREDto IIO BL Credit AcquiredUNC_R3_IIO_CREDITS_REJECTto IIO BL Credit RejectedUNC_R3_IIO_CREDITS_USEDto IIO BL Credit In UseUNC_R3_RING_AD_USEDR3 AD Ring in UseUNC_R3_RING_AK_USEDR3 AK Ring in UseUNC_R3_RING_BL_USEDR3 BL Ring in UseUNC_R3_RING_IV_USEDR3 IV Ring in UseUNC_R3_RXR_BYPASSEDUNC_R3_RXR_CYCLES_NEIngress Cycles Not EmptyUNC_R3_RXR_INSERTSIngress AllocationsUNC_R3_RXR_OCCUPANCYIngress Occupancy AccumulatorUNC_R3_TXR_CYCLES_FULLEgress cycles fullUNC_R3_TXR_INSERTSEgress allocationsUNC_R3_TXR_NACKEgress NackUNC_R3_VN0_CREDITS_REJECTVN0 Credit Acquisition Failed on DRSUNC_R3_VN0_CREDITS_USEDVN0 Credit UsedUNC_R3_VNA_CREDITS_ACQUIREDVNA credit AcquisitionsUNC_R3_VNA_CREDITS_REJECTVNA Credit RejectUNC_R3_VNA_CREDIT_CYCLES_OUTCycles with no VNA credits availableUNC_R3_VNA_CREDIT_CYCLES_USEDCycles with 1 or more VNA credits in useIntel Sandy Bridge-EP R3QPI0 uncoresnbep_unc_r3qpi0uncore_r3qpi_0Intel Sandy Bridge-EP R3QPI1 uncoresnbep_unc_r3qpi1uncore_r3qpi_1DATA_READData read requestsWRITEWrite requests. Includes all write transactions (cached, uncached)REMOTE_SNOOPExternal snoop requestANYAny requestNIDMatch a given RTID destination NID (must provide nf=X modifier)STATE_IInvalid cacheline stateSTATE_SShared cacheline stateSTATE_EExclusive cacheline stateSTATE_MModified cacheline stateSTATE_FForward cacheline stateSTATE_MESIFAny cache line stateLines in M stateLines in E stateLines in S stateMISSTBDVictimized Lines matching the NID filter (must provide nf=X modifier)UP_VR0_EVENUp and Even ring polarity filter on virtual ring 0UP_VR0_ODDUp and odd ring polarity filter on virtual ring 0DOWN_VR0_EVENDown and even ring polarity filter on virtual ring 0DOWN_VR0_ODDDown and odd ring polarity filter on virtual ring 0UP_VR1_EVENUp and Even ring polarity filter on virtual ring 1UP_VR1_ODDUp and odd ring polarity filter on virtual ring 1DOWN_VR1_EVENDown and even ring polarity filter on virtual ring 1DOWN_VR1_ODDDown and odd ring polarity filter on virtual ring 1UPUp on any virtual ringDOWNDown any virtual ringAD_IRQAKAcknowledgments to coreBLData responses to coreIVSnoops of processor cacheAny filterFilter on any up polarityFilter on any down polarityIRQIrq externally starved, therefore blocking the IPQIPQIPQ externally starved, therefore blocking the IRQPRQIRQ is blocking the ingress queue and causing starvationISMQ_BIDSNumber of time the ISMQ bidsIRQ_REJECTEDIRQ rejectedVFIFOCounts the number of allocated into the IRQ ordering FIFOADDR_CONFLICTAddress conflictAny RejectFULLNo Egress creditsQPI_CREDITSNo QPI creditsAny rejectRTIDNo RTIDsIIO_CREDITSNo IIO CreditsNo IIO creditsNO QPI creditsWB_CREDITSNo WB creditsOPCODENumber of transactions inserted into the TOR that match an opcode (must provide opc_* umask)MISS_OPCODENumber of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)EVICTIONNumber of Evictions transactions inserted into TORALLNumber of transactions inserted in TORWBNumber of write transactions inserted into the TORLOCAL_OPCODENumber of opcode-matched transactions inserted into the TOR that are satisfied by locally homed memoryMISS_LOCAL_OPCODENumber of miss opcode-matched transactions inserted into the TOR that are satisfied by locally homed memoryLOCALNumber of transactions inserted into the TOR that are satisfied by locally homed memoryMISS_LOCALNumber of miss transactions inserted into the TOR that are satisfied by locally homed memoryNID_OPCODENumber of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)NID_MISS_OPCODENumber of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)NID_EVICTIONNumber of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)NID_ALLNumber of NID-matched transactions inserted into the TOR (must provide nf=X modifier)NID_MISS_ALLNumber of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)NID_WBNumber of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)REMOTE_OPCODENumber of opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memoryMISS_REMOTE_OPCODENumber of miss opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memoryREMOTENumber of transactions inserted into the TOR that are satisfied by remote caches or memoryMISS_REMOTENumber of miss transactions inserted into the TOR that are satisfied by remote caches or memoryOPC_RFODemand data RFO (combine with any OPCODE umask)OPC_CRDDemand code read (combine with any OPCODE umask)OPC_DRDDemand data read (combine with any OPCODE umask)OPC_PRDPartial reads (UC) (combine with any OPCODE umask)OPC_WCILFFull Stream store (combine with any OPCODE umask)OPC_WCILPartial Stream store (combine with any OPCODE umask)OPC_PF_RFOPrefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PF_CODEPrefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PF_DATAPrefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PCIWILFPCIe write (non-allocating) (combine with any OPCODE umask)OPC_PCIPRDPCIe UC read (combine with any OPCODE umask)OPC_PCIITOMPCIe write (allocating) (combine with any OPCODE umask)OPC_PCIRDCURPCIe read current (combine with any OPCODE umask)OPC_WBMTOIRequest writeback modified invalidate line (combine with any OPCODE umask)OPC_WBMTOERequest writeback modified set to exclusive (combine with any OPCODE umask)OPC_ITOMRequest invalidate line (combine with any OPCODE umask)OPC_PCINSRDPCIe non-snoop read (combine with any OPCODE umask)OPC_PCINSWRPCIe non-snoop write (partial) (combine with any OPCODE umask)OPC_PCINSWRFPCIe non-snoop write (full) (combine with any OPCODE umask)Number of TOR entries that match an opcode (must provide opc_* umask)Number of TOR entries that match a NID and an opcode (must provide opc_* umask)Number of outstanding eviction transactions in the TORAll valid TOR entriesMISS_ALLNumber of outstanding miss requests in the TORNumber of write transactions in the TOR. Does not include RFO, but actual operations that contain data being sent from the coreNumber of opcode-matched transactions in the TOR that are satisfied by locally homed memoryNumber of miss opcode-matched transactions in the TOR that are satisfied by locally homed memoryNumber of transactions in the TOR that are satisfied by locally homed memoryNumber of miss transactions in the TOR that are satisfied by locally homed memoryNumber of NID-matched TOR entries that an opcode (must provide nf=X modifier and opc_* umask)Number of NID-matched outstanding miss requests in the TOR that an opcode (must provide nf=X modifier and opc_* umask)Number of NID-matched outstanding requests in the TOR (must provide a nf=X modifier)Number of NID-matched outstanding requests in the TOR (must provide nf=X modifier)Number of NID-matched outstanding miss requests in the TOR (must provide a nf=X modifier)Number of NID-matched write transactions in the TOR (must provide a nf=X modifier)Number of opcode-matched transactions in the TOR that are satisfied by remote caches or memoryNumber of miss opcode-matched transactions in the TOR that are satisfied by remote caches or memoryNumber of transactions in the TOR that are satisfied by remote caches or memoryAD_CACHECounts the number of ring transactions from Cachebo to AD ringAK_CACHECounts the number of ring transactions from Cachebo to AK ringBL_CACHECounts the number of ring transactions from Cachebo to BL ringIV_CACHECounts the number of ring transactions from Cachebo ton IV ringAD_CORECounts the number of ring transactions from Corebo to AD ringAK_CORECounts the number of ring transactions from Corebo to AK ringBL_CORECounts the number of ring transactions from Corebo to BL ringADonto AD ringOnto AK ringOnto BL ringRSPI_WAS_FSECounts the number of times when a SNoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodingsWC_ALIASINGCounts the number of times a USWC write (WCIL(F)) transaction hits in the LLC in M state, triggering a WBMTOI followed by the USWC write. This occurs when there is WC aliasingSTARTEDRFO_HIT_SCounts the number of times that an RFO hits in S state. This is useful for determining if it might be good for a workload to use RSPIWB instead of RSPSWBUNC_C_CLOCKTICKSC-box Uncore clockticksUNC_C_COUNTER0_OCCUPANCYCounter 0 occupancy. Counts the occupancy related information by filtering CB0 occupancy count captured in counter 0.UNC_C_LLC_LOOKUPCache lookupsUNC_C_LLC_VICTIMSLines victimizedUNC_C_MISCMiscellaneous C-Box eventsUNC_C_RING_AD_USEDAddress ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_AK_USEDAcknowledgement ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_BL_USEDBus or Data ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_BOUNCESNumber of LLC responses that bounced in the ringUNC_C_RING_IV_USEDInvalidate ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_SRC_THRTLTDBUNC_C_RXR_EXT_STARVEDIngress arbiter blocking cyclesUNC_C_RXR_INSERTSIngress AllocationsUNC_C_RXR_IPQ_RETRYProbe Queue RetriesUNC_C_RXR_IRQ_RETRYIngress Request Queue RejectsUNC_C_RXR_ISMQ_RETRYISMQ RetriesUNC_C_RXR_OCCUPANCYIngress OccupancyUNC_C_TOR_INSERTSTOR InsertsUNC_C_TOR_OCCUPANCYTOR OccupancyUNC_C_TXR_ADS_USEDEgress eventsUNC_C_TXR_INSERTSEgress allocations[UNC_CBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d tid_en=%d] %s [UNC_CBOX_FILTER0=0x%lx tid=%d core=0x%x state=0x%x] [UNC_CBOX_FILTER1=0x%lx nid=%d opc=0x%x nc=0x%x isoc=0x%x] Intel Ivy Bridge-EP C-Box 0 uncoreivbep_unc_cbo0uncore_cbox_0Intel Ivy Bridge-EP C-Box 1 uncoreivbep_unc_cbo1uncore_cbox_1Intel Ivy Bridge-EP C-Box 2 uncoreivbep_unc_cbo2uncore_cbox_2Intel Ivy Bridge-EP C-Box 3 uncoreivbep_unc_cbo3uncore_cbox_3Intel Ivy Bridge-EP C-Box 4 uncoreivbep_unc_cbo4uncore_cbox_4Intel Ivy Bridge-EP C-Box 5 uncoreivbep_unc_cbo5uncore_cbox_5Intel Ivy Bridge-EP C-Box 6 uncoreivbep_unc_cbo6uncore_cbox_6Intel Ivy Bridge-EP C-Box 7 uncoreivbep_unc_cbo7uncore_cbox_7Intel Ivy Bridge-EP C-Box 8 uncoreivbep_unc_cbo8uncore_cbox_8Intel Ivy Bridge-EP C-Box 9 uncoreivbep_unc_cbo9uncore_cbox_9Intel Ivy Bridge-EP C-Box 10 uncoreivbep_unc_cbo10uncore_cbox_10Intel Ivy Bridge-EP C-Box 11 uncoreivbep_unc_cbo11uncore_cbox_11Intel Ivy Bridge-EP C-Box 12 uncoreivbep_unc_cbo12uncore_cbox_12Intel Ivy Bridge-EP C-Box 13 uncoreivbep_unc_cbo13uncore_cbox_13Intel Ivy Bridge-EP C-Box 14 uncoreivbep_unc_cbo14uncore_cbox_14CONFLICTNumber of cycles that we are handling conflictsLASTCount every last conflictor in conflict chain. Can be used to compute average conflict chain lengthCMP_FWDSCount the number of cmp_fwd. This gives the number of late conflictsACKCNFLTSCount the number AcknfltsNO_SNPSnoop not neededSNOOPSNooop neededTAKENBypass takenNOT_TAKENBypass not takenANYCounts any directory updateCLEARDirectory clearsSETDirectory setAD_QPI0AD to QPI link 0AD_QPI1AD to QPI link 1BL_QPI0BL to QPI link 0BL_QPI1BL to QPI link 1ALLCounts all writesFULLCounts full line non ISOCHFULL_ISOCHCounts ISOCH full linePARTIALCounts partial non-ISOCHPARTIAL_ISOCHCounts ISOCH partialNORMALNormal priorityREADSCounts incoming read requests. Good proxy for LLC read misses, incl. RFOsREADS_LOCALCounts incoming read requests coming from local socket. Good proxy for LLC read misses, incl. RFOs from the local socketREADS_REMOTECounts incoming read requests coming from remote socket. Good proxy for LLC read misses, incl. RFOs from the remote socketWRITESCounts incoming writesWRITES_LOCALCounts incoming writes from local socketWRITES_REMOTECounts incoming writes from remote socketINVITOE_LOCALCounts InvItoE coming from local socketINVITOE_REMOTECounts InvItoE coming from remote socketCHN0Channel 0CHN1Channel 1CHN2channel 2CHN3Chanell 3REGION0Counts for TAD Region 0REGION1Counts for TAD Region 1REGION2Counts for TAD Region 2REGION3Counts for TAD Region 3REGION4Counts for TAD Region 4REGION5Counts for TAD Region 5REGION6Counts for TAD Region 6REGION7Counts for TAD Region 7REGION8Counts for TAD Region 8REGION9Counts for TAD Region 9REGION10Counts for TAD Region 10REGION11Counts for TAD Region 11RSPIFilters for snoop responses of RspI. RspI is returned when the remote cache does not have the data or when the remote cache silently evicts data (e.g. RFO hit non-modified line)RSPSFilters for snoop responses of RspS. RspS is returned when the remote cache has the data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E-stateRSPIFWDFilters for snoop responses of RspIFwd. RspIFwd is returned when the remote cache agent forwards data and the requesting agent is able to acquire the data in E or M state. This is commonly returned with RFO transacations. It can be either HitM or HitFERSPSFWDFilters for snoop responses of RspSFwd. RspSFwd is returned when the remote cache agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F stateRSP_WBFilters for snoop responses of RspIWB or RspSWB. This is returned when a non-RFO requests hits in M-state. Data and code reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownershipRSP_FWD_WBFilters for snoop responses of RspxFwdxWB. This snoop response is only used in 4s systems. It is used when a snoop HITM in a remote caching agent and it directly forwards data to a requester and simultaneously returns data to the home to be written back to memoryRSPCNFLCTFilters for snoop responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CMAs that caching agent. This triggers the conflict resolution hardware. This covers both RspConflct and RspCnflctWBICounts cycles full from both schedulersSCHED0Counts cycles full from scheduler bank 0SCHED1Counts cycles full from scheduler bank 1Counts cycles from both schedulersCounts cycles from scheduler bank 0Counts cycles from scheduler bank 1DRS_CACHECounts data being sent to the cacheDRS_CORECounts data being sent directly to the requesting coreDRS_QPICounts data being sent to a remote socket over QPILOCALLocalREMOTERemoteReads remoteWrites localWrites remoteLocal readsLocal InvItoEAll data returnsREADS_LOCAL_IReads to local IREADS_REMOTE_IReads to remote IREADS_LOCAL_SReads to local SREADS_REMOTE_SReads to remote SCCW_VR0_EVENCounter-clockwise and even ring polarity on virtual ring 0CCW_VR0_ODDCounter-clockwise and odd ring polarity on virtual ring 0CW_VR0_EVENClockwise and even ring polarity on virtual ring 0CW_VR0_ODDClockwise and odd ring polarity on virtual ring 0CCW_VR1_EVENCounter-clockwise and even ring polarity on virtual ring 1CCW_VR1_ODDCounter-clockwise and odd ring polarity on virtual ring 1CW_VR1_EVENClockwise and even ring polarity on virtual ring 1CW_VR1_ODDClockwise and odd ring polarity on virtual ring 1CWClockwise with any polarity on either virtual ringsCCWCounter-clockwise with any polarity on either virtual ringsOTHERFilters all other snoop responsesNDRNumber of outbound NDR (non-data response) transactions send on the AK ring. AK NDR is used for messages to the local socketCRD_CBONumber of outbound CDR transactions send on the AK ring to CBOCRD_QPINumber of outbound CDR transactions send on the AK ring to QPIAny conflictLast conflictUNC_H_CLOCKTICKSHA Uncore clockticksUNC_H_CONFLICT_CYCLESConflict ChecksUNC_H_DIRECT2CORE_COUNTDirect2Core Messages SentUNC_H_DIRECT2CORE_CYCLES_DISABLEDCycles when Direct2Core was DisabledUNC_H_DIRECT2CORE_TXN_OVERRIDENumber of Reads that had Direct2Core OverriddenUNC_H_DIRECTORY_LOOKUPDirectory LookupsUNC_H_DIRECTORY_UPDATEDirectory UpdatesUNC_H_IGR_NO_CREDIT_CYCLESCycles without QPI Ingress CreditsUNC_H_IMC_RETRYRetry EventsUNC_H_IMC_WRITESHA to IMC Full Line Writes IssuedUNC_H_IMC_READSHA to IMC normal priority reads issuedUNC_H_REQUESTSRead and Write RequestsUNC_H_RPQ_CYCLES_NO_REG_CREDITSIMC RPQ Credits EmptyUNC_H_TAD_REQUESTS_G0HA Requests to a TAD RegionUNC_H_TAD_REQUESTS_G1UNC_H_TXR_AD_CYCLES_FULLAD Egress FullUNC_H_TXR_AK_CYCLES_FULLAK Egress FullUNC_H_TXR_AKOutbound Ring Transactions on AKUNC_H_TXR_BLOutbound DRS Ring Transactions to CacheUNC_H_TXR_BL_CYCLES_FULLBL Egress FullUNC_H_WPQ_CYCLES_NO_REG_CREDITSHA IMC CHN0 WPQ Credits EmptyUNC_H_BT_BYPASSBackup Tracker bypassUNC_H_BYPASS_IMCHA to IMC bypassUNC_H_BT_CYCLES_NEBackup Tracker cycles not emptyUNC_H_BT_OCCUPANCYBackup Tracker insertsUNC_H_IGR_AD_QPI2AD QPI Link 2 credit accumulatorUNC_H_IGR_BL_QPI2BL QPI Link 2 credit accumulatorUNC_H_IODC_INSERTSIODC insertsUNC_H_IODC_CONFLICTSIODC conflictsUNC_H_IODC_OLEN_WBMTOIIODC zero length writesUNC_H_OSBOSB snoop broadcastUNC_H_OSB_EDROSB early data returnUNC_H_RING_AD_USEDAD ring in useUNC_H_RING_AK_USEDAK ring in useUNC_H_RING_BL_USEDBL ring in useUNC_H_DIRECTORY_LAT_OPTDirectory latency optimization data return path takenUNC_H_SNP_RESP_RECV_LOCALSnoop responses received localUNC_H_TXR_BL_OCCUPANCYBL Egress occupancyUNC_H_SNOOP_RESPSnoop responses received[UNC_HA=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s [UNC_HA_ADDR=0x%lx lo_addr=0x%x hi_addr=0x%x] [UNC_HA_OPC=0x%lx opc=0x%x] Intel Ivy Bridge-EP HA 0 uncoreivbep_unc_ha0uncore_ha_0Intel Ivy Bridge-EP HA 1 uncoreivbep_unc_ha1uncore_ha_1ALLCounts total number of DRAM CAS commands issued on this channelRDCounts all DRAM reads on this channel, incl. underfillsRD_REGCounts number of DRAM read CAS commands issued on this channel, incl. regular read CAS and those with implicit prechargeRD_UNDERFILLCounts number of underfill reads issued by the memory controllerWRCounts number of DRAM write CAS commands on this channelWR_RMMCounts Number of opportunistic DRAM write CAS commands issued on this channelWR_WMMCounts number of DRAM write CAS commands issued on this channel while in Write-Major modeRD_RMMCounts Number of opportunistic DRAM read CAS commands issued on this channelRD_WMMCounts number of DRAM read CAS commands issued on this channel while in Write-Major modeHIGHTBDPANICISOCHCounts cycles in ISOCH Major modePARTIALCounts cycles in Partial Major modeREADCounts cycles in Read Major modeWRITECounts cycles in Write Major modeRANK0Count cycles for rank 0RANK1Count cycles for rank 1RANK2Count cycles for rank 2RANK3Count cycles for rank 3RANK4Count cycles for rank 4RANK5Count cycles for rank 5RANK6Count cycles for rank 6RANK7Count cycles for rank 7RD_PREEMPT_RDCounts read over read preemptionsRD_PREEMPT_WRCounts read over write preemptionsPAGE_CLOSECounts number of DRAM precharge commands sent on this channel as a result of the page close counter expiringPAGE_MISSCounts number of DRAM precharge commands sent on this channel as a result of page missesPrecharge due to readPrecharge due to writeBYPPrecharge due to bypassActivate due to readActivate due to writeActivate due to bypassACTACT command issued by 2 cycle bypassCASCAS command issued by 2 cycle bypassPREPRE command issued by 2 cycle bypassLOWRead CAS issued with low priorityMEDRead CAS issued with medium priorityRead CAS issued with high priorityRead CAS issued with panic non isoch priority (starved)BANK0Bank 0BANK1Bank 1BANK2Bank 2BANK3Bank 3BANK4Bank 4BANK5Bank 5BANK6Bank 6BANK7Bank 7WMMVMSE write push issued in WMMRMMVMSE write push issued in RMMLOW_THRESTransition from WMM to RMM because of starve counterSTARVEVMSE_RETRYUNC_M_CLOCKTICKSIMC Uncore clockticks (fixed counter)UNC_M_DCLOCKTICKSIMC Uncore clockticks (generic counters)UNC_M_ACT_COUNTDRAM Activate CountUNC_M_CAS_COUNTDRAM RD_CAS and WR_CAS Commands.UNC_M_DRAM_PRE_ALLDRAM Precharge All CommandsUNC_M_DRAM_REFRESHNumber of DRAM Refreshes IssuedUNC_M_ECC_CORRECTABLE_ERRORSECC Correctable ErrorsUNC_M_MAJOR_MODESCycles in a Major ModeUNC_M_POWER_CHANNEL_DLLOFFChannel DLLOFF CyclesUNC_M_POWER_CHANNEL_PPDChannel PPD CyclesUNC_M_POWER_CKE_CYCLESCKE_ON_CYCLES by RankUNC_M_POWER_CRITICAL_THROTTLE_CYCLESCritical Throttle CyclesUNC_M_POWER_SELF_REFRESHClock-Enabled Self-RefreshUNC_M_POWER_THROTTLE_CYCLESThrottle CyclesUNC_M_PREEMPTIONRead Preemption CountUNC_M_PRE_COUNTDRAM Precharge commands.UNC_M_RPQ_CYCLES_NERead Pending Queue Not EmptyUNC_M_RPQ_INSERTSRead Pending Queue AllocationsUNC_M_WPQ_CYCLES_FULLWrite Pending Queue Full CyclesUNC_M_WPQ_CYCLES_NEWrite Pending Queue Not EmptyUNC_M_WPQ_INSERTSWrite Pending Queue AllocationsUNC_M_WPQ_READ_HITWrite Pending Queue CAM MatchUNC_M_WPQ_WRITE_HITUNC_M_BYP_CMDSBypass command eventUNC_M_RD_CAS_PRIORead CAS priorityUNC_M_RD_CAS_RANK0Read CAS access to Rank 0UNC_M_RD_CAS_RANK1Read CAS access to Rank 1UNC_M_RD_CAS_RANK2Read CAS access to Rank 2UNC_M_RD_CAS_RANK3Read CAS access to Rank 3UNC_M_RD_CAS_RANK4Read CAS access to Rank 4UNC_M_RD_CAS_RANK5Read CAS access to Rank 5UNC_M_RD_CAS_RANK6Read CAS access to Rank 6UNC_M_RD_CAS_RANK7Read CAS access to Rank 7UNC_M_VMSE_MXB_WR_OCCUPANCYVMSE MXB write buffer occupancyUNC_M_VMSE_WR_PUSHVMSE WR push issuedUNC_M_WMM_TO_RMMTransitions from WMM to RMM because of low thresholdUNC_M_WRONG_MMNot getting the requested major modeUNC_M_WR_CAS_RANK0Write CAS access to Rank 0UNC_M_WR_CAS_RANK1Write CAS access to Rank 1UNC_M_WR_CAS_RANK2Write CAS access to Rank 2UNC_M_WR_CAS_RANK3Write CAS access to Rank 3UNC_M_WR_CAS_RANK4Write CAS access to Rank 4UNC_M_WR_CAS_RANK5Write CAS access to Rank 5UNC_M_WR_CAS_RANK6Write CAS access to Rank 6UNC_M_WR_CAS_RANK7Write CAS access to Rank 7Intel Iyy Bridge-EP IMC0 uncoreivbep_unc_imc0uncore_imc_0Intel Iyy Bridge-EP IMC1 uncoreivbep_unc_imc1uncore_imc_1Intel Iyy Bridge-EP IMC2 uncoreivbep_unc_imc2uncore_imc_2Intel Iyy Bridge-EP IMC3 uncoreivbep_unc_imc3uncore_imc_3Intel Iyy Bridge-EP IMC4 uncoreivbep_unc_imc4uncore_imc_4Intel Iyy Bridge-EP IMC5 uncoreivbep_unc_imc5uncore_imc_5Intel Iyy Bridge-EP IMC6 uncoreivbep_unc_imc6uncore_imc_6Intel Iyy Bridge-EP IMC7 uncoreivbep_unc_imc7uncore_imc_7CORES_C0Counts number of cores in C0CORES_C3Counts number of cores in C3CORES_C6Counts number of cores in C6UNC_P_CLOCKTICKSPCU Uncore clockticksUNC_P_CORE0_TRANSITION_CYCLESCore 0 C State Transition CyclesUNC_P_CORE1_TRANSITION_CYCLESCore 1 C State Transition CyclesUNC_P_CORE2_TRANSITION_CYCLESCore 2 C State Transition CyclesUNC_P_CORE3_TRANSITION_CYCLESCore 3 C State Transition CyclesUNC_P_CORE4_TRANSITION_CYCLESCore 4 C State Transition CyclesUNC_P_CORE5_TRANSITION_CYCLESCore 5 C State Transition CyclesUNC_P_CORE6_TRANSITION_CYCLESCore 6 C State Transition CyclesUNC_P_CORE7_TRANSITION_CYCLESCore 7 C State Transition CyclesUNC_P_CORE8_TRANSITION_CYCLESCore 8 C State Transition CyclesUNC_P_CORE9_TRANSITION_CYCLESCore 9 C State Transition CyclesUNC_P_CORE10_TRANSITION_CYCLESCore 10 C State Transition CyclesUNC_P_CORE11_TRANSITION_CYCLESCore 11 C State Transition CyclesUNC_P_CORE12_TRANSITION_CYCLESCore 12 C State Transition CyclesUNC_P_CORE13_TRANSITION_CYCLESCore 13 C State Transition CyclesUNC_P_CORE14_TRANSITION_CYCLESCore 14 C State Transition CyclesUNC_P_DELAYED_C_STATE_ABORT_CORE0Deep C state rejection Core 0UNC_P_DELAYED_C_STATE_ABORT_CORE1Deep C state rejection Core 1UNC_P_DELAYED_C_STATE_ABORT_CORE2Deep C state rejection Core 2UNC_P_DELAYED_C_STATE_ABORT_CORE3Deep C state rejection Core 3UNC_P_DELAYED_C_STATE_ABORT_CORE4Deep C state rejection Core 4UNC_P_DELAYED_C_STATE_ABORT_CORE5Deep C state rejection Core 5UNC_P_DELAYED_C_STATE_ABORT_CORE6Deep C state rejection Core 6UNC_P_DELAYED_C_STATE_ABORT_CORE7Deep C state rejection Core 7UNC_P_DELAYED_C_STATE_ABORT_CORE8Deep C state rejection Core 8UNC_P_DELAYED_C_STATE_ABORT_CORE9Deep C state rejection Core 9UNC_P_DELAYED_C_STATE_ABORT_CORE10Deep C state rejection Core 10UNC_P_DELAYED_C_STATE_ABORT_CORE11Deep C state rejection Core 11UNC_P_DELAYED_C_STATE_ABORT_CORE12Deep C state rejection Core 12UNC_P_DELAYED_C_STATE_ABORT_CORE13Deep C state rejection Core 13UNC_P_DELAYED_C_STATE_ABORT_CORE14Deep C state rejection Core 14UNC_P_DEMOTIONS_CORE0Core 0 C State DemotionsUNC_P_DEMOTIONS_CORE1Core 1 C State DemotionsUNC_P_DEMOTIONS_CORE2Core 2 C State DemotionsUNC_P_DEMOTIONS_CORE3Core 3 C State DemotionsUNC_P_DEMOTIONS_CORE4Core 4 C State DemotionsUNC_P_DEMOTIONS_CORE5Core 5 C State DemotionsUNC_P_DEMOTIONS_CORE6Core 6 C State DemotionsUNC_P_DEMOTIONS_CORE7Core 7 C State DemotionsUNC_P_DEMOTIONS_CORE8Core 8 C State DemotionsUNC_P_DEMOTIONS_CORE9Core 9 C State DemotionsUNC_P_DEMOTIONS_CORE10Core 10 C State DemotionsUNC_P_DEMOTIONS_CORE11Core 11 C State DemotionsUNC_P_DEMOTIONS_CORE12Core 12 C State DemotionsUNC_P_DEMOTIONS_CORE13Core 13 C State DemotionsUNC_P_DEMOTIONS_CORE14Core 14 C State DemotionsUNC_P_FREQ_BAND0_CYCLESFrequency ResidencyUNC_P_FREQ_BAND1_CYCLESUNC_P_FREQ_BAND2_CYCLESUNC_P_FREQ_BAND3_CYCLESUNC_P_FREQ_MAX_CURRENT_CYCLESCurrent Strongest Upper Limit CyclesUNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLESThermal Strongest Upper Limit CyclesUNC_P_FREQ_MAX_OS_CYCLESOS Strongest Upper Limit CyclesUNC_P_FREQ_MAX_POWER_CYCLESPower Strongest Upper Limit CyclesUNC_P_FREQ_MIN_PERF_P_CYCLESPerf P Limit Strongest Lower Limit CyclesUNC_P_FREQ_MIN_IO_P_CYCLESIO P Limit Strongest Lower Limit CyclesUNC_P_FREQ_TRANS_CYCLESCycles spent changing FrequencyUNC_P_MEMORY_PHASE_SHEDDING_CYCLESMemory Phase Shedding CyclesUNC_P_PKG_C_EXIT_LATENCYPackage C state exit latency. Counts cycles the package is transitioning from C2 to C3UNC_P_POWER_STATE_OCCUPANCYNumber of cores in C0UNC_P_PROCHOT_EXTERNAL_CYCLESExternal ProchotUNC_P_PROCHOT_INTERNAL_CYCLESInternal ProchotUNC_P_TOTAL_TRANSITION_CYCLESTotal Core C State Transition CyclesUNC_P_VOLT_TRANS_CYCLES_CHANGECycles Changing VoltageUNC_P_VOLT_TRANS_CYCLES_DECREASECycles Decreasing VoltageUNC_P_VOLT_TRANS_CYCLES_INCREASECycles Increasing VoltageUNC_P_VR_HOT_CYCLESVR Hot[UNC_PCU=0x%lx event=0x%x sel_ext=%d occ_sel=0x%x en=%d edge=%d thres=%d occ_inv=%d occ_edge=%d] %s [UNC_PCU_FILTER=0x%lx band0=%u band1=%u band2=%u band3=%u] Intel Ivy Bridge-EP PCU uncoreivbep_unc_pcuuncore_pcuFAILURE_CREDITSNumber of spawn failures due to lack of Egress creditsFAILURE_CREDITS_RBTNumber of spawn failures due to lack of Egress credit and route-back table (RBT) bit was not setFAILURE_RBT_HITNumber of spawn failures because route-back table (RBT) specified that the transaction should not trigger a direct2core transactionSUCCESS_RBT_HITNumber of spawn successesFAILURE_MISSNumber of spawn failures due to RBT tag not matching although the valid bit was set and there was enough Egress creditsFAILURE_CREDITS_MISSNumber of spawn failures due to RBT tag not matching and they were not enough Egress credits. The valid bit was setFAILURE_RBT_MISSNumber of spawn failures due to RBT tag not matching, the valid bit was not set but there were enough Egress creditsFAILURE_CREDITS_RBT_MISSNumber of spawn failures due to RBT tag not matching, the valid bit was not set and there were not enough Egress creditsDRSNumber of times VN0 consumed for DRS message classHOMNumber of times VN0 consumed for HOM message classNCBNumber of times VN0 consumed for NCB message classNCSNumber of times VN0 consumed for NCS message classNDRNumber of times VN0 consumed for NDR message classSNPNumber of times VN0 consumed for SNP message classNumber of times VN1 consumed for DRS message classNumber of times VN1 consumed for HOM message classNumber of times VN1 consumed for NCB message classNumber of times VN1 consumed for NCS message classNumber of times VN1 consumed for NDR message classNumber of times VN1 consumed for SNP message classDATANumber of data flits over QPIIDLENumber of flits over QPI that do not hold protocol payloadNON_DATANumber of non-NULL non-data flits over QPINumber of flits over QPI on the Data Response (DRS) channelDRS_DATANumber of data flits over QPI on the Data Response (DRS) channelDRS_NONDATANumber of protocol flits over QPI on the Data Response (DRS) channelNumber of flits over QPI on the home channelHOM_NONREQNumber of non-request flits over QPI on the home channelHOM_REQNumber of data requests over QPI on the home channelNumber of snoop requests flits over QPINumber of non-coherent bypass flitsNCB_DATANumber of non-coherent data flitsNCB_NONDATANumber of bypass non-data flitsNumber of non-coherent standard (NCS) flitsNDR_ADNumber of flits received over Non-data response (NDR) channelNDR_AKNumber of flits received on the Non-data response (NDR) channel)VN0for VN0VN1for VN1VN_SHRfor shared VNUNC_Q_CLOCKTICKSNumber of qfclksUNC_Q_CTO_COUNTCount of CTO EventsUNC_Q_DIRECT2COREDirect 2 Core SpawningUNC_Q_L1_POWER_CYCLESCycles in L1UNC_Q_RXL0P_POWER_CYCLESCycles in L0pUNC_Q_RXL0_POWER_CYCLESCycles in L0UNC_Q_RXL_BYPASSEDRx Flit Buffer BypassedUNC_Q_RXL_CREDITS_CONSUMED_VN0VN0 Credit ConsumedUNC_Q_RXL_CREDITS_CONSUMED_VN1VN1 Credit ConsumedUNC_Q_RXL_CREDITS_CONSUMED_VNAVNA Credit ConsumedUNC_Q_RXL_CYCLES_NERxQ Cycles Not EmptyUNC_Q_RXL_FLITS_G0Flits Received - Group 0UNC_Q_RXL_FLITS_G1Flits Received - Group 1UNC_Q_RXL_FLITS_G2Flits Received - Group 2UNC_Q_RXL_INSERTSRx Flit Buffer AllocationsUNC_Q_RXL_INSERTS_DRSRx Flit Buffer Allocations - DRSUNC_Q_RXL_INSERTS_HOMRx Flit Buffer Allocations - HOMUNC_Q_RXL_INSERTS_NCBRx Flit Buffer Allocations - NCBUNC_Q_RXL_INSERTS_NCSRx Flit Buffer Allocations - NCSUNC_Q_RXL_INSERTS_NDRRx Flit Buffer Allocations - NDRUNC_Q_RXL_INSERTS_SNPRx Flit Buffer Allocations - SNPUNC_Q_RXL_OCCUPANCYRxQ Occupancy - All PacketsUNC_Q_RXL_OCCUPANCY_DRSRxQ Occupancy - DRSUNC_Q_RXL_OCCUPANCY_HOMRxQ Occupancy - HOMUNC_Q_RXL_OCCUPANCY_NCBRxQ Occupancy - NCBUNC_Q_RXL_OCCUPANCY_NCSRxQ Occupancy - NCSUNC_Q_RXL_OCCUPANCY_NDRRxQ Occupancy - NDRUNC_Q_RXL_OCCUPANCY_SNPRxQ Occupancy - SNPUNC_Q_TXL0P_POWER_CYCLESUNC_Q_TXL0_POWER_CYCLESUNC_Q_TXL_BYPASSEDTx Flit Buffer BypassedUNC_Q_TXL_CYCLES_NETx Flit Buffer Cycles not EmptyUNC_Q_TXL_FLITS_G0Flits Transferred - Group 0UNC_Q_TXL_FLITS_G1Flits Transferred - Group 1UNC_Q_TXL_FLITS_G2Flits Transferred - Group 2UNC_Q_TXL_INSERTSTx Flit Buffer AllocationsUNC_Q_TXL_OCCUPANCYTx Flit Buffer OccupancyUNC_Q_VNA_CREDIT_RETURNSVNA Credits ReturnedUNC_Q_VNA_CREDIT_RETURN_OCCUPANCYVNA Credits Pending Return - OccupancyUNC_Q_TXR_AD_HOM_CREDIT_ACQUIREDR3QPI Egress credit occupancy AD HOMUNC_Q_TXR_AD_HOM_CREDIT_OCCUPANCYUNC_Q_TXR_AD_NDR_CREDIT_ACQUIREDR3QPI Egress credit occupancy AD NDRUNC_Q_TXR_AD_NDR_CREDIT_OCCUPANCYUNC_Q_TXR_AD_SNP_CREDIT_ACQUIREDR3QPI Egress credit occupancy AD SNPUNC_Q_TXR_AD_SNP_CREDIT_OCCUPANCYUNC_Q_TXR_AK_NDR_CREDIT_ACQUIREDR3QPI Egress credit occupancy AK NDRUNC_Q_TXR_AK_NDR_CREDIT_OCCUPANCYUNC_Q_TXR_BL_DRS_CREDIT_ACQUIREDR3QPI Egress credit occupancy BL DRSUNC_Q_TXR_BL_DRS_CREDIT_OCCUPANCYUNC_Q_TXR_BL_NCB_CREDIT_ACQUIREDR3QPI Egress credit occupancy BL NCBUNC_Q_TXR_BL_NCB_CREDIT_OCCUPANCYUNC_Q_TXR_BL_NCS_CREDIT_ACQUIREDR3QPI Egress credit occupancy BL NCSUNC_Q_TXR_BL_NCS_CREDIT_OCCUPANCY[UNC_QPI=0x%lx event=0x%x sel_ext=%d umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel Ivy Bridge-EP QPI0 uncoreivbep_unc_qpi0uncore_qpi_0Intel Ivy Bridge-EP QPI1 uncoreivbep_unc_qpi1uncore_qpi_1Intel Ivy Bridge-EP QPI2 uncoreivbep_unc_qpi2uncore_qpi_2DOORBELL_RCVDTBDINT_PRIOIPI_RCVDMSI_RCVDVLW_RCVDASSERT_TO_ACKNumber of cycles asserted to ACKACK_TO_DEASSERTNumber of cycles ACK to deassertUNC_U_EVENT_MSGVLW ReceivedUNC_U_LOCK_CYCLESIDI Lock/SplitLock CyclesUNC_U_PHOLD_CYCLESCycles PHOLD asserts to AckUNC_U_RACU_REQUESTSRACU requestsIntel Ivy Bridge-EP U-Box uncoreivbep_unc_ubouncore_uboxCCW_VR0_EVENCounter-clockwise and even ring polarity on virtual ring 0CCW_VR0_ODDCounter-clockwise and odd ring polarity on virtual ring 0CW_VR0_EVENClockwise and even ring polarity on virtual ring 0CW_VR0_ODDClockwise and odd ring polarity on virtual ring 0CCW_VR1_EVENCounter-clockwise and even ring polarity on virtual ring 1CCW_VR1_ODDCounter-clockwise and odd ring polarity on virtual ring 1CW_VR1_EVENClockwise and even ring polarity on virtual ring 1CW_VR1_ODDClockwise and odd ring polarity on virtual ring 1CWClockwise with any polarity on either virtual ringsCCWCounter-clockwise with any polarity on either virtual ringsClockwiseCounter-clockwiseDRSDRS Ingress queueANYany direction and any polarity on any virtual ringNCBNCB Ingress queueNCSNCS Ingress queueADAD Egress queueAKAK Egress queueBLBL Egress queueUNC_R2_CLOCKTICKSNumber of uclks in domainUNC_R2_RING_AD_USEDR2 AD Ring in UseUNC_R2_RING_AK_USEDR2 AK Ring in UseUNC_R2_RING_BL_USEDR2 BL Ring in UseUNC_R2_RING_IV_USEDR2 IV Ring in UseUNC_R2_RXR_AK_BOUNCESAK Ingress BouncedUNC_R2_RXR_OCCUPANCYIngress occupancy accumulatorUNC_R2_RXR_CYCLES_NEIngress Cycles Not EmptyUNC_R2_RXR_INSERTSIngress insertsUNC_R2_TXR_CYCLES_FULLEgress Cycles FullUNC_R2_TXR_CYCLES_NEEgress Cycles Not EmptyUNC_R2_TXR_NACK_CCWEgress counter-clockwise BACKUNC_R2_TXR_NACK_CWEgress clockwise BACKIntel Ivy Bridge-EP R2PCIe uncoreivbep_unc_r2pcieuncore_r2pcieCCW_VR0_EVENCounter-Clockwise and even ring polarity on virtual ring 0CCW_VR0_ODDCounter-Clockwise and odd ring polarity on virtual ring 0CW_VR0_EVENClockwise and even ring polarity on virtual ring 0CW_VR0_ODDClockwise and odd ring polarity on virtual ring 0CWClockwise with any polarity on either virtual ringsCCWCounter-clockwise with any polarity on either virtual ringsANYHOMHOM Ingress queueSNPSNP Ingress queueNDRNDR Ingress queueDRSDRS Ingress queueNCBNCB Ingress queueNCSNCS Ingress queueFilter HOM message classFilter SNP message classFilter NDR message classFilter DRS message classFilter NCB message classFilter NCS message classCBO8CBox 8CBO9CBox 9CBO10CBox 10CBO11CBox 11CBO12CBox 12CBO13CBox 13CBO14CBox 14 & 16CBO0CBox 0CBO1CBox 1CBO2CBox 2CBO3CBox 3CBO4CBox 4CBO5CBox 5CBO6CBox 6CBO7CBox 7HA0HA1R2_NCBR2 NCB messagesR2_NCSR2 NCS messagesVNAVN0_HOMVN0 HOM messagesVN0_SNPVN0 SNP messagesVN0_NDRVN0 NDR messagesVN1_HOMVN1 HOM messagesVN1_SNPVN1 SNP messagesVN1_NDRVN1 NDR messagesADBL counter-clockwise Egress queueAKAD clockwise Egress queueBLAD counter-clockwise Egress queueBL clockwise Egress queueFor AD ringFor BL ringUNC_R3_CLOCKTICKSNumber of uclks in domainUNC_R3_RING_AD_USEDR3 AD Ring in UseUNC_R3_RING_AK_USEDR3 AK Ring in UseUNC_R3_RING_BL_USEDR3 BL Ring in UseUNC_R3_RING_IV_USEDR3 IV Ring in UseUNC_R3_RXR_AD_BYPASSEDIngress BypassedUNC_R3_RXR_CYCLES_NEIngress Cycles Not EmptyUNC_R3_RXR_INSERTSIngress AllocationsUNC_R3_RXR_OCCUPANCYIngress Occupancy AccumulatorUNC_R3_TXR_CYCLES_FULLEgress cycles fullUNC_R3_VN0_CREDITS_REJECTVN0 Credit Acquisition FailedUNC_R3_VN0_CREDITS_USEDVN0 Credit UsedUNC_R3_VNA_CREDITS_ACQUIREDVNA credit AcquisitionsUNC_R3_VNA_CREDITS_REJECTVNA Credit RejectUNC_R3_VNA_CREDIT_CYCLES_OUTCycles with no VNA credits availableUNC_R3_VNA_CREDIT_CYCLES_USEDCycles with 1 or more VNA credits in useUNC_R3_C_HI_AD_CREDITS_EMPTYCbox AD credits emptyUNC_R3_C_LO_AD_CREDITS_EMPTYUNC_R3_HA_R2_BL_CREDITS_EMPTYHA/R2 AD credits emptyUNC_R3_QPI0_AD_CREDITS_EMPTYQPI0 AD credits emptyUNC_R3_QPI0_BL_CREDITS_EMPTYQPI0 BL credits emptyUNC_R3_QPI1_AD_CREDITS_EMPTYQPI1 AD credits emptyUNC_R3_QPI1_BL_CREDITS_EMPTYQPI1 BL credits emptyUNC_R3_TXR_CYCLES_NEEgress cycles not emptyUNC_R3_TXR_NACK_CCWEgress NACK counter-clockwiseUNC_R3_TXR_NACK_CWUNC_R3_VN1_CREDITS_REJECTVN1 Credit Acquisition FailedUNC_R3_VN1_CREDITS_USEDIntel Ivy Bridge-EP R3QPI0 uncoreivbep_unc_r3qpi0uncore_r3qpi_0Intel Ivy Bridge-EP R3QPI1 uncoreivbep_unc_r3qpi1uncore_r3qpi_1Intel Ivy Bridge-EP R3QPI2 uncoreivbep_unc_r3qpi2uncore_r3qpi_2STALL_COUNTNumber of time when it is not possible to merge two conflicting requests, a stall event occursMERGE_COUNTNumber of times when two requests to the same address from the same source are received back to back, it is possible to merge themANYAny sourceSOURCETrack all requests from any source portLOST_OWNERSHIPNumber of request that lost ownership as a result of a tickleTOP_OF_QUEUENumber of cases when a tickle was received but the request was at the head of the queue in the switch. In this case data is returned rather than releasing ownershipREADSNumber of read requests (not including read prefetches)WRITESNumber of write requests. Each write should have a prefetch, so there is no need to explicitly track these requestsRD_PREFETCHESNumber of read prefetchesUNC_I_CLOCKTICKSNumber of uclks in domainUNC_I_ADDRESS_MATCHAddress match conflict countUNC_I_CACHE_ACK_PENDING_OCCUPANCYWrite ACK pending occupancyUNC_I_CACHE_OWN_OCCUPANCYOutstanding write ownership occupancyUNC_I_CACHE_READ_OCCUPANCYOutstanding read occupancyUNC_I_CACHE_TOTAL_OCCUPANCYTotal write cache occupancyUNC_I_CACHE_WRITE_OCCUPANCYOutstanding write occupancyUNC_I_RXR_AK_CYCLES_FULLTBDUNC_I_RXR_AK_INSERTSEgress cycles fullUNC_I_RXR_AK_OCCUPANCYUNC_I_RXR_BL_DRS_CYCLES_FULLUNC_I_RXR_BL_DRS_INSERTSBL Ingress occupancy DRSUNC_I_RXR_BL_DRS_OCCUPANCYUNC_I_RXR_BL_NCB_CYCLES_FULLUNC_I_RXR_BL_NCB_INSERTSBL Ingress occupancy NCBUNC_I_RXR_BL_NCB_OCCUPANCYUNC_I_RXR_BL_NCS_CYCLES_FULLUNC_I_RXR_BL_NCS_INSERTSBL Ingress Occupancy NCSUNC_I_RXR_BL_NCS_OCCUPANCYUNC_I_TICKLESTickle countUNC_I_TRANSACTIONSInbound transaction countUNC_I_TXR_AD_STALL_CREDIT_CYCLESNo AD Egress credit stallsUNC_I_TXR_BL_STALL_CREDIT_CYCLESNo BL Egress credit stallsUNC_I_TXR_DATA_INSERTS_NCBOutbound read requestsUNC_I_TXR_DATA_INSERTS_NCSUNC_I_TXR_REQUEST_OCCUPANCYOutbound request queue occupancyUNC_I_WRITE_ORDERING_STALL_CYCLESWrite ordering stalls[UNC_IRP=0x%lx event=0x%x umask=0x%x en=%d edge=%d thres=%d] %s Intel Ivy Bridge-EP IRP uncoreivbep_unc_irpuncore_irpDATA_READData read requestsWRITEWrite requests. Includes all write transactions (cached, uncached)REMOTE_SNOOPExternal snoop requestANYAny requestNIDMatch a given RTID destination NID (must provide nf=X modifier)STATE_IInvalid cacheline stateSTATE_SShared cacheline stateSTATE_EExclusive cacheline stateSTATE_MModified cacheline stateSTATE_FForward cacheline stateSTATE_DDebug cacheline stateSTATE_MPCacheline is modified but never written, was forwarded in modified stateSTATE_MESIFDAny cache line stateLines in M stateLines in E stateLines in S stateLines in F stateMISSTBDVictimized Lines matching the NID filter (must provide nf=X modifier)UP_EVENUp and Even ring polarity filterUP_ODDUp and odd ring polarity filterDOWN_EVENDown and even ring polarity filterDOWN_ODDDown and odd ring polarity filterUPUp ring polarity filterDOWNDown ring polarity filterALLup or down ring polarity filterAD_IRQAKAcknowledgments to coreBLData responses to coreIVSnoops of processor cacheAny filterFilter on any up polarityDNFilter on any down polarityIRQIrq externally starved, therefore blocking the IPQIPQIPQ externally starved, therefore blocking the IRQPRQIRQ is blocking the ingress queue and causing starvationISMQ_BIDSNumber of time the ISMQ bidsIRQ_REJECTEDIRQ rejectedPRQ_REJECTEDPRQ rejectedADDR_CONFLICTAddress conflictAny RejectFULLNo Egress creditsQPI_CREDITSNo QPI creditsAD_SBOCount number of time that a request from the IPQ was retried because it lacked credits to send an AD packet to SBOTARGETCount number of times that a request from the IPQ was retried filtered by the target NodeIdAny rejectRTIDNo RTIDsIIO_CREDITSNo IIO CreditsCount number of time that a request from the IRQ was retried because it lacked credits to send an AD packet to SBOBL_SBOCount number of time that a request from the IRQ was retried because it lacked credits to send an BL packet to SBOCount number of times that a request from the IRQ was retried filtered by the target NodeIdNo IIO creditsNO QPI creditsWB_CREDITSNo WB creditsCount number of time that a request from the ISMQ was retried because it lacked credits to send an AD packet to SBOCount number of time that a request from the ISMQ was retried because it lacked credits to send an BL packet to SBOCount number of times that a request from the ISMQ was retried filtered by the target NodeIdOPCODENumber of transactions inserted into the TOR that match an opcode (must provide opc_* umask)MISS_OPCODENumber of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)EVICTIONNumber of Evictions transactions inserted into TORNumber of transactions inserted in TORWBNumber of write transactions inserted into the TORLOCAL_OPCODENumber of opcode-matched transactions inserted into the TOR that are satisfied by locally homed memoryMISS_LOCAL_OPCODENumber of miss opcode-matched transactions inserted into the TOR that are satisfied by locally homed memoryLOCALNumber of transactions inserted into the TOR that are satisfied by locally homed memoryMISS_LOCALNumber of miss transactions inserted into the TOR that are satisfied by locally homed memoryNID_OPCODENumber of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)NID_MISS_OPCODENumber of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)NID_EVICTIONNumber of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)NID_ALLNumber of NID-matched transactions inserted into the TOR (must provide nf=X modifier)NID_MISS_ALLNumber of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)NID_WBNumber of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)REMOTE_OPCODENumber of opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memoryMISS_REMOTE_OPCODENumber of miss opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memoryREMOTENumber of transactions inserted into the TOR that are satisfied by remote caches or memoryMISS_REMOTENumber of miss transactions inserted into the TOR that are satisfied by remote caches or memoryOPC_RFODemand data RFO (combine with any OPCODE umask)OPC_CRDDemand code read (combine with any OPCODE umask)OPC_DRDDemand data read (combine with any OPCODE umask)OPC_PRDPartial reads (UC) (combine with any OPCODE umask)OPC_WCILFFull Stream store (combine with any OPCODE umask)OPC_WCILPartial Stream store (combine with any OPCODE umask)OPC_WILWrite Invalidate Line (Partial) (combine with any OPCODE umask)OPC_PF_RFOPrefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PF_CODEPrefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PF_DATAPrefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PCIWILPCIe write (partial, non-allocating) - partial line MMIO write transactions from IIO (P2P). Not used for coherent transacions. Uncacheable. (combine with any OPCODE umask)OPC_PCIWIFPCIe write (full, non-allocating) - full line MMIO write transactions from IIO (P2P). Not used for coherent transacions. Uncacheable. (combine with any OPCODE umask)OPC_PCIITOMPCIe write (allocating) (combine with any OPCODE umask)OPC_PCIRDCURPCIe read current (combine with any OPCODE umask)OPC_WBMTOIRequest writeback modified invalidate line (combine with any OPCODE umask)OPC_WBMTOERequest writeback modified set to exclusive (combine with any OPCODE umask)OPC_ITOMRequest invalidate line. Request exclusive ownership of the line (combine with any OPCODE umask)OPC_PCINSRDPCIe non-snoop read (combine with any OPCODE umask)OPC_PCINSWRPCIe non-snoop write (partial) (combine with any OPCODE umask)OPC_PCINSWRFPCIe non-snoop write (full) (combine with any OPCODE umask)Number of TOR entries that match an opcode (must provide opc_* umask)Number of TOR entries that match a NID and an opcode (must provide opc_* umask)Number of outstanding eviction transactions in the TORAll valid TOR entriesMISS_ALLNumber of outstanding miss requests in the TORNumber of write transactions in the TOR. Does not include RFO, but actual operations that contain data being sent from the coreNumber of opcode-matched transactions in the TOR that are satisfied by locally homed memoryNumber of miss opcode-matched transactions in the TOR that are satisfied by locally homed memoryNumber of transactions in the TOR that are satisfied by locally homed memoryNumber of miss transactions in the TOR that are satisfied by locally homed memoryNumber of NID-matched TOR entries that an opcode (must provide nf=X modifier and opc_* umask)Number of NID-matched outstanding miss requests in the TOR that an opcode (must provide nf=X modifier and opc_* umask)Number of NID-matched outstanding requests in the TOR (must provide a nf=X modifier)Number of NID-matched outstanding requests in the TOR (must provide nf=X modifier)Number of NID-matched outstanding miss requests in the TOR (must provide a nf=X modifier)Number of NID-matched write transactions in the TOR (must provide a nf=X modifier)Number of opcode-matched transactions in the TOR that are satisfied by remote caches or memoryNumber of miss opcode-matched transactions in the TOR that are satisfied by remote caches or memoryNumber of transactions in the TOR that are satisfied by remote caches or memoryAD_CACHECounts the number of ring transactions from Cachebo to AD ringAK_CACHECounts the number of ring transactions from Cachebo to AK ringBL_CACHECounts the number of ring transactions from Cachebo to BL ringIV_CACHECounts the number of ring transactions from Cachebo ton IV ringAD_CORECounts the number of ring transactions from Corebo to AD ringAK_CORECounts the number of ring transactions from Corebo to AK ringBL_CORECounts the number of ring transactions from Corebo to BL ringADonto AD ringOnto AK ringOnto BL ringRSPI_WAS_FSECounts the number of times when a SNoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodingsWC_ALIASINGCounts the number of times a USWC write (WCIL(F)) transaction hits in the LLC in M state, triggering a WBMTOI followed by the USWC write. This occurs when there is WC aliasingSTARTEDRFO_HIT_SCounts the number of times that an RFO hits in S state. This is useful for determining if it might be good for a workload to use RSPIWB instead of RSPSWBCVZERO_PREFETCH_VICTIMCounts the number of clean victims with raw CV=0 (core valid)CVZERO_PREFETCH_MISSCounts the number of Demand Data Read requests hitting non-modified state lines with raw CV=0 (core valid)for AD ringfor BL ringUNC_C_CLOCKTICKSC-box Uncore clockticksUNC_C_COUNTER0_OCCUPANCYCounter 0 occupancy. Counts the occupancy related information by filtering CB0 occupancy count captured in counter 0.UNC_C_LLC_LOOKUPCache lookupsUNC_C_LLC_VICTIMSLines victimizedUNC_C_MISCMiscellaneous C-Box eventsUNC_C_RING_AD_USEDAddress ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_AK_USEDAcknowledgement ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_BL_USEDBus or Data ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_BOUNCESNumber of LLC responses that bounced in the ringUNC_C_FAST_ASSERTEDNumber of cycles in which the local distress or incoming distress signals are asserted (FaST). Incoming distress includes both up and downUNC_C_BOUNCE_CONTROLBounce controlUNC_C_RING_IV_USEDInvalidate ring in use. Counts number of cycles ring is being used at this ring stopUNC_C_RING_SRC_THRTLTDBUNC_C_RXR_EXT_STARVEDIngress arbiter blocking cyclesUNC_C_RXR_INSERTSIngress AllocationsUNC_C_RXR_IPQ_RETRYProbe Queue RetriesUNC_C_RXR_IPQ_RETRY2UNC_C_RXR_IRQ_RETRYIngress Request Queue RejectsUNC_C_RXR_IRQ_RETRY2UNC_C_RXR_ISMQ_RETRYISMQ RetriesUNC_C_RXR_ISMQ_RETRY2UNC_C_RXR_OCCUPANCYIngress OccupancyUNC_C_TOR_INSERTSTOR InsertsUNC_C_TOR_OCCUPANCYTOR OccupancyUNC_C_TXR_ADS_USEDEgress eventsUNC_C_TXR_INSERTSEgress allocationsUNC_C_SBO_CREDITS_ACQUIREDSBO credits acquiredUNC_C_SBO_CREDITS_OCCUPANCYSBO credits occupancy[UNC_CBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d tid_en=%d] %s [UNC_CBOX_FILTER0=0x%lx tid=%d core=0x%x state=0x%x] [UNC_CBOX_FILTER1=0x%lx nid=%d opc=0x%x nc=0x%x isoc=0x%x] Intel Haswell-EP C-Box 0 uncorehswep_unc_cbo0uncore_cbox_0Intel Haswell-EP C-Box 1 uncorehswep_unc_cbo1uncore_cbox_1Intel Haswell-EP C-Box 2 uncorehswep_unc_cbo2uncore_cbox_2Intel Haswell-EP C-Box 3 uncorehswep_unc_cbo3uncore_cbox_3Intel Haswell-EP C-Box 4 uncorehswep_unc_cbo4uncore_cbox_4Intel Haswell-EP C-Box 5 uncorehswep_unc_cbo5uncore_cbox_5Intel Haswell-EP C-Box 6 uncorehswep_unc_cbo6uncore_cbox_6Intel Haswell-EP C-Box 7 uncorehswep_unc_cbo7uncore_cbox_7Intel Haswell-EP C-Box 8 uncorehswep_unc_cbo8uncore_cbox_8Intel Haswell-EP C-Box 9 uncorehswep_unc_cbo9uncore_cbox_9Intel Haswell-EP C-Box 10 uncorehswep_unc_cbo10uncore_cbox_10Intel Haswell-EP C-Box 11 uncorehswep_unc_cbo11uncore_cbox_11Intel Haswell-EP C-Box 12 uncorehswep_unc_cbo12uncore_cbox_12Intel Haswell-EP C-Box 13 uncorehswep_unc_cbo13uncore_cbox_13Intel Haswell-EP C-Box 14 uncorehswep_unc_cbo14uncore_cbox_14Intel Haswell-EP C-Box 15 uncorehswep_unc_cbo15uncore_cbox_15Intel Haswell-EP C-Box 16 uncorehswep_unc_cbo16uncore_cbox_16Intel Haswell-EP C-Box 17 uncorehswep_unc_cbo17uncore_cbox_17NO_SNPSnoop not neededSNOOPSNooop neededTAKENBypass takenNOT_TAKENBypass not takenANYCounts any directory updateCLEARDirectory clearsSETDirectory setALLAll requestsREAD_OR_INVITOENumber of hits with opcode RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvToEWBMTOINumber of hits with opcode WbToMtoIACKCNFLTWBINumber of hits with opcode AckCnfltWbIWBMTOE_OR_SNumber of hits with opcode WbMtoE or WbMtoSHOMNumber of hits with HOM requestsRSPFWDI_REMOTENumber of hits with opcode RspIFwd, RspIFwdWb for remore requestsRSPFWDI_LOCALNumber of hits with opcode RspIFwd, RspIFwdWb for local requestsINVALSNumber of hits for invalidationsRSPFWDSNumber of hits with opcode RsSFwd, RspSFwdWbEVICTSNumber of hits for allocationsALLOCSRSPNumber of hits with opcode RspI, RspIWb, RspSWb, RspCnflt, RspCnfltWbIAD_QPI0AD to QPI link 0AD_QPI1AD to QPI link 1BL_QPI0BL to QPI link 0BL_QPI1BL to QPI link 1AD_QPI2AD to QPI link 2BL_QPI2BL to QPI link 2Counts all writesFULLCounts full line non ISOCHPARTIALCounts partial non-ISOCHFULL_ISOCHCounts ISOCH full linePARTIAL_ISOCHCounts ISOCH partialNORMALNormal priorityREADSCounts incoming read requests. Good proxy for LLC read misses, incl. RFOsREADS_LOCALCounts incoming read requests coming from local socket. Good proxy for LLC read misses, incl. RFOs from the local socketREADS_REMOTECounts incoming read requests coming from remote socket. Good proxy for LLC read misses, incl. RFOs from the remote socketWRITESCounts incoming writesWRITES_LOCALCounts incoming writes from local socketWRITES_REMOTECounts incoming writes from remote socketINVITOE_LOCALCounts InvItoE coming from local socketINVITOE_REMOTECounts InvItoE coming from remote socketCHN0Channel 0CHN1Channel 1CHN2channel 2CHN3Chanel 3REGION0Counts for TAD Region 0REGION1Counts for TAD Region 1REGION2Counts for TAD Region 2REGION3Counts for TAD Region 3REGION4Counts for TAD Region 4REGION5Counts for TAD Region 5REGION6Counts for TAD Region 6REGION7Counts for TAD Region 7REGION8Counts for TAD Region 8REGION9Counts for TAD Region 9REGION10Counts for TAD Region 10REGION11Counts for TAD Region 11RSPIFilters for snoop responses of RspI. RspI is returned when the remote cache does not have the data or when the remote cache silently evicts data (e.g. RFO hit non-modified line)RSPSFilters for snoop responses of RspS. RspS is returned when the remote cache has the data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E-stateRSPIFWDFilters for snoop responses of RspIFwd. RspIFwd is returned when the remote cache agent forwards data and the requesting agent is able to acquire the data in E or M state. This is commonly returned with RFO transacations. It can be either HitM or HitFERSPSFWDFilters for snoop responses of RspSFwd. RspSFwd is returned when the remote cache agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F stateRSP_WBFilters for snoop responses of RspIWB or RspSWB. This is returned when a non-RFO requests hits in M-state. Data and code reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownershipRSP_FWD_WBFilters for snoop responses of RspxFwdxWB. This snoop response is only used in 4s systems. It is used when a snoop HITM in a remote caching agent and it directly forwards data to a requester and simultaneously returns data to the home to be written back to memoryRSPCNFLCTFilters for snoop responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CMAs that caching agent. This triggers the conflict resolution hardware. This covers both RspConflct and RspCnflctWBICounts cycles full from both schedulersSCHED0Counts cycles full from scheduler bank 0SCHED1Counts cycles full from scheduler bank 1Counts cycles from both schedulersCounts cycles from scheduler bank 0Counts cycles from scheduler bank 1DRS_CACHECounts data being sent to the cacheDRS_CORECounts data being sent directly to the requesting coreDRS_QPICounts data being sent to a remote socket over QPIREMOTERemoteLocal readsLocal InvItoECANCELLEDCancelled due to D2C or OtherREADS_LOCAL_USEFULLocal reads - usefulREMOTE_USEFULRemote - usefulAll data returnsREADS_LOCAL_IReads to local IREADS_REMOTE_IReads to remote IREADS_LOCAL_SReads to local SREADS_REMOTE_SReads to remote SCCW_EVENCounter-clockwise and even ring polarityCCW_ODDCounter-clockwise and odd ring polarityCW_EVENClockwise and even ring polarityCW_ODDClockwise and odd ring polarityCWClockwise with any polarityCCWCounter-clockwise with any polarityOTHERFilters all other snoop responsesADFor AD ringBLFor BL ringLOCALLocalNDRNumber of outbound NDR (non-data response) transactions send on the AK ring. AK NDR is used for messages to the local socketCRD_CBONumber of outbound CDR transactions send on the AK ring to CBOCRD_QPINumber of outbound CDR transactions send on the AK ring to QPISBO0_ADNo credit for SBO0 AD RingSBO1_ADNo credit for SBO1 AD RingSBO0_BLNo credit for SBO0 BL RingSBO1_BLNo credit for SBO1 BL RingLocal read requestsRemote read requestsLocal write requestsRemote write requestsLocal InvItoE requestsRemote InvItoE requestsAKUNC_H_CLOCKTICKSHA Uncore clockticksUNC_H_CONFLICT_CYCLESConflict ChecksUNC_H_DIRECT2CORE_COUNTDirect2Core Messages SentUNC_H_DIRECT2CORE_CYCLES_DISABLEDCycles when Direct2Core was DisabledUNC_H_DIRECT2CORE_TXN_OVERRIDENumber of Reads that had Direct2Core OverriddenUNC_H_DIRECTORY_LOOKUPDirectory LookupsUNC_H_DIRECTORY_UPDATEDirectory UpdatesUNC_H_IGR_NO_CREDIT_CYCLESCycles without QPI Ingress CreditsUNC_H_IMC_RETRYRetry EventsUNC_H_IMC_WRITESHA to IMC Full Line Writes IssuedUNC_H_IMC_READSHA to IMC normal priority reads issuedUNC_H_REQUESTSRead and Write RequestsUNC_H_RPQ_CYCLES_NO_REG_CREDITSIMC RPQ Credits EmptyUNC_H_TAD_REQUESTS_G0HA Requests to a TAD RegionUNC_H_TAD_REQUESTS_G1UNC_H_TXR_AD_CYCLES_FULLAD Egress FullUNC_H_TXR_AK_CYCLES_FULLAK Egress FullUNC_H_TXR_AKOutbound Ring Transactions on AKUNC_H_TXR_BLOutbound DRS Ring Transactions to CacheUNC_H_TXR_BL_CYCLES_FULLBL Egress FullUNC_H_WPQ_CYCLES_NO_REG_CREDITSHA IMC CHN0 WPQ Credits EmptyUNC_H_BT_BYPASSBackup Tracker bypassUNC_H_BYPASS_IMCHA to IMC bypassUNC_H_BT_CYCLES_NEBackup Tracker cycles not emptyUNC_H_BT_OCCUPANCYBackup Tracker insertsUNC_H_OSBOSB snoop broadcastUNC_H_OSB_EDROSB early data returnUNC_H_RING_AD_USEDAD ring in useUNC_H_RING_AK_USEDAK ring in useUNC_H_RING_BL_USEDBL ring in useUNC_H_DIRECTORY_LAT_OPTDirectory latency optimization data return path takenUNC_H_SNOOP_RESP_RECV_LOCALSnoop responses received localUNC_H_SNP_RESP_RECV_LOCALUNC_H_TXR_BL_OCCUPANCYBL Egress occupancyUNC_H_SNOOP_RESPSnoop responses receivedUNC_H_HITME_HITHits in the HitMe cacheUNC_H_HITME_HIT_PV_BITS_SETNumber of PV bits set on HitMe cache hitsUNC_H_HITME_LOOKUPNumber of accesses to HitMe cacheUNC_H_SBO0_CREDIT_ACQUIREDSBO0 credits acquiredUNC_H_SBO0_CREDIT_OCCUPANCYSBO0 credits occupancyUNC_H_SBO1_CREDIT_ACQUIREDSBO1 credits acquiredSBO1 credits occupancyUNC_H_SNOOPS_RSP_AFTER_DATANumber of reads when the snoops was on the critical path to the data returnUNC_H_SNOOPS_CYCLES_NENumber of cycles when one or more snoops are outstandingUNC_H_SNOOPS_OCCUPANCYTracker snoops outstanding accumulatorUNC_H_STALL_NO_SBO_CREDITStalls on no SBO creditsUNC_H_TRACKER_CYCLES_NETracker cycles not emptyUNC_H_TRACKER_OCCUPANCYTracker occupancy accumulatorUNC_H_TRACKER_PENDING_OCCUPANCYData pending occupancy accumulatorUNC_H_TXR_STARVEDInjection starvation[UNC_HA=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s [UNC_HA_ADDR=0x%lx lo_addr=0x%x hi_addr=0x%x] [UNC_HA_OPC=0x%lx opc=0x%x] Intel Haswell-EP HA 0 uncorehswep_unc_ha0uncore_ha_0Intel Haswell-EP HA 1 uncorehswep_unc_ha1uncore_ha_1ALLCounts total number of DRAM CAS commands issued on this channelRDCounts all DRAM reads on this channel, incl. underfillsRD_REGCounts number of DRAM read CAS commands issued on this channel, incl. regular read CAS and those with implicit prechargeRD_UNDERFILLCounts number of underfill reads issued by the memory controllerWRCounts number of DRAM write CAS commands on this channelWR_RMMCounts Number of opportunistic DRAM write CAS commands issued on this channelWR_WMMCounts number of DRAM write CAS commands issued on this channel while in Write-Major modeRD_RMMCounts Number of opportunistic DRAM read CAS commands issued on this channelRD_WMMCounts number of DRAM read CAS commands issued on this channel while in Write-Major modeHIGHHighPANICPanicISOCHCounts cycles in ISOCH Major modePARTIALCounts cycles in Partial Major modeREADCounts cycles in Read Major modeWRITECounts cycles in Write Major modeRANK0Count cycles for rank 0RANK1Count cycles for rank 1RANK2Count cycles for rank 2RANK3Count cycles for rank 3RANK4Count cycles for rank 4RANK5Count cycles for rank 5RANK6Count cycles for rank 6RANK7Count cycles for rank 7RD_PREEMPT_RDCounts read over read preemptionsRD_PREEMPT_WRCounts read over write preemptionsPAGE_CLOSECounts number of DRAM precharge commands sent on this channel as a result of the page close counter expiringPAGE_MISSCounts number of DRAM precharge commands sent on this channel as a result of page missesPrecharge due to readPrecharge due to writeBYPPrecharge due to bypassActivate due to readActivate due to writeActivate due to bypassACTACT command issued by 2 cycle bypassCASCAS command issued by 2 cycle bypassPREPRE command issued by 2 cycle bypassLOWRead CAS issued with low priorityMEDRead CAS issued with medium priorityRead CAS issued with high priorityRead CAS issued with panic non isoch priority (starved)BANK0Bank 0BANK1Bank 1BANK2Bank 2BANK3Bank 3BANK4Bank 4BANK5Bank 5BANK6Bank 6BANK7Bank 7BANK8Bank 8BANK9Bank 9BANK10Bank 10BANK11Bank 11BANK12Bank 12BANK13Bank 13BANK14Bank 14BANK15Bank 15ALLBANKSBANKG0Bank Group 0 (bank 0-3)BANKG1Bank Group 1 (bank 4-7)BANKG2Bank Group 2 (8-11)BANKG3Bank Group 3 (12-15)WMMVMSE write push issued in WMMRMMVMSE write push issued in RMMLOW_THRESTransition from WMM to RMM because of starve counterSTARVEStarveVMSE_RETRYVMSE retryUNC_M_CLOCKTICKSIMC Uncore clockticks (fixed counter)UNC_M_DCLOCKTICKSIMC Uncore clockticks (generic counters)UNC_M_ACT_COUNTDRAM Activate CountUNC_M_CAS_COUNTDRAM RD_CAS and WR_CAS Commands.UNC_M_DRAM_PRE_ALLDRAM Precharge All CommandsUNC_M_DRAM_REFRESHNumber of DRAM Refreshes IssuedUNC_M_ECC_CORRECTABLE_ERRORSECC Correctable ErrorsUNC_M_MAJOR_MODESCycles in a Major ModeUNC_M_POWER_CHANNEL_DLLOFFChannel DLLOFF CyclesUNC_M_POWER_CHANNEL_PPDChannel PPD CyclesUNC_M_POWER_CKE_CYCLESCKE_ON_CYCLES by RankUNC_M_POWER_CRITICAL_THROTTLE_CYCLESCritical Throttle CyclesUNC_M_POWER_SELF_REFRESHClock-Enabled Self-RefreshUNC_M_POWER_THROTTLE_CYCLESThrottle CyclesUNC_M_POWER_PCU_THROTTLINGPCU throttlingUNC_M_PREEMPTIONRead Preemption CountUNC_M_PRE_COUNTDRAM Precharge commands.UNC_M_RPQ_CYCLES_NERead Pending Queue Not EmptyUNC_M_RPQ_INSERTSRead Pending Queue AllocationsUNC_M_WPQ_CYCLES_FULLWrite Pending Queue Full CyclesUNC_M_WPQ_CYCLES_NEWrite Pending Queue Not EmptyUNC_M_WPQ_READ_HITWrite Pending Queue CAM MatchUNC_M_WPQ_WRITE_HITUNC_M_BYP_CMDSBypass command eventUNC_M_RD_CAS_PRIORead CAS priorityUNC_M_RD_CAS_RANK0Read CAS access to Rank 0UNC_M_RD_CAS_RANK1Read CAS access to Rank 1UNC_M_RD_CAS_RANK2Read CAS access to Rank 2UNC_M_RD_CAS_RANK3Read CAS access to Rank 3UNC_M_RD_CAS_RANK4Read CAS access to Rank 4UNC_M_RD_CAS_RANK5Read CAS access to Rank 5UNC_M_RD_CAS_RANK6Read CAS access to Rank 6UNC_M_RD_CAS_RANK7Read CAS access to Rank 7UNC_M_VMSE_MXB_WR_OCCUPANCYVMSE MXB write buffer occupancyUNC_M_VMSE_WR_PUSHVMSE WR push issuedUNC_M_WMM_TO_RMMTransitions from WMM to RMM because of low thresholdUNC_M_WRONG_MMNot getting the requested major modeUNC_M_WR_CAS_RANK0Write CAS access to Rank 0UNC_M_WR_CAS_RANK1Write CAS access to Rank 1UNC_M_WR_CAS_RANK2Write CAS access to Rank 2UNC_M_WR_CAS_RANK3Write CAS access to Rank 3UNC_M_WR_CAS_RANK4Write CAS access to Rank 4UNC_M_WR_CAS_RANK5Write CAS access to Rank 5UNC_M_WR_CAS_RANK6Write CAS access to Rank 6UNC_M_WR_CAS_RANK7Write CAS access to Rank 7Intel Haswell-EP IMC0 uncorehswep_unc_imc0uncore_imc_0Intel Haswell-EP IMC1 uncorehswep_unc_imc1uncore_imc_1Intel Haswell-EP IMC2 uncorehswep_unc_imc2uncore_imc_2Intel Haswell-EP IMC3 uncorehswep_unc_imc3uncore_imc_3Intel Haswell-EP IMC4 uncorehswep_unc_imc4uncore_imc_4Intel Haswell-EP IMC5 uncorehswep_unc_imc5uncore_imc_5Intel Haswell-EP IMC6 uncorehswep_unc_imc6uncore_imc_6Intel Haswell-EP IMC7 uncorehswep_unc_imc7uncore_imc_7CORES_C0Counts number of cores in C0CORES_C3Counts number of cores in C3CORES_C6Counts number of cores in C6UNC_P_CLOCKTICKSPCU Uncore clockticksUNC_P_CORE0_TRANSITION_CYCLESCore 0 C State Transition CyclesUNC_P_CORE1_TRANSITION_CYCLESCore 1 C State Transition CyclesUNC_P_CORE2_TRANSITION_CYCLESCore 2 C State Transition CyclesUNC_P_CORE3_TRANSITION_CYCLESCore 3 C State Transition CyclesUNC_P_CORE4_TRANSITION_CYCLESCore 4 C State Transition CyclesUNC_P_CORE5_TRANSITION_CYCLESCore 5 C State Transition CyclesUNC_P_CORE6_TRANSITION_CYCLESCore 6 C State Transition CyclesUNC_P_CORE7_TRANSITION_CYCLESCore 7 C State Transition CyclesUNC_P_CORE8_TRANSITION_CYCLESCore 8 C State Transition CyclesUNC_P_CORE9_TRANSITION_CYCLESCore 9 C State Transition CyclesUNC_P_CORE10_TRANSITION_CYCLESCore 10 C State Transition CyclesUNC_P_CORE11_TRANSITION_CYCLESCore 11 C State Transition CyclesUNC_P_CORE12_TRANSITION_CYCLESCore 12 C State Transition CyclesUNC_P_CORE13_TRANSITION_CYCLESCore 13 C State Transition CyclesUNC_P_CORE14_TRANSITION_CYCLESCore 14 C State Transition CyclesUNC_P_CORE15_TRANSITION_CYCLESCore 15 C State Transition CyclesUNC_P_CORE16_TRANSITION_CYCLESCore 16 C State Transition CyclesUNC_P_CORE17_TRANSITION_CYCLESCore 17 C State Transition CyclesUNC_P_DEMOTIONS_CORE0Core 0 C State DemotionsUNC_P_DEMOTIONS_CORE1Core 1 C State DemotionsUNC_P_DEMOTIONS_CORE2Core 2 C State DemotionsUNC_P_DEMOTIONS_CORE3Core 3 C State DemotionsUNC_P_DEMOTIONS_CORE4Core 4 C State DemotionsUNC_P_DEMOTIONS_CORE5Core 5 C State DemotionsUNC_P_DEMOTIONS_CORE6Core 6 C State DemotionsUNC_P_DEMOTIONS_CORE7Core 7 C State DemotionsUNC_P_DEMOTIONS_CORE8Core 8 C State DemotionsUNC_P_DEMOTIONS_CORE9Core 9 C State DemotionsUNC_P_DEMOTIONS_CORE10Core 10 C State DemotionsUNC_P_DEMOTIONS_CORE11Core 11 C State DemotionsUNC_P_DEMOTIONS_CORE12Core 12 C State DemotionsUNC_P_DEMOTIONS_CORE13Core 13 C State DemotionsUNC_P_DEMOTIONS_CORE14Core 14 C State DemotionsUNC_P_DEMOTIONS_CORE15Core 15 C State DemotionsUNC_P_DEMOTIONS_CORE16Core 16 C State DemotionsUNC_P_DEMOTIONS_CORE17Core 17 C State DemotionsUNC_P_FREQ_BAND0_CYCLESFrequency ResidencyUNC_P_FREQ_BAND1_CYCLESUNC_P_FREQ_BAND2_CYCLESUNC_P_FREQ_BAND3_CYCLESUNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLESThermal Strongest Upper Limit CyclesUNC_P_FREQ_MAX_OS_CYCLESOS Strongest Upper Limit CyclesUNC_P_FREQ_MAX_POWER_CYCLESPower Strongest Upper Limit CyclesUNC_P_FREQ_MIN_IO_P_CYCLESIO P Limit Strongest Lower Limit CyclesUNC_P_FREQ_TRANS_CYCLESCycles spent changing FrequencyUNC_P_PKG_RESIDENCY_C0_CYCLESPackage C State residency - C0UNC_P_PKG_RESIDENCY_C1E_CYCLESPackage C State residency - C1EUNC_P_PKG_RESIDENCY_C2E_CYCLESPackage C State residency - C2EUNC_P_PKG_RESIDENCY_C3_CYCLESPackage C State residency - C3UNC_P_PKG_RESIDENCY_C6_CYCLESPackage C State residency - C6UNC_P_PKG_RESIDENCY_C7_CYCLESPackage C State residency - C7UNC_P_MEMORY_PHASE_SHEDDING_CYCLESMemory Phase Shedding CyclesUNC_P_POWER_STATE_OCCUPANCYNumber of cores in C0UNC_P_PROCHOT_EXTERNAL_CYCLESExternal ProchotUNC_P_PROCHOT_INTERNAL_CYCLESInternal ProchotUNC_P_TOTAL_TRANSITION_CYCLESTotal Core C State Transition CyclesUNC_P_VR_HOT_CYCLESVR Hot[UNC_PCU=0x%lx event=0x%x sel_ext=%d occ_sel=0x%x en=%d edge=%d thres=%d occ_inv=%d occ_edge=%d] %s [UNC_PCU_FILTER=0x%lx band0=%u band1=%u band2=%u band3=%u] Intel Haswell-EP PCU uncorehswep_unc_pcuuncore_pcuFAILURE_CREDITSNumber of spawn failures due to lack of Egress creditsFAILURE_CREDITS_RBTNumber of spawn failures due to lack of Egress credit and route-back table (RBT) bit was not setFAILURE_RBT_HITNumber of spawn failures because route-back table (RBT) specified that the transaction should not trigger a direct2core transactionSUCCESS_RBT_HITNumber of spawn successesFAILURE_MISSNumber of spawn failures due to RBT tag not matching although the valid bit was set and there was enough Egress creditsFAILURE_CREDITS_MISSNumber of spawn failures due to RBT tag not matching and they were not enough Egress credits. The valid bit was setFAILURE_RBT_MISSNumber of spawn failures due to RBT tag not matching, the valid bit was not set but there were enough Egress creditsFAILURE_CREDITS_RBT_MISSNumber of spawn failures due to RBT tag not matching, the valid bit was not set and there were not enough Egress creditsDRSNumber of times VN0 consumed for DRS message classHOMNumber of times VN0 consumed for HOM message classNCBNumber of times VN0 consumed for NCB message classNCSNumber of times VN0 consumed for NCS message classNDRNumber of times VN0 consumed for NDR message classSNPNumber of times VN0 consumed for SNP message classNumber of times VN1 consumed for DRS message classNumber of times VN1 consumed for HOM message classNumber of times VN1 consumed for NCB message classNumber of times VN1 consumed for NCS message classNumber of times VN1 consumed for NDR message classNumber of times VN1 consumed for SNP message classDATANumber of data flits over QPINON_DATANumber of non-NULL non-data flits over QPINumber of flits over QPI on the Data Response (DRS) channelDRS_DATANumber of data flits over QPI on the Data Response (DRS) channelDRS_NONDATANumber of protocol flits over QPI on the Data Response (DRS) channelNumber of flits over QPI on the home channelHOM_NONREQNumber of non-request flits over QPI on the home channelHOM_REQNumber of data requests over QPI on the home channelNumber of snoop requests flits over QPINumber of non-coherent bypass flitsNCB_DATANumber of non-coherent data flitsNCB_NONDATANumber of bypass non-data flitsNumber of non-coherent standard (NCS) flitsNDR_ADNumber of flits received over Non-data response (NDR) channelNDR_AKNumber of flits received on the Non-data response (NDR) channel)VN0for VN0VN1for VN1VN_SHRfor shared VNUNC_Q_CLOCKTICKSNumber of qfclksUNC_Q_CTO_COUNTCount of CTO EventsUNC_Q_DIRECT2COREDirect 2 Core SpawningUNC_Q_L1_POWER_CYCLESCycles in L1UNC_Q_RXL0P_POWER_CYCLESCycles in L0pUNC_Q_RXL0_POWER_CYCLESCycles in L0UNC_Q_RXL_BYPASSEDRx Flit Buffer BypassedUNC_Q_RXL_CREDITS_CONSUMED_VN0VN0 Credit ConsumedUNC_Q_RXL_CREDITS_CONSUMED_VN1VN1 Credit ConsumedUNC_Q_RXL_CREDITS_CONSUMED_VNAVNA Credit ConsumedUNC_Q_RXL_CYCLES_NERxQ Cycles Not EmptyUNC_Q_RXL_FLITS_G1Flits Received - Group 1UNC_Q_RXL_FLITS_G2Flits Received - Group 2UNC_Q_RXL_INSERTSRx Flit Buffer AllocationsUNC_Q_RXL_INSERTS_DRSRx Flit Buffer Allocations - DRSUNC_Q_RXL_INSERTS_HOMRx Flit Buffer Allocations - HOMUNC_Q_RXL_INSERTS_NCBRx Flit Buffer Allocations - NCBUNC_Q_RXL_INSERTS_NCSRx Flit Buffer Allocations - NCSUNC_Q_RXL_INSERTS_NDRRx Flit Buffer Allocations - NDRUNC_Q_RXL_INSERTS_SNPRx Flit Buffer Allocations - SNPUNC_Q_RXL_OCCUPANCYRxQ Occupancy - All PacketsUNC_Q_RXL_OCCUPANCY_DRSRxQ Occupancy - DRSUNC_Q_RXL_OCCUPANCY_HOMRxQ Occupancy - HOMUNC_Q_RXL_OCCUPANCY_NCBRxQ Occupancy - NCBUNC_Q_RXL_OCCUPANCY_NCSRxQ Occupancy - NCSUNC_Q_RXL_OCCUPANCY_NDRRxQ Occupancy - NDRUNC_Q_RXL_OCCUPANCY_SNPRxQ Occupancy - SNPUNC_Q_TXL0P_POWER_CYCLESUNC_Q_TXL0_POWER_CYCLESUNC_Q_TXL_BYPASSEDTx Flit Buffer BypassedUNC_Q_TXL_CYCLES_NETx Flit Buffer Cycles not EmptyUNC_Q_TXL_FLITS_G0Flits Transferred - Group 0UNC_Q_TXL_FLITS_G1Flits Transferred - Group 1UNC_Q_TXL_FLITS_G2Flits Transferred - Group 2UNC_Q_TXL_INSERTSTx Flit Buffer AllocationsUNC_Q_TXL_OCCUPANCYTx Flit Buffer OccupancyUNC_Q_VNA_CREDIT_RETURNSVNA Credits ReturnedUNC_Q_VNA_CREDIT_RETURN_OCCUPANCYVNA Credits Pending Return - OccupancyUNC_Q_TXR_AD_HOM_CREDIT_ACQUIREDR3QPI Egress credit occupancy AD HOMUNC_Q_TXR_AD_HOM_CREDIT_OCCUPANCYUNC_Q_TXR_AD_NDR_CREDIT_ACQUIREDR3QPI Egress credit occupancy AD NDRUNC_Q_TXR_AD_NDR_CREDIT_OCCUPANCYUNC_Q_TXR_AD_SNP_CREDIT_ACQUIREDR3QPI Egress credit occupancy AD SNPUNC_Q_TXR_AD_SNP_CREDIT_OCCUPANCYUNC_Q_TXR_AK_NDR_CREDIT_ACQUIREDR3QPI Egress credit occupancy AK NDRUNC_Q_TXR_AK_NDR_CREDIT_OCCUPANCYUNC_Q_TXR_BL_DRS_CREDIT_ACQUIREDR3QPI Egress credit occupancy BL DRSUNC_Q_TXR_BL_DRS_CREDIT_OCCUPANCYUNC_Q_TXR_BL_NCB_CREDIT_ACQUIREDR3QPI Egress credit occupancy BL NCBUNC_Q_TXR_BL_NCB_CREDIT_OCCUPANCYUNC_Q_TXR_BL_NCS_CREDIT_ACQUIREDR3QPI Egress credit occupancy BL NCSUNC_Q_TXR_BL_NCS_CREDIT_OCCUPANCY[UNC_QPI=0x%lx event=0x%x sel_ext=%d umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel Haswell-EP QPI0 uncorehswep_unc_qpi0uncore_qpi_0Intel Haswell-EP QPI1 uncorehswep_unc_qpi1uncore_qpi_1DOORBELL_RCVDTBDASSERT_TO_ACKNumber of cycles asserted to ACKUNC_U_EVENT_MSGVLW ReceivedUNC_U_PHOLD_CYCLESCycles PHOLD asserts to AckUNC_U_RACU_REQUESTSRACU requests[UNC_UBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel Haswell-EP U-Box uncorehswep_unc_ubouncore_uboxCCW_EVENCounter-clockwise and even ring polarity on virtual ringCCW_ODDCounter-clockwise and odd ring polarity on virtual ringCW_EVENClockwise and even ring polarity on virtual ringCW_ODDClockwise and odd ring polarity on virtual ringCWClockwise with any polarity on either virtual ringsCCWCounter-clockwise with any polarity on either virtual ringsUPUpDOWNDownDRSDRS Ingress queueClockwise with any polarity on virtual ringCounter-clockwise with any polarity on virtual ringANYany direction and any polarity on virtual ringNCBNCB Ingress queueNCSNCS Ingress queueADFor ring ADBLFor ring BLPRQ_QPI0QPI0PRQ_QPI1QPI1ISOCH_QPI0Isochronous QPI0ISOCH_QPI1Isochronous QPI1DN_ADAD counter clockwise Egress queueDN_BLBL counter clockwise Egress queueDN_AKAK counter clockwise Egress queueUP_ADAD clockwise Egress queueUP_BLBL clockwise Egress queueUP_AKAK clockwise Egress queueSBO0_ADFor SBO0, AD ringSBO1_ADFor SBO1, AD ringSBO0_BLFor SBO0, BL ringSBO1_BLFor SBO1, BL ringUNC_R2_CLOCKTICKSNumber of uclks in domainUNC_R2_RING_AD_USEDR2 AD Ring in UseUNC_R2_RING_AK_USEDR2 AK Ring in UseUNC_R2_RING_BL_USEDR2 BL Ring in UseUNC_R2_RING_IV_USEDR2 IV Ring in UseUNC_R2_RXR_AK_BOUNCESAK Ingress BouncedUNC_R2_RXR_OCCUPANCYIngress occupancy accumulatorUNC_R2_RXR_CYCLES_NEIngress Cycles Not EmptyUNC_R2_RXR_INSERTSIngress insertsUNC_R2_TXR_NACK_CWEgress clockwise BACKUNC_R2_SBO0_CREDITS_ACQUIREDSBO0 credits acquiredUNC_R2_STALL_NO_SBO_CREDITStall on No SBo CreditsUNC_R2_IIO_CREDITEgress counter-clockwise BACK[UNC_R2PCIE=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel Haswell-EP R2PCIe uncorehswep_unc_r2pcieuncore_r2pcieCCW_EVENCounter-Clockwise and even ring polarityCCW_ODDCounter-Clockwise and odd ring polarityCW_EVENClockwise and even ring polarityCW_ODDClockwise and odd ring polarityCWClockwise with any polarity on either virtual ringsCCWCounter-clockwise with any polarity on either virtual ringsANYHOMHOM Ingress queueSNPSNP Ingress queueNDRNDR Ingress queueDRSDRS Ingress queueNCBNCB Ingress queueNCSNCS Ingress queueFilter HOM message classFilter SNP message classFilter NDR message classFilter DRS message classFilter NCB message classFilter NCS message classCBO0CBox 0CBO1CBox 1CBO2CBox 2CBO3CBox 3CBO4CBox 4CBO5CBox 5CBO6CBox 6CBO7CBox 7CBO8CBox 8CBO9CBox 9CBO10CBox 10CBO11CBox 11CBO12CBox 12CBO13CBox 13CBO14_16CBox 14 and CBox 16CBO15_17CBox 15 and CBox 17HA0HA1R2_NCBR2 NCB messagesR2_NCSR2 NCS messagesVNAVN0_HOMVN0 HOM messagesVN0_SNPVN0 SNP messagesVN0_NDRVN0 NDR messagesVN1_HOMVN1 HOM messagesVN1_SNPVN1 SNP messagesVN1_NDRVN1 NDR messagesADFor AD ringBLFor BL ringAD clockwise Egress queueAKAD counter-clockwise Egress queueBL clockwise Egress queueSBO0_ADFor SBO0, AD ringSBO1_ADFor SBO1, AD ringSBO0_BLFor SBO0, BL ringSBO1_BLFor SBO1, BL ringFor AJ ringUNC_R3_CLOCKTICKSNumber of uclks in domainUNC_R3_RING_AD_USEDR3 AD Ring in UseUNC_R3_RING_AK_USEDR3 AK Ring in UseUNC_R3_RING_BL_USEDR3 BL Ring in UseUNC_R3_RING_IV_USEDR3 IV Ring in UseUNC_R3_RING_SINK_STARVEDR3 Ring stop starvedUNC_R3_RXR_CYCLES_NEIngress Cycles Not EmptyUNC_R3_RXR_CYCLES_NE_VN1VN1 Ingress Cycles Not EmptyUNC_R3_RXR_INSERTSIngress AllocationsUNC_R3_RXR_INSERTS_VN1VN1 Ingress AllocationsUNC_R3_RXR_OCCUPANCY_VN1VN1 Ingress Occupancy AccumulatorUNC_R3_VN0_CREDITS_REJECTVN0 Credit Acquisition FailedUNC_R3_VN0_CREDITS_USEDVN0 Credit UsedUNC_R3_VNA_CREDITS_ACQUIREDVNA credit AcquisitionsUNC_R3_VNA_CREDITS_REJECTVNA Credit RejectUNC_R3_STALL_NO_SBO_CREDITStall no SBO creditUNC_R3_C_LO_AD_CREDITS_EMPTYCbox AD credits emptyUNC_R3_C_HI_AD_CREDITS_EMPTYUNC_R3_QPI0_AD_CREDITS_EMPTYQPI0 AD credits emptyUNC_R3_QPI0_BL_CREDITS_EMPTYQPI0 BL credits emptyUNC_R3_QPI1_BL_CREDITS_EMPTYUNC_R3_HA_R2_BL_CREDITS_EMPTYHA/R2 AD credits emptyUNC_R3_SBO0_CREDITS_ACQUIREDSBO0 credits acquiredUNC_R3_SBO1_CREDITS_ACQUIREDSBO1 credits acquiredUNC_R3_TXR_NACKEgress NACKUNC_R3_VN1_CREDITS_REJECTVN1 Credit Acquisition FailedUNC_R3_VN1_CREDITS_USED[UNC_R3QPI=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel Haswell-EP R3QPI0 uncorehswep_unc_r3qpi0uncore_r3qpi_0Intel Haswell-EP R3QPI1 uncorehswep_unc_r3qpi1uncore_r3qpi_1Intel Haswell-EP R3QPI2 uncorehswep_unc_r3qpi2uncore_r3qpi_2ANYAny sourceSOURCETrack all requests from any source portPCIRDCURPCI read currentCRDDRDRFOPCITOMDRITOMPCIDCAHINTWBMTOICFLUSHFAST_REQFastpath requestsFAST_REJFastpath rejects2ND_RD_INSERTCache insert of read transaction as secondary2ND_WR_INSERTCache insert of write transaction as secondary2ND_ATOMIC_INSERTCache insert of atomic transaction as secondaryFAST_XFERFastpath trasnfers from primary to secondaryPF_ACK_HINTPrefetch ack hints from primary to secondaryPF_TIMEOUTPrefetch timeoutSLOW_ISlow transfer of I-state cachelineSLOW_SSlow transfer of S-state cachelineSLOW_ESlow transfer of e-state cachelineSLOW_MSlow transfer of M-state cachelineLOST_FWDLOST forwardsSEC_RCVD_INVLDReceived InvalidSEC_RCVD_VLDReceived ValidDATA_THROTTLEData throttledMISSMissHIT_IHit in Invalid stateHIT_ESHit in Exclusive or Shared stateHIT_MHit in Modified stateSNPCODESnoop CodeSNPDATASnoop DataSNPINVSnoop InvalidREADSReads (not including prefetches)WRITESWritesRD_PREFRead prefetchesWR_PREFWrite prefetchesATOMICAtomic transactionsOTHEROther kinds of transactionsORDERINGQTrack request coming from port designated in IRP OrderingQ filterUNC_I_CLOCKTICKSNumber of uclks in domainUNC_I_SNOOP_RESPSnoop responsesUNC_I_MISC0Miscellaneous eventsUNC_I_COHERENT_OPSCoherent operationsUNC_I_CACHE_TOTAL_OCCUPANCYTotal write cache occupancyUNC_I_RXR_AK_INSERTSEgress cycles fullUNC_I_RXR_BL_DRS_CYCLES_FULLTBDUNC_I_RXR_BL_DRS_INSERTSBL Ingress occupancy DRSUNC_I_RXR_BL_DRS_OCCUPANCYUNC_I_RXR_BL_NCB_CYCLES_FULLUNC_I_RXR_BL_NCB_INSERTSBL Ingress occupancy NCBUNC_I_RXR_BL_NCB_OCCUPANCYUNC_I_RXR_BL_NCS_CYCLES_FULLUNC_I_RXR_BL_NCS_INSERTSBL Ingress Occupancy NCSUNC_I_RXR_BL_NCS_OCCUPANCYUNC_I_TRANSACTIONSInbound transactionsUNC_I_MISC1Misc eventsUNC_I_TXR_AD_STALL_CREDIT_CYCLESNo AD Egress credit stallsUNC_I_TXR_BL_STALL_CREDIT_CYCLESNo BL Egress credit stallsUNC_I_TXR_DATA_INSERTS_NCBOutbound read requestsUNC_I_TXR_DATA_INSERTS_NCSUNC_I_TXR_REQUEST_OCCUPANCYOutbound request queue occupancy[UNC_IRP=0x%lx event=0x%x umask=0x%x en=%d edge=%d thres=%d] %s Intel Haswell-EP IRP uncorehswep_unc_irpuncore_irpUP_EVENUp and Even ring polarity filterUP_ODDUp and odd ring polarity filterDOWN_EVENDown and even ring polarity filterDOWN_ODDDown and odd ring polarity filterUPUp ring polarity filterDOWNDown ring polarity filterAD_CACHEAK_COREAcknowledgments to coreBL_COREData responses to coreIV_CORESnoops of processor cacheANYAny filterFilter on any up polarityFilter on any down polarityAD_CRDAD credisAD_BNCAD bouncesBL_CRDBL creditsBL_BNCBL bouncesAKIVADonto AD ringOnto AK ringBLOnto BL ringUNC_S_CLOCKTICKSS-box Uncore clockticksUNC_S_RING_AD_USEDAddress ring in use. Counts number of cycles ring is being used at this ring stopUNC_S_RING_AK_USEDAcknowledgement ring in use. Counts number of cycles ring is being used at this ring stopUNC_S_RING_BL_USEDBus or Data ring in use. Counts number of cycles ring is being used at this ring stopUNC_S_RING_IV_USEDInvalidate ring in use. Counts number of cycles ring is being used at this ring stopUNC_S_RING_BOUNCESNumber of LLC responses that bounced in the ringUNC_S_FAST_ASSERTEDNumber of cycles in which the local distress or incoming distress signals are asserted (FaST). Incoming distress includes both up and downUNC_C_BOUNCE_CONTROLBounce controlUNC_S_RXR_OCCUPANCYIngress OccupancyUNC_S_RXR_BYPASSIngress AllocationsUNC_S_RXR_INSERTSUNC_S_TXR_ADS_USEDEgress eventsUNC_S_TXR_INSERTSEgress allocationsUNC_S_TXR_OCCUPANCY[UNC_SBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel Haswell-EP S-BOX0 uncorehswep_unc_sbo0uncore_sbox_0Intel Haswell-EP S-BOX1 uncorehswep_unc_sbo1uncore_sbox_1Intel Haswell-EP S-BOX2 uncorehswep_unc_sbo2uncore_sbox_2Intel Haswell-EP S-BOX3 uncorehswep_unc_sbo3uncore_sbox_3ANYCache Lookups -- Any RequestDATA_READCache Lookups -- Data Read RequestNIDCache Lookups -- Lookups that Match NIDREADCache Lookups -- Any Read RequestREMOTE_SNOOPCache Lookups -- External Snoop RequestWRITECache Lookups -- Write RequestsSTATE_IInvalid cacheline stateSTATE_SShared cacheline stateSTATE_EExclusive cacheline stateSTATE_MModified cacheline stateSTATE_FForward cacheline stateSTATE_DDebug cacheline stateSTATE_MPCacheline is modified but never written, was forwarded in modified stateSTATE_MESIFDAny cache line stateF_STATELines in Forward stateI_STATELines in S StateS_STATELines in S stateE_STATELines in E stateM_STATELines in M stateMISSLines VictimizedLines Victimized -- Victimized Lines that Match NIDCVZERO_PREFETCH_MISSCbo Misc -- DRd hitting non-M with raw CV=0CVZERO_PREFETCH_VICTIMCbo Misc -- Clean Victim with raw CV=0RFO_HIT_SCbo Misc -- RFO HitSRSPI_WAS_FSECbo Misc -- Silent Snoop EvictionSTARTEDCbo Misc -- WC_ALIASINGCbo Misc -- Write Combining AliasingALLAD Ring In Use -- AllCCWAD Ring In Use -- DownCWAD Ring In Use -- UpDOWN_EVENAD Ring In Use -- Down and EvenDOWN_ODDAD Ring In Use -- Down and OddUP_EVENAD Ring In Use -- Up and EvenUP_ODDAD Ring In Use -- Up and OddAK Ring In Use -- AllAK Ring In Use -- DownAK Ring In Use -- UpAK Ring In Use -- Down and EvenAK Ring In Use -- Down and OddAK Ring In Use -- Up and EvenAK Ring In Use -- Up and OddBL Ring in Use -- DownBL Ring in Use -- UpBL Ring in Use -- Down and EvenBL Ring in Use -- Down and OddBL Ring in Use -- Up and EvenBL Ring in Use -- Up and OddADNumber of LLC responses that bounced on the Ring. -- ADAKNumber of LLC responses that bounced on the Ring. -- AKBLNumber of LLC responses that bounced on the Ring. -- BLIVNumber of LLC responses that bounced on the Ring. -- Snoops of processors cachee.BL Ring in Use -- AnyDNDOWNUPIPQIngress Arbiter Blocking Cycles -- IRQIRQIngress Arbiter Blocking Cycles -- IPQISMQ_BIDSIngress Arbiter Blocking Cycles -- ISMQ_BIDPRQIngress Arbiter Blocking Cycles -- PRQIngress Allocations -- IPQIngress Allocations -- IRQIRQ_REJIngress Allocations -- IRQ RejectedIngress Allocations -- PRQPRQ_REJADDR_CONFLICTProbe Queue Retries -- Address ConflictProbe Queue Retries -- Any RejectFULLProbe Queue Retries -- No Egress CreditsQPI_CREDITSProbe Queue Retries -- No QPI CreditsAD_SBOProbe Queue Retries -- No AD Sbo CreditsTARGETProbe Queue Retries -- Target Node FilterIngress Request Queue Rejects -- Address ConflictIngress Request Queue Rejects -- Any RejectIngress Request Queue Rejects -- No Egress CreditsIIO_CREDITSIngress Request Queue Rejects -- No IIO CreditsIngress Request Queue Rejects -- Ingress Request Queue Rejects -- No QPI CreditsRTIDIngress Request Queue Rejects -- No RTIDsIngress Request Queue Rejects -- No AD Sbo CreditsBL_SBOIngress Request Queue Rejects -- No BL Sbo CreditsIngress Request Queue Rejects -- Target Node FilterISMQ Retries -- Any RejectISMQ Retries -- No Egress CreditsISMQ Retries -- No IIO CreditsISMQ Retries -- ISMQ Retries -- No QPI CreditsISMQ Retries -- No RTIDsWB_CREDITSISMQ Request Queue Rejects -- No AD Sbo CreditsISMQ Request Queue Rejects -- No BL Sbo CreditsISMQ Request Queue Rejects -- Target Node FilterIngress Occupancy -- IPQIngress Occupancy -- IRQIngress Occupancy -- IRQ RejectedIngress Occupancy -- PRQ RejectsSBo Credits Acquired -- For AD RingSBo Credits Acquired -- For BL RingSBo Credits Occupancy -- For AD RingSBo Credits Occupancy -- For BL RingAllEVICTIONEvictionsLOCALLocal MemoryLOCAL_OPCODELocal Memory - Opcode MatchedMISS_LOCALMisses to Local MemoryMISS_LOCAL_OPCODEMisses to Local Memory - Opcode MatchedMISS_OPCODEMiss Opcode MatchMISS_REMOTEMisses to Remote MemoryMISS_REMOTE_OPCODEMisses to Remote Memory - Opcode MatchedNID_ALLNID MatchedNID_EVICTIONNID Matched EvictionsNID_MISS_ALLNID Matched Miss AllNID_MISS_OPCODENID and Opcode Matched MissNID_OPCODENID and Opcode MatchedNID_WBNID Matched WritebacksOPCODEOpcode MatchREMOTERemote MemoryREMOTE_OPCODERemote Memory - Opcode MatchedWBWritebacksOPC_RFODemand data RFO (combine with any OPCODE umask)OPC_CRDDemand code read (combine with any OPCODE umask)OPC_DRDDemand data read (combine with any OPCODE umask)OPC_PRDPartial reads (UC) (combine with any OPCODE umask)OPC_WCILFFull Stream store (combine with any OPCODE umask)OPC_WCILPartial Stream store (combine with any OPCODE umask)OPC_WILWrite Invalidate Line (Partial) (combine with any OPCODE umask)OPC_PF_RFOPrefetch RFO into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PF_CODEPrefetch code into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PF_DATAPrefetch data into LLC but do not pass to L2 (includes hints) (combine with any OPCODE umask)OPC_PCIWILPCIe write (partial, non-allocating) - partial line MMIO write transactions from IIO (P2P). Not used for coherent transacions. Uncacheable. (combine with any OPCODE umask)OPC_PCIWIFPCIe write (full, non-allocating) - full line MMIO write transactions from IIO (P2P). Not used for coherent transacions. Uncacheable. (combine with any OPCODE umask)OPC_PCIITOMPCIe write (allocating) (combine with any OPCODE umask)OPC_PCIRDCURPCIe read current (combine with any OPCODE umask)OPC_WBMTOIRequest writeback modified invalidate line (combine with any OPCODE umask)OPC_WBMTOERequest writeback modified set to exclusive (combine with any OPCODE umask)OPC_ITOMRequest invalidate line. Request exclusive ownership of the line (combine with any OPCODE umask)OPC_PCINSRDPCIe non-snoop read (combine with any OPCODE umask)OPC_PCINSWRPCIe non-snoop write (partial) (combine with any OPCODE umask)OPC_PCINSWRFPCIe non-snoop write (full) (combine with any OPCODE umask)AnyNumber of transactions in the TOR that are satisfied by locally homed memoryMISS_ALLMiss AllNumber of miss transactions in the TOR that are satisfied by locally homed memoryNumber of miss opcode-matched transactions inserted into the TOR that are satisfied by locally homed memoryNumber of miss transactions inserted into the TOR that match an opcode (must provide opc_* umask)Number of miss opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memoryNumber of NID-matched transactions inserted into the TOR (must provide nf=X modifier)Number of NID-matched eviction transactions inserted into the TOR (must provide nf=X modifier)Number of NID-matched miss transactions that were inserted into the TOR (must provide nf=X modifier)Number of NID and opcode matched miss transactions inserted into the TOR (must provide opc_* umask and nf=X modifier)Number of transactions inserted into the TOR that match a NID and opcode (must provide opc_* umask and nf=X modifier)Number of NID-matched write back transactions inserted into the TOR (must provide nf=X modifier)Number of transactions inserted into the TOR that match an opcode (must provide opc_* umask)Number of transactions inserted into the TOR that are satisfied by remote caches or memoryNumber of opcode-matched transactions inserted into the TOR that are satisfied by remote caches or memoryNumber of write transactions inserted into the TORNumber of miss transactions inserted into the TOR that are satisfied by remote caches or memoryOnto AD RingOnto AK RingOnto BL RingAD_CACHEEgress Allocations -- AD - CacheboAD_COREEgress Allocations -- AD - CoreboAK_CACHEEgress Allocations -- AK - CacheboAK_COREEgress Allocations -- AK - CoreboBL_CACHEEgress Allocations -- BL - CachenoBL_COREEgress Allocations -- BL - CoreboIV_CACHEEgress Allocations -- IV - CacheboUNC_C_BOUNCE_CONTROLTBDUNC_C_CLOCKTICKSClock ticksUNC_C_COUNTER0_OCCUPANCYSince occupancy counts can only be captured in the Cbos 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entryy.UNC_C_FAST_ASSERTEDCounts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn.UNC_C_LLC_LOOKUPCounts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.UNC_C_LLC_VICTIMSCounts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.UNC_C_MISCMiscellaneous events in the Cbo.UNC_C_RING_AD_USEDCounts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_C_RING_AK_USEDCounts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_C_RING_BL_USEDCounts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_C_RING_BOUNCESUNC_C_RING_IV_USEDCounts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.UNC_C_RING_SRC_THRTLUNC_C_RXR_EXT_STARVEDCounts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.UNC_C_RXR_INSERTSCounts number of allocations per cycle into the specified Ingress queue.UNC_C_RXR_IPQ_RETRYNumber of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.UNC_C_RXR_IPQ_RETRY2UNC_C_RXR_IRQ_RETRYUNC_C_RXR_IRQ_RETRY2UNC_C_RXR_ISMQ_RETRYNumber of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.UNC_C_RXR_ISMQ_RETRY2UNC_C_RXR_OCCUPANCYCounts number of entries in the specified Ingress queue in each cycle.UNC_C_SBO_CREDITS_ACQUIREDNumber of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.UNC_C_SBO_CREDIT_OCCUPANCYNumber of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.UNC_C_TOR_INSERTSCounts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent filters but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x1(0x182).UNC_C_TOR_OCCUPANCYFor each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent filters but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x (0x182)UNC_C_TXR_ADS_USEDUNC_C_TXR_INSERTSNumber of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.[UNC_CBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d tid_en=%d] %s [UNC_CBOX_FILTER0=0x%lx tid=%d core=0x%x state=0x%x] [UNC_CBOX_FILTER1=0x%lx nid=%d opc=0x%x nc=0x%x isoc=0x%x] Intel BroadwellX C-Box 0 uncorebdx_unc_cbo0uncore_cbox_0Intel BroadwellX C-Box 1 uncorebdx_unc_cbo1uncore_cbox_1Intel BroadwellX C-Box 2 uncorebdx_unc_cbo2uncore_cbox_2Intel BroadwellX C-Box 3 uncorebdx_unc_cbo3uncore_cbox_3Intel BroadwellX C-Box 4 uncorebdx_unc_cbo4uncore_cbox_4Intel BroadwellX C-Box 5 uncorebdx_unc_cbo5uncore_cbox_5Intel BroadwellX C-Box 6 uncorebdx_unc_cbo6uncore_cbox_6Intel BroadwellX C-Box 7 uncorebdx_unc_cbo7uncore_cbox_7Intel BroadwellX C-Box 8 uncorebdx_unc_cbo8uncore_cbox_8Intel BroadwellX C-Box 9 uncorebdx_unc_cbo9uncore_cbox_9Intel BroadwellX C-Box 10 uncorebdx_unc_cbo10uncore_cbox_10Intel BroadwellX C-Box 11 uncorebdx_unc_cbo11uncore_cbox_11Intel BroadwellX C-Box 12 uncorebdx_unc_cbo12uncore_cbox_12Intel BroadwellX C-Box 13 uncorebdx_unc_cbo13uncore_cbox_13Intel BroadwellX C-Box 14 uncorebdx_unc_cbo14uncore_cbox_14Intel BroadwellX C-Box 15 uncorebdx_unc_cbo15uncore_cbox_15Intel BroadwellX C-Box 16 uncorebdx_unc_cbo16uncore_cbox_16Intel BroadwellX C-Box 17 uncorebdx_unc_cbo17uncore_cbox_17Intel BroadwellX C-Box 18 uncorebdx_unc_cbo18uncore_cbox_18Intel BroadwellX C-Box 19 uncorebdx_unc_cbo19uncore_cbox_19Intel BroadwellX C-Box 20 uncorebdx_unc_cbo20uncore_cbox_20Intel BroadwellX C-Box 21 uncorebdx_unc_cbo21uncore_cbox_21Intel BroadwellX C-Box 22 uncorebdx_unc_cbo22uncore_cbox_22Intel BroadwellX C-Box 23 uncorebdx_unc_cbo23uncore_cbox_23DOORBELL_RCVDVLW ReceivedASSERT_TO_ACKCycles PHOLD Assert to Ack. Assert to ACKUNC_U_EVENT_MSGVirtual Logical Wire (legacy) message were received from uncoreUNC_U_PHOLD_CYCLESPHOLD cycles. Filter from source CoreID.UNC_U_RACU_REQUESTSNumber outstanding register requests within message channel tracker[UNC_UBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel BroadwellX U-Box uncorebdx_unc_ubouncore_uboxDOWN_EVENDown and EventDOWN_ODDDown and OddUP_EVENUp and EvenUP_ODDUp and OddUPUpDOWNDownAD_CACHENumber of LLC responses that bounced on the Ring. -- AK_CORENumber of LLC responses that bounced on the Ring. -- Acknowledgements to coreBL_CORENumber of LLC responses that bounced on the Ring. -- Data Responses to coreIV_CORENumber of LLC responses that bounced on the Ring. -- Snoops of processors cachee.DNBL Ring in Use -- AnyAD_BNCBypass -- AD - BouncesAD_CRDBypass -- AD - CreditsAKBypass -- AKBL_BNCBypass -- BL - BouncesBL_CRDBypass -- BL - CreditsIVBypass -- IVIngress Allocations -- AD - BouncesIngress Allocations -- AD - CreditsIngress Allocations -- AKIngress Allocations -- BL - BouncesIngress Allocations -- BL - CreditsIngress Allocations -- IVIngress Occupancy -- AD - BouncesIngress Occupancy -- AD - CreditsIngress Occupancy -- AKIngress Occupancy -- BL - BouncesIngress Occupancy -- BL - CreditsIngress Occupancy -- IVADTBDBLEgress Allocations -- AD - BouncesEgress Allocations -- AD - CreditsEgress Allocations -- AKEgress Allocations -- BL - BouncesEgress Allocations -- BL - CreditsEgress Allocations -- IVEgress Occupancy -- AD - BouncesEgress Occupancy -- AD - CreditsEgress Occupancy -- AKEgress Occupancy -- BL - BouncesEgress Occupancy -- BL - CreditsEgress Occupancy -- IVIVSNOOPGO_UPIVSNOOP_DNAK_U2C_UP_EVENAK_U2C_UP_ODDAK_U2C_DN_EVENAK_U2C_DN_ODDUNC_S_BOUNCE_CONTROLUNC_S_CLOCKTICKSUNC_S_FAST_ASSERTEDCounts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.UNC_S_RING_AD_USEDCounts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_S_RING_AK_USEDCounts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_S_RING_BL_USEDCounts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_S_RING_BOUNCESUNC_S_RING_IV_USEDCounts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in BDX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.UNC_S_RXR_BYPASSBypass the Sbo Ingress.UNC_S_RXR_INSERTSNumber of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.UNC_S_RXR_OCCUPANCYOccupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.UNC_S_TXR_ADS_USEDUNC_S_TXR_INSERTSNumber of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.UNC_S_TXR_OCCUPANCYOccupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.UNC_S_TXR_ORDERINGTB[UNC_SBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel BroadwellX S-BOX0 uncorebdx_unc_sbo0uncore_sbox_0Intel BroadwellX S-BOX1 uncorebdx_unc_sbo1uncore_sbox_1Intel BroadwellX S-BOX2 uncorebdx_unc_sbo2uncore_sbox_2Intel BroadwellX S-BOX3 uncorebdx_unc_sbo3uncore_sbox_3NOT_TAKENHA to iMC Bypass -- Not TakenTAKENHA to iMC Bypass -- TakenNO_SNPDirectory Lookups -- Snoop Not NeededSNPDirectory Lookups -- Snoop NeededANYDirectory Updates -- Any Directory UpdateCLEARDirectory Updates -- Directory ClearSETDirectory Updates -- Directory SetACKCNFLTWBICounts Number of Hits in HitMe Cache -- op is AckCnfltWbIALLCounts Number of Hits in HitMe Cache -- All RequestsALLOCSCounts Number of Hits in HitMe Cache -- AllocationsEVICTSHOMCounts Number of Hits in HitMe Cache -- HOM RequestsINVALSCounts Number of Hits in HitMe Cache -- InvalidationsREAD_OR_INVITOECounts Number of Hits in HitMe Cache -- op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoERSPCounts Number of Hits in HitMe Cache -- op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbIRSPFWDI_LOCALCounts Number of Hits in HitMe Cache -- op is RspIFwd or RspIFwdWb for a local requestRSPFWDI_REMOTECounts Number of Hits in HitMe Cache -- op is RspIFwd or RspIFwdWb for a remote requestRSPFWDSCounts Number of Hits in HitMe Cache -- op is RsSFwd or RspSFwdWbWBMTOE_OR_SCounts Number of Hits in HitMe Cache -- op is WbMtoE or WbMtoSWBMTOICounts Number of Hits in HitMe Cache -- op is WbMtoIAccumulates Number of PV bits set on HitMe Cache Hits -- op is AckCnfltWbIAccumulates Number of PV bits set on HitMe Cache Hits -- All RequestsAccumulates Number of PV bits set on HitMe Cache Hits -- HOM RequestsAccumulates Number of PV bits set on HitMe Cache Hits -- op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoEAccumulates Number of PV bits set on HitMe Cache Hits -- op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbIAccumulates Number of PV bits set on HitMe Cache Hits -- op is RspIFwd or RspIFwdWb for a local requestAccumulates Number of PV bits set on HitMe Cache Hits -- op is RspIFwd or RspIFwdWb for a remote requestAccumulates Number of PV bits set on HitMe Cache Hits -- op is RsSFwd or RspSFwdWbAccumulates Number of PV bits set on HitMe Cache Hits -- op is WbMtoE or WbMtoSAccumulates Number of PV bits set on HitMe Cache Hits -- op is WbMtoICounts Number of times HitMe Cache is accessed -- op is AckCnfltWbICounts Number of times HitMe Cache is accessed -- All RequestsCounts Number of times HitMe Cache is accessed -- AllocationsCounts Number of times HitMe Cache is accessed -- HOM RequestsCounts Number of times HitMe Cache is accessed -- InvalidationsCounts Number of times HitMe Cache is accessed -- op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoECounts Number of times HitMe Cache is accessed -- op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbICounts Number of times HitMe Cache is accessed -- op is RspIFwd or RspIFwdWb for a local requestCounts Number of times HitMe Cache is accessed -- op is RspIFwd or RspIFwdWb for a remote requestCounts Number of times HitMe Cache is accessed -- op is RsSFwd or RspSFwdWbCounts Number of times HitMe Cache is accessed -- op is WbMtoE or WbMtoSCounts Number of times HitMe Cache is accessed -- op is WbMtoIAD_QPI0Cycles without QPI Ingress Credits -- AD to QPI Link 0AD_QPI1Cycles without QPI Ingress Credits -- AD to QPI Link 1AD_QPI2Cycles without QPI Ingress Credits -- BL to QPI Link 0BL_QPI0BL_QPI1Cycles without QPI Ingress Credits -- BL to QPI Link 1BL_QPI2NORMALHA to iMC Normal Priority Reads Issued -- Normal PriorityHA to iMC Full Line Writes Issued -- All WritesFULLHA to iMC Full Line Writes Issued -- Full Line Non-ISOCHFULL_ISOCHHA to iMC Full Line Writes Issued -- ISOCH Full LinePARTIALHA to iMC Full Line Writes Issued -- Partial Non-ISOCHPARTIAL_ISOCHHA to iMC Full Line Writes Issued -- ISOCH PartialCANCELLEDOSB Snoop Broadcast -- CancelledINVITOE_LOCALOSB Snoop Broadcast -- Local InvItoEREADS_LOCALOSB Snoop Broadcast -- Local ReadsREADS_LOCAL_USEFULOSB Snoop Broadcast -- Reads Local - UsefulREMOTEOSB Snoop Broadcast -- RemoteREMOTE_USEFULOSB Snoop Broadcast -- Remote - UsefulOSB Early Data Return -- AllREADS_LOCAL_IOSB Early Data Return -- Reads to Local IREADS_LOCAL_SOSB Early Data Return -- Reads to Local SREADS_REMOTE_IOSB Early Data Return -- Reads to Remote IREADS_REMOTE_SOSB Early Data Return -- Reads to Remote SRead and Write Requests -- Local InvItoEsINVITOE_REMOTERead and Write Requests -- Remote InvItoEsREADSRead and Write Requests -- ReadsRead and Write Requests -- Local ReadsREADS_REMOTERead and Write Requests -- Remote ReadsWRITESRead and Write Requests -- WritesWRITES_LOCALRead and Write Requests -- Local WritesWRITES_REMOTERead and Write Requests -- Remote WritesCCWCounterclockwiseCCW_EVENCounterclockwise and EvenCCW_ODDCounterclockwise and OddCWClockwiseCW_EVENClockwise and EvenCW_ODDClockwise and OddCHN0iMC RPQ Credits Empty - Regular -- Channel 0CHN1iMC RPQ Credits Empty - Regular -- Channel 1CHN2iMC RPQ Credits Empty - Regular -- Channel 2CHN3iMC RPQ Credits Empty - Regular -- Channel 3ADFor AD RingBLFor BL RingLOCALData beat the Snoop Responses -- Local RequestsData beat the Snoop Responses -- Remote RequestsCycles with Snoops Outstanding -- All RequestsCycles with Snoops Outstanding -- Local RequestsCycles with Snoops Outstanding -- Remote RequestsTracker Snoops Outstanding Accumulator -- Local RequestsTracker Snoops Outstanding Accumulator -- Remote RequestsRSPCNFLCTSnoop Responses Received -- RSPCNFLCT*RSPISnoop Responses Received -- RspIRSPIFWDSnoop Responses Received -- RspIFwdRSPSSnoop Responses Received -- RspSRSPSFWDSnoop Responses Received -- RspSFwdRSP_FWD_WBSnoop Responses Received -- Rsp*Fwd*WBRSP_WBSnoop Responses Received -- Rsp*WBOTHERSnoop Responses Received Local -- OtherSnoop Responses Received Local -- RspCnflctSnoop Responses Received Local -- RspISnoop Responses Received Local -- RspIFwdSnoop Responses Received Local -- RspSSnoop Responses Received Local -- RspSFwdRSPxFWDxWBSnoop Responses Received Local -- Rsp*FWD*WBRSPxWBSnoop Responses Received Local -- Rsp*WBSBO0_ADStall on No Sbo Credits -- For SBo0, AD RingSBO0_BLStall on No Sbo Credits -- For SBo0, BL RingSBO1_ADStall on No Sbo Credits -- For SBo1, AD RingSBO1_BLStall on No Sbo Credits -- For SBo1, BL RingREGION0HA Requests to a TAD Region - Group 0 -- TAD Region 0REGION1HA Requests to a TAD Region - Group 0 -- TAD Region 1REGION2HA Requests to a TAD Region - Group 0 -- TAD Region 2REGION3HA Requests to a TAD Region - Group 0 -- TAD Region 3REGION4HA Requests to a TAD Region - Group 0 -- TAD Region 4REGION5HA Requests to a TAD Region - Group 0 -- TAD Region 5REGION6HA Requests to a TAD Region - Group 0 -- TAD Region 6REGION7HA Requests to a TAD Region - Group 0 -- TAD Region 7REGION10HA Requests to a TAD Region - Group 1 -- TAD Region 10REGION11HA Requests to a TAD Region - Group 1 -- TAD Region 11REGION8HA Requests to a TAD Region - Group 1 -- TAD Region 8REGION9HA Requests to a TAD Region - Group 1 -- TAD Region 9Tracker Cycles Full -- Cycles Completely UsedGPTracker Cycles Full -- Cycles GP Completely UsedTracker Cycles Not Empty -- All RequestsTracker Cycles Not Empty -- Local RequestsTracker Cycles Not Empty -- Remote RequestsTracker Occupancy Accumultor -- Local InvItoE RequestsTracker Occupancy Accumultor -- Remote InvItoE RequestsTracker Occupancy Accumultor -- Local Read RequestsTracker Occupancy Accumultor -- Remote Read RequestsTracker Occupancy Accumultor -- Local Write RequestsTracker Occupancy Accumultor -- Remote Write RequestsData Pending Occupancy Accumultor -- Local RequestsData Pending Occupancy Accumultor -- Remote RequestsAllSCHED0Scheduler 0SCHED1Scheduler 1DRS_CACHEOutbound DRS Ring Transactions to Cache -- Data to CacheDRS_COREOutbound DRS Ring Transactions to Cache -- Data to CoreDRS_QPIOutbound DRS Ring Transactions to Cache -- Data to QPIAKInjection Starvation -- For AK RingInjection Starvation -- For BL RingHA iMC CHN0 WPQ Credits Empty - Regular -- Channel 0HA iMC CHN0 WPQ Credits Empty - Regular -- Channel 1HA iMC CHN0 WPQ Credits Empty - Regular -- Channel 2HA iMC CHN0 WPQ Credits Empty - Regular -- Channel 3UNC_H_BT_CYCLES_NECycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.UNC_H_BT_OCCUPANCYAccumulates the occupancy of te HA BT pool in every cycle. This can be used with the 'not empty' stat to calculate the average queue occupancy or the 'allocations' stat to calculate average queue latency. HA BTs are allocated as son as a request enters the HA and are released after the snoop response and data return and the response is returned to the ringUNC_H_BYPASS_IMCCounts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.UNC_H_CONFLICT_CYCLESTBDUNC_H_CLOCKTICKSCounts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.UNC_H_DIRECT2CORE_COUNTNumber of Direct2Core messages sentUNC_H_DIRECT2CORE_CYCLES_DISABLEDNumber of cycles in which Direct2Core was disabledUNC_H_DIRECT2CORE_TXN_OVERRIDENumber of Reads where Direct2Core overriddenUNC_H_DIRECTORY_LAT_OPTDirectory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).UNC_H_DIRECTORY_LOOKUPCounts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.UNC_H_DIRECTORY_UPDATECounts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.UNC_H_HITME_HITUNC_H_HITME_HIT_PV_BITS_SETUNC_H_HITME_LOOKUPUNC_H_IGR_NO_CREDIT_CYCLESCounts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.UNC_H_IMC_READSCount of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.UNC_H_IMC_RETRYUNC_H_IMC_WRITESCounts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.UNC_H_OSBCount of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.UNC_H_OSB_EDRCounts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data returnUNC_H_REQUESTSCounts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).UNC_H_RING_AD_USEDCounts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.UNC_H_RING_AK_USEDCounts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.UNC_H_RING_BL_USEDCounts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.UNC_H_RPQ_CYCLES_NO_REG_CREDITSCounts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMCs RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given iven time.UNC_H_SBO0_CREDITS_ACQUIREDNumber of Sbo 0 credits acquired in a given cycle, per ring.UNC_H_SBO0_CREDIT_OCCUPANCYNumber of Sbo 0 credits in use in a given cycle, per ring.UNC_H_SBO1_CREDITS_ACQUIREDNumber of Sbo 1 credits acquired in a given cycle, per ring.UNC_H_SBO1_CREDIT_OCCUPANCYNumber of Sbo 1 credits in use in a given cycle, per ring.UNC_H_SNOOPS_RSP_AFTER_DATACounts the number of reads when the snoop was on the critical path to the data return.UNC_H_SNOOP_CYCLES_NECounts cycles when one or more snoops are outstanding.UNC_H_SNOOP_OCCUPANCYAccumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have retureturned.UNC_H_SNOOP_RESPCounts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.UNC_H_SNP_RESP_RECV_LOCALNumber of snoop responses received for a Local requestUNC_H_STALL_NO_SBO_CREDITNumber of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.UNC_H_TAD_REQUESTS_G0Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save powewer.UNC_H_TAD_REQUESTS_G1Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save powewer.UNC_H_TRACKER_CYCLES_FULLCounts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.UNC_H_TRACKER_CYCLES_NECounts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.UNC_H_TRACKER_OCCUPANCYAccumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the rhe ring.UNC_H_TRACKER_PENDING_OCCUPANCYAccumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system cant schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requestss.UNC_H_TXR_AD_CYCLES_FULLAD Egress FullUNC_H_TXR_AK_CYCLES_FULLAK Egress FullUNC_H_TXR_BLCounts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.UNC_H_TXR_BL_CYCLES_FULLBL Egress FullUNC_H_TXR_STARVEDCounts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.UNC_H_WPQ_CYCLES_NO_REG_CREDITSCounts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMCs WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given iven time.[UNC_HA=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s [UNC_HA_ADDR=0x%lx lo_addr=0x%x hi_addr=0x%x] [UNC_HA_OPC=0x%lx opc=0x%x] Intel BroadwellX HA 0 uncorebdx_unc_ha0uncore_ha_0Intel BroadwellX HA 1 uncorebdx_unc_ha1uncore_ha_1BYPDRAM Activate Count -- Activate due to WriteRDDRAM Activate Count -- Activate due to ReadWRACTACT command issued by 2 cycle bypassCASCAS command issued by 2 cycle bypassPREPRE command issued by 2 cycle bypassALLDRAM RD_CAS and WR_CAS Commands. All DRAM WR_CAS (w/ and w/out auto-pre)DRAM RD_CAS and WR_CAS Commands. All DRAM Reads (RD_CAS + Underfills)RD_REGDRAM RD_CAS and WR_CAS Commands. All DRAM RD_CAS (w/ and w/out auto-pre)RD_RMMDRAM RD_CAS and WR_CAS Commands. Read CAS issued in RMMRD_UNDERFILLDRAM RD_CAS and WR_CAS Commands. Underfill Read IssuedRD_WMMDRAM RD_CAS and WR_CAS Commands. Read CAS issued in WMMDRAM RD_CAS and WR_CAS Commands. All DRAM WR_CAS (both Modes)WR_RMMDRAM RD_CAS and WR_CAS Commands. DRAM WR_CAS (w/ and w/out auto-pre) in Read Major ModeWR_WMMDRAM RD_CAS and WR_CAS Commands. DRAM WR_CAS (w/ and w/out auto-pre) in Write Major ModeHIGHNumber of DRAM Refreshes IssuedPANICISOCHCycles in a Major Mode -- Isoch Major ModePARTIALCycles in a Major Mode -- Partial Major ModeREADCycles in a Major Mode -- Read Major ModeWRITECycles in a Major Mode -- Write Major ModeRANK0Rank0 -- DIMM IDRANK1Rank1 -- DIMM IDRANK2Rank2 -- DIMM IDRANK3Rank3 -- DIMM IDRANK4Rank4 -- DIMM IDRANK5Rank5 -- DIMM IDRANK6Rank6 -- DIMM IDRANK7Rank7 -- DIMM IDRD_PREEMPT_RDRead Preemption Count -- Read over Read PreemptionRD_PREEMPT_WRRead Preemption Count -- Read over Write PreemptionDRAM Precharge commands. -- Precharge due to bypassPAGE_CLOSEDRAM Precharge commands. -- Precharge due to timer expirationPAGE_MISSDRAM Precharge commands. -- Precharges due to page missDRAM Precharge commands. -- Precharge due to readDRAM Precharge commands. -- Precharge due to writeRead CAS issued with HIGH priorityLOWRead CAS issued with LOW priorityMEDRead CAS issued with MEDIUM priorityRead CAS issued with PANIC NON ISOCH priority (starved)ALLBANKSAccess to Rank 0 -- All BanksBANK0Access to Rank 0 -- Bank 0BANK1Access to Rank 0 -- Bank 1BANK10Access to Rank 0 -- Bank 10BANK11Access to Rank 0 -- Bank 11BANK12Access to Rank 0 -- Bank 12BANK13Access to Rank 0 -- Bank 13BANK14Access to Rank 0 -- Bank 14BANK15Access to Rank 0 -- Bank 15BANK2Access to Rank 0 -- Bank 2BANK3Access to Rank 0 -- Bank 3BANK4Access to Rank 0 -- Bank 4BANK5Access to Rank 0 -- Bank 5BANK6Access to Rank 0 -- Bank 6BANK7Access to Rank 0 -- Bank 7BANK8Access to Rank 0 -- Bank 8BANK9Access to Rank 0 -- Bank 9BANKG0Access to Rank 0 -- Bank Group 0 (Banks 0-3)BANKG1Access to Rank 0 -- Bank Group 1 (Banks 4-7)BANKG2Access to Rank 0 -- Bank Group 2 (Banks 8-11)BANKG3Access to Rank 0 -- Bank Group 3 (Banks 12-15)RD_CAS Access to Rank 2 -- Bank 0RMMVMSE WR PUSH issued -- VMSE write PUSH issued in RMMWMMVMSE WR PUSH issued -- VMSE write PUSH issued in WMMLOW_THRESHTransition from WMM to RMM because of low threshold -- Transition from WMM to RMM because of starve counterSTARVETransition from WMM to RMM because of low threshold -- VMSE_RETRYUNC_M_CLOCKTICKSIMC Uncore clockticks (fixed counter)UNC_M_ACT_COUNTCounts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.UNC_M_BYP_CMDSTBDUNC_M_CAS_COUNTDRAM RD_CAS and WR_CAS CommandsUNC_M_DCLOCKTICKSUNC_M_DRAM_PRE_ALLCounts the number of times that the precharge all command was sent.UNC_M_DRAM_REFRESHCounts the number of refreshes issued.UNC_M_ECC_CORRECTABLE_ERRORSCounts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.UNC_M_MAJOR_MODESCounts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.UNC_M_POWER_CHANNEL_DLLOFFNumber of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.UNC_M_POWER_CHANNEL_PPDNumber of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.UNC_M_POWER_CKE_CYCLESNumber of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).UNC_M_POWER_CRITICAL_THROTTLE_CYCLESCounts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event.UNC_M_POWER_PCU_THROTTLINGUNC_M_POWER_SELF_REFRESHCounts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.UNC_M_POWER_THROTTLE_CYCLESCounts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.UNC_M_PREEMPTIONCounts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.UNC_M_PRE_COUNTCounts the number of DRAM Precharge commands sent on this channel.UNC_M_RD_CAS_PRIOUNC_M_RD_CAS_RANK0UNC_M_RD_CAS_RANK1UNC_M_RD_CAS_RANK2UNC_M_RD_CAS_RANK4UNC_M_RD_CAS_RANK5UNC_M_RD_CAS_RANK6UNC_M_RD_CAS_RANK7UNC_M_RPQ_CYCLES_NECounts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.UNC_M_RPQ_INSERTSCounts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.UNC_M_VMSE_MXB_WR_OCCUPANCYUNC_M_VMSE_WR_PUSHUNC_M_WMM_TO_RMMUNC_M_WPQ_CYCLES_FULLCounts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.UNC_M_WPQ_CYCLES_NECounts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencieies.UNC_M_WPQ_READ_HITCounts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.UNC_M_WPQ_WRITE_HITUNC_M_WRONG_MMUNC_M_WR_CAS_RANK0UNC_M_WR_CAS_RANK1UNC_M_WR_CAS_RANK4UNC_M_WR_CAS_RANK5UNC_M_WR_CAS_RANK6UNC_M_WR_CAS_RANK7Intel BroadwellX IMC0 uncorebdx_unc_imc0uncore_imc_0Intel BroadwellX IMC1 uncorebdx_unc_imc1uncore_imc_1Intel BroadwellX IMC2 uncorebdx_unc_imc2uncore_imc_2Intel BroadwellX IMC3 uncorebdx_unc_imc3uncore_imc_3Intel BroadwellX IMC4 uncorebdx_unc_imc4uncore_imc_4Intel BroadwellX IMC5 uncorebdx_unc_imc5uncore_imc_5Intel BroadwellX IMC6 uncorebdx_unc_imc6uncore_imc_6Intel BroadwellX IMC7 uncorebdx_unc_imc7uncore_imc_7ANYTotal Write Cache Occupancy -- Any SourceSOURCETotal Write Cache Occupancy -- Select SourceCLFLUSHCoherent Ops -- CLFlushCRDCoherent Ops -- CRdDRDCoherent Ops -- DRdPCIDCAHINTCoherent Ops -- PCIDCAHin5tPCIRDCURCoherent Ops -- PCIRdCurPCITOMCoherent Ops -- PCIItoMRFOCoherent Ops -- RFOWBMTOICoherent Ops -- WbMtoI2ND_ATOMIC_INSERTMisc Events - Set 0 -- Cache Inserts of Atomic Transactions as Secondary2ND_RD_INSERTMisc Events - Set 0 -- Cache Inserts of Read Transactions as Secondary2ND_WR_INSERTMisc Events - Set 0 -- Cache Inserts of Write Transactions as SecondaryFAST_REJMisc Events - Set 0 -- Fastpath RejectsFAST_REQMisc Events - Set 0 -- Fastpath RequestsFAST_XFERMisc Events - Set 0 -- Fastpath Transfers From Primary to SecondaryPF_ACK_HINTMisc Events - Set 0 -- Prefetch Ack Hints From Primary to SecondaryPF_TIMEOUTMisc Events - Set 0 -- Prefetch TimeOutDATA_THROTTLEMisc Events - Set 1 -- Data ThrottledLOST_FWDMisc Events - Set 1 -- SEC_RCVD_INVLDMisc Events - Set 1 -- Received InvalidSEC_RCVD_VLDMisc Events - Set 1 -- Received ValidSLOW_IMisc Events - Set 1 -- Slow Transfer of I LineSLOW_SMisc Events - Set 1 -- Slow Transfer of S LineSLOW_EMisc Events - Set 1 -- Slow Transfer of E LineSLOW_MMisc Events - Set 1 -- Slow Transfer of M LineHIT_ESSnoop Responses -- Hit E or SHIT_ISnoop Responses -- Hit IHIT_MSnoop Responses -- Hit MMISSSnoop Responses -- MissSNPCODESnoop Responses -- SnpCodeSNPDATASnoop Responses -- SnpDataSNPINVSnoop Responses -- SnpInvATOMICInbound Transaction Count -- AtomicORDERINGQInbound Transaction Count -- Select Source via IRP orderingQ registerOTHERInbound Transaction Count -- OtherRD_PREFInbound Transaction Count -- Read PrefetchesREADSInbound Transaction Count -- ReadsWRITESInbound Transaction Count -- WritesWR_PREFInbound Transaction Count -- Write PrefetchesUNC_I_CACHE_TOTAL_OCCUPANCYAccumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.UNC_I_CLOCKTICKSNumber of clocks in the IRP.UNC_I_COHERENT_OPSCounts the number of coherency related operations servied by the IRPUNC_I_MISC0TBDUNC_I_MISC1UNC_I_RXR_AK_INSERTSCounts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).UNC_I_RXR_BL_DRS_CYCLES_FULLCounts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.UNC_I_RXR_BL_DRS_INSERTSCounts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.UNC_I_RXR_BL_DRS_OCCUPANCYAccumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.UNC_I_RXR_BL_NCB_CYCLES_FULLUNC_I_RXR_BL_NCB_INSERTSUNC_I_RXR_BL_NCB_OCCUPANCYUNC_I_RXR_BL_NCS_CYCLES_FULLUNC_I_RXR_BL_NCS_INSERTSUNC_I_RXR_BL_NCS_OCCUPANCYUNC_I_SNOOP_RESPUNC_I_TRANSACTIONSCounts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portItID.UNC_I_TXR_AD_STALL_CREDIT_CYCLESCounts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.UNC_I_TXR_BL_STALL_CREDIT_CYCLESCounts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.UNC_I_TXR_DATA_INSERTS_NCBCounts the number of requests issued to the switch (towards the devices).UNC_I_TXR_DATA_INSERTS_NCSUNC_I_TXR_REQUEST_OCCUPANCYAccumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.[UNC_IRP=0x%lx event=0x%x umask=0x%x en=%d edge=%d thres=%d] %s Intel BroadwellX IRP uncorebdx_unc_irpuncore_irpCORES_C0Number of cores in C-State -- C0 and C1CORES_C3Number of cores in C-State -- C3CORES_C6Number of cores in C-State -- C6 and C7UNC_P_CLOCKTICKSThe PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controllers dclk, counts at a constant rate making it a good measure of actual wall timee.UNC_P_CORE0_TRANSITION_CYCLESNumber of cycles spent performing core C state transitions. There is one event per core.UNC_P_CORE10_TRANSITION_CYCLESUNC_P_CORE11_TRANSITION_CYCLESUNC_P_CORE12_TRANSITION_CYCLESUNC_P_CORE13_TRANSITION_CYCLESUNC_P_CORE14_TRANSITION_CYCLESUNC_P_CORE15_TRANSITION_CYCLESUNC_P_CORE16_TRANSITION_CYCLESUNC_P_CORE17_TRANSITION_CYCLESUNC_P_CORE1_TRANSITION_CYCLESUNC_P_CORE2_TRANSITION_CYCLESUNC_P_CORE3_TRANSITION_CYCLESUNC_P_CORE4_TRANSITION_CYCLESUNC_P_CORE5_TRANSITION_CYCLESUNC_P_CORE6_TRANSITION_CYCLESUNC_P_CORE7_TRANSITION_CYCLESUNC_P_CORE8_TRANSITION_CYCLESUNC_P_CORE9_TRANSITION_CYCLESUNC_P_DEMOTIONS_CORE0Counts the number of times when a configurable cores had a C-state demotionUNC_P_DEMOTIONS_CORE1UNC_P_DEMOTIONS_CORE10UNC_P_DEMOTIONS_CORE11UNC_P_DEMOTIONS_CORE12UNC_P_DEMOTIONS_CORE13UNC_P_DEMOTIONS_CORE14UNC_P_DEMOTIONS_CORE15UNC_P_DEMOTIONS_CORE16UNC_P_DEMOTIONS_CORE17UNC_P_DEMOTIONS_CORE2UNC_P_DEMOTIONS_CORE3UNC_P_DEMOTIONS_CORE4UNC_P_DEMOTIONS_CORE5UNC_P_DEMOTIONS_CORE6UNC_P_DEMOTIONS_CORE7UNC_P_DEMOTIONS_CORE8UNC_P_DEMOTIONS_CORE9UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLESCounts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.UNC_P_FREQ_MAX_OS_CYCLESCounts the number of cycles when the OS is the upper limit on frequency.UNC_P_FREQ_MAX_POWER_CYCLESCounts the number of cycles when power is the upper limit on frequency.UNC_P_FREQ_MIN_IO_P_CYCLESCounts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.UNC_P_FREQ_TRANS_CYCLESCounts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.UNC_P_MEMORY_PHASE_SHEDDING_CYCLESCounts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.UNC_P_POWER_STATE_OCCUPANCYThis is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.UNC_P_PROCHOT_EXTERNAL_CYCLESCounts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.UNC_P_PROCHOT_INTERNAL_CYCLESCounts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.UNC_P_TOTAL_TRANSITION_CYCLESNumber of cycles spent performing core C state transitions across all cores.UNC_P_UFS_BANDWIDTH_MAX_RANGETBDUNC_P_UFS_TRANSITIONS_DOWNRing GV down due to low trafficUNC_P_UFS_TRANSITIONS_IO_P_LIMITUNC_P_UFS_TRANSITIONS_NO_CHANGERing GV with same final and inital frequencyUNC_P_UFS_TRANSITIONS_UP_RINGRing GV up due to high ring trafficUNC_P_UFS_TRANSITIONS_UP_STALLRing GV up due to high core stallsUNC_P_VR_HOT_CYCLESUNC_P_FREQ_BAND0_CYCLESFrequency ResidencyUNC_P_FREQ_BAND1_CYCLESUNC_P_FREQ_BAND2_CYCLESUNC_P_FREQ_BAND3_CYCLESUNC_P_FIVR_PS_PS0_CYCLESCycles spent in phase-shedding power state 0UNC_P_FIVR_PS_PS1_CYCLESCycles spent in phase-shedding power state 1UNC_P_FIVR_PS_PS2_CYCLESCycles spent in phase-shedding power state 2UNC_P_FIVR_PS_PS3_CYCLESCycles spent in phase-shedding power state 3[UNC_PCU=0x%lx event=0x%x sel_ext=%d occ_sel=0x%x en=%d edge=%d thres=%d occ_inv=%d occ_edge=%d] %s [UNC_PCU_FILTER=0x%lx band0=%u band1=%u band2=%u band3=%u] Intel BroadwellX PCU uncorebdx_unc_pcuuncore_pcuFAILURE_CREDITSDirect 2 Core Spawning -- Spawn Failure - Egress CreditsFAILURE_CREDITS_MISSDirect 2 Core Spawning -- Spawn Failure - Egress and RBT MissFAILURE_CREDITS_RBTDirect 2 Core Spawning -- Spawn Failure - Egress and RBT InvalidFAILURE_CREDITS_RBT_MISSDirect 2 Core Spawning -- Spawn Failure - Egress and RBT Miss, InvalidFAILURE_MISSDirect 2 Core Spawning -- Spawn Failure - RBT MissFAILURE_RBT_HITDirect 2 Core Spawning -- Spawn Failure - RBT InvalidFAILURE_RBT_MISSDirect 2 Core Spawning -- Spawn Failure - RBT Miss and InvalidSUCCESS_RBT_HITDirect 2 Core Spawning -- Spawn SuccessDRSVN0 Credit Consumed -- DRSHOMVN0 Credit Consumed -- HOMNCBVN0 Credit Consumed -- NCBNCSVN0 Credit Consumed -- NCSNDRVN0 Credit Consumed -- NDRSNPVN0 Credit Consumed -- SNPFlits Received - Group 1 -- DRS Flits (both Header and Data)DRS_DATAFlits Received - Group 1 -- DRS Data FlitsDRS_NONDATAFlits Received - Group 1 -- DRS Header FlitsFlits Received - Group 1 -- HOM FlitsHOM_NONREQFlits Received - Group 1 -- HOM Non-Request FlitsHOM_REQFlits Received - Group 1 -- HOM Request FlitsFlits Received - Group 1 -- SNP FlitsFlits Received - Group 2 -- Non-Coherent Rx FlitsNCB_DATAFlits Received - Group 2 -- Non-Coherent data Rx FlitsNCB_NONDATAFlits Received - Group 2 -- Non-Coherent non-data Rx FlitsFlits Received - Group 2 -- Non-Coherent standard Rx FlitsNDR_ADFlits Received - Group 2 -- Non-Data Response Rx Flits - ADNDR_AKFlits Received - Group 2 -- Non-Data Response Rx Flits - AKVN0for VN0VN1for VN1IDLENumber of data flits over QPI that do not hold payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits acrossDATANumber of data flits over QPINON_DATANumber of non-NULL non-data flits over QPIFlits Transferred - Group 0 -- Data Tx FlitsFlits Transferred - Group 0 -- Non-Data protocol Tx FlitsFlits Transferred - Group 1 -- DRS Flits (both Header and Data)Flits Transferred - Group 1 -- DRS Data FlitsFlits Transferred - Group 1 -- DRS Header FlitsFlits Transferred - Group 1 -- HOM FlitsFlits Transferred - Group 1 -- HOM Non-Request FlitsFlits Transferred - Group 1 -- HOM Request FlitsFlits Transferred - Group 1 -- SNP FlitsFlits Transferred - Group 2 -- Non-Coherent Bypass Tx FlitsFlits Transferred - Group 2 -- Non-Coherent data Tx FlitsFlits Transferred - Group 2 -- Non-Coherent non-data Tx FlitsFlits Transferred - Group 2 -- Non-Coherent standard Tx FlitsFlits Transferred - Group 2 -- Non-Data Response Tx Flits - ADFlits Transferred - Group 2 -- Non-Data Response Tx Flits - AKR3QPI Egress Credit Occupancy - DRS -- for VN0R3QPI Egress Credit Occupancy - DRS -- for VN1VN_SHRR3QPI Egress Credit Occupancy - DRS -- for Shared VNUNC_Q_CLOCKTICKSCounts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. BDX does not support dynamic link speeds, so this frequency is fixexed.UNC_Q_CTO_COUNTCounts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.UNC_Q_DIRECT2CORECounts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.UNC_Q_L1_POWER_CYCLESNumber of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.UNC_Q_RXL0P_POWER_CYCLESNumber of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.UNC_Q_RXL0_POWER_CYCLESNumber of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.UNC_Q_RXL_BYPASSEDCounts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.UNC_Q_RXL_CREDITS_CONSUMED_VN0Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.UNC_Q_RXL_CREDITS_CONSUMED_VN1Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.UNC_Q_RXL_CREDITS_CONSUMED_VNACounts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.UNC_Q_RXL_CYCLES_NECounts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.UNC_Q_RXL_FLITS_G0Counts the number of flits received from the QPI Link.UNC_Q_RXL_FLITS_G1Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: datld therefore do: data flits * 8B / time.UNC_Q_RXL_FLITS_G2Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: datld therefore do: data flits * 8B / time.UNC_Q_RXL_INSERTSNumber of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.UNC_Q_RXL_INSERTS_DRSNumber of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.UNC_Q_RXL_INSERTS_HOMNumber of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.UNC_Q_RXL_INSERTS_NCBNumber of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.UNC_Q_RXL_INSERTS_NCSNumber of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.UNC_Q_RXL_INSERTS_NDRNumber of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.UNC_Q_RXL_INSERTS_SNPNumber of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.UNC_Q_RXL_OCCUPANCYAccumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.UNC_Q_RXL_OCCUPANCY_DRSAccumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.UNC_Q_RXL_OCCUPANCY_HOMAccumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.UNC_Q_RXL_OCCUPANCY_NCBAccumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.UNC_Q_RXL_OCCUPANCY_NCSAccumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.UNC_Q_RXL_OCCUPANCY_NDRAccumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.UNC_Q_RXL_OCCUPANCY_SNPAccumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.UNC_Q_TXL0P_POWER_CYCLESUNC_Q_TXL0_POWER_CYCLESUNC_Q_TXL_BYPASSEDCounts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.UNC_Q_TXL_CYCLES_NECounts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.UNC_Q_TXL_FLITS_G0Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instfor L0) or 4B instead of 8B for L0p.UNC_Q_TXL_FLITS_G1UNC_Q_TXL_FLITS_G2Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: datld therefore do: data flits * 8B / time.UNC_Q_TXL_INSERTSNumber of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.UNC_Q_TXL_OCCUPANCYAccumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.UNC_Q_TXR_AD_HOM_CREDIT_ACQUIREDNumber of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.UNC_Q_TXR_AD_HOM_CREDIT_OCCUPANCYOccupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.UNC_Q_TXR_AD_NDR_CREDIT_ACQUIREDNumber of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.UNC_Q_TXR_AD_NDR_CREDIT_OCCUPANCYOccupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.UNC_Q_TXR_AD_SNP_CREDIT_ACQUIREDNumber of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.UNC_Q_TXR_AD_SNP_CREDIT_OCCUPANCYOccupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO fro Snoop messages on AD.UNC_Q_TXR_AK_NDR_CREDIT_ACQUIREDNumber of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.UNC_Q_TXR_AK_NDR_CREDIT_OCCUPANCYOccupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.UNC_Q_TXR_BL_DRS_CREDIT_ACQUIREDNumber of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.UNC_Q_TXR_BL_DRS_CREDIT_OCCUPANCYOccupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.UNC_Q_TXR_BL_NCB_CREDIT_ACQUIREDNumber of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.UNC_Q_TXR_BL_NCB_CREDIT_OCCUPANCYOccupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.UNC_Q_TXR_BL_NCS_CREDIT_ACQUIREDNumber of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.UNC_Q_TXR_BL_NCS_CREDIT_OCCUPANCYOccupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.UNC_Q_VNA_CREDIT_RETURNSNumber of VNA credits returned.UNC_Q_VNA_CREDIT_RETURN_OCCUPANCYNumber of VNA credits in the Rx side that are waitng to be returned back across the link.[UNC_QPI=0x%lx event=0x%x sel_ext=%d umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel BroadwellX QPI0 uncorebdx_unc_qpi0uncore_qpi_0Intel BroadwellX QPI1 uncorebdx_unc_qpi1uncore_qpi_1Intel BroadwellX QPI2 uncorebdx_unc_qpi2uncore_qpi_2ISOCH_QPI0TBDISOCH_QPI1PRQ_QPI0PRQ_QPI1CCWCounterclockwiseCCW_EVENCounterclockwise and EvenCCW_ODDCounterclockwise and OddCWClockwiseCW_EVENClockwise and EvenCW_ODDClockwise and OddDNAK Ingress Bounced -- DnUPAK Ingress Bounced -- UpANYAny directionsNCBNCSDRSIngress Occupancy Accumulator -- DRSADSBo0 Credits Acquired -- For AD RingBLSBo0 Credits Acquired -- For BL RingSBO0_ADStall on No Sbo Credits -- For SBo0, AD RingSBO0_BLStall on No Sbo Credits -- For SBo0, BL RingSBO1_ADStall on No Sbo Credits -- For SBo1, AD RingSBO1_BLStall on No Sbo Credits -- For SBo1, BL RingEgress Cycles Full -- ADAKEgress Cycles Full -- AKEgress Cycles Full -- BLEgress Cycles Not Empty -- ADEgress Cycles Not Empty -- AKEgress Cycles Not Empty -- BLDN_ADEgress CCW NACK -- AD CCWDN_AKEgress CCW NACK -- AK CCWDN_BLEgress CCW NACK -- BL CCWUP_ADUP_AKEgress CCW NACK -- BL CWUP_BLUNC_R2_CLOCKTICKSCounts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.UNC_R2_IIO_CREDITUNC_R2_RING_AD_USEDCounts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.UNC_R2_RING_AK_BOUNCESCounts the number of times when a request destined for the AK ingress bounced.UNC_R2_RING_AK_USEDCounts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.UNC_R2_RING_BL_USEDCounts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.UNC_R2_RING_IV_USEDCounts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.UNC_R2_RXR_CYCLES_NECounts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.UNC_R2_RXR_INSERTSCounts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.UNC_R2_RXR_OCCUPANCYAccumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.UNC_R2_SBO0_CREDITS_ACQUIREDNumber of Sbo 0 credits acquired in a given cycle, per ring.UNC_R2_STALL_NO_SBO_CREDITNumber of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.UNC_R2_TXR_CYCLES_FULLCounts the number of cycles when the R2PCIe Egress buffer is full.UNC_R2_TXR_CYCLES_NECounts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.UNC_R2_TXR_NACK_CW[UNC_R2PCIE=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel BroadwellX R2PCIe uncorebdx_unc_r2pcieuncore_r2pcieCBO10CBox AD Credits EmptyCBO11CBO12CBO13CBO14_16CBO8CBO9CBO_15_17CBO0CBO1CBO2CBO3CBO4CBO5CBO6CBO7HA0HA/R2 AD Credits EmptyHA1R2_NCBR2_NCSVN0_HOMVN0 HOM messagesVN0_NDRVN0 NDR messagesVN0_SNPVN0 SNP messagesVN1_HOMVN1 HOM messagesVN1_NDRVN1 NDR messagesVN1_SNPVN1 SNP messagesVNAVNA messagesQPIx BL Credits EmptyCCWCounterclockwiseCCW_EVENCounterclockwise and EvenCCW_ODDCounterclockwise and OddCWClockwiseCW_EVENClockwise and EvenCW_ODDClockwise and OddANYAnyAKHOMIngress Cycles Not Empty -- HOMNDRIngress Cycles Not Empty -- NDRSNPIngress Cycles Not Empty -- SNPDRSVN1 Ingress Cycles Not Empty -- DRSVN1 Ingress Cycles Not Empty -- HOMNCBVN1 Ingress Cycles Not Empty -- NCBNCSVN1 Ingress Cycles Not Empty -- NCSVN1 Ingress Cycles Not Empty -- NDRVN1 Ingress Cycles Not Empty -- SNPIngress Allocations -- DRSIngress Allocations -- HOMIngress Allocations -- NCBIngress Allocations -- NCSIngress Allocations -- NDRIngress Allocations -- SNPADSBo0 Credits Acquired -- For AD RingBLSBo0 Credits Acquired -- For BL RingSBo1 Credits Acquired -- For AD RingSBo1 Credits Acquired -- For BL RingSBO0_ADStall on No Sbo Credits -- For SBo0, AD RingSBO0_BLStall on No Sbo Credits -- For SBo0, BL RingSBO1_ADStall on No Sbo Credits -- For SBo1, AD RingSBO1_BLStall on No Sbo Credits -- For SBo1, BL RingDN_ADEgress CCW NACK -- AD CCWDN_AKEgress CCW NACK -- AK CCWDN_BLEgress CCW NACK -- BL CCWUP_ADUP_AKEgress CCW NACK -- BL CWUP_BLVN0 Credit Acquisition Failed on DRS -- DRS Message ClassVN0 Credit Acquisition Failed on DRS -- HOM Message ClassVN0 Credit Acquisition Failed on DRS -- NCB Message ClassVN0 Credit Acquisition Failed on DRS -- NCS Message ClassVN0 Credit Acquisition Failed on DRS -- NDR Message ClassVN0 Credit Acquisition Failed on DRS -- SNP Message ClassVN0 Credit Used -- DRS Message ClassVN0 Credit Used -- HOM Message ClassVN0 Credit Used -- NCB Message ClassVN0 Credit Used -- NCS Message ClassVN0 Credit Used -- NDR Message ClassVN0 Credit Used -- SNP Message ClassVN1 Credit Acquisition Failed on DRS -- DRS Message ClassVN1 Credit Acquisition Failed on DRS -- HOM Message ClassVN1 Credit Acquisition Failed on DRS -- NCB Message ClassVN1 Credit Acquisition Failed on DRS -- NCS Message ClassVN1 Credit Acquisition Failed on DRS -- NDR Message ClassVN1 Credit Acquisition Failed on DRS -- SNP Message ClassVN1 Credit Used -- DRS Message ClassVN1 Credit Used -- HOM Message ClassVN1 Credit Used -- NCB Message ClassVN1 Credit Used -- NCS Message ClassVN1 Credit Used -- NDR Message ClassVN1 Credit Used -- SNP Message ClassVNA credit Acquisitions -- HOM Message ClassVNA Credit Reject -- DRS Message ClassVNA Credit Reject -- HOM Message ClassVNA Credit Reject -- NCB Message ClassVNA Credit Reject -- NCS Message ClassVNA Credit Reject -- NDR Message ClassVNA Credit Reject -- SNP Message ClassUNC_R3_CLOCKTICKSCounts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.UNC_R3_C_HI_AD_CREDITS_EMPTYNo credits available to send to Cbox on the AD Ring (covers higher CBoxes)UNC_R3_C_LO_AD_CREDITS_EMPTYNo credits available to send to Cbox on the AD Ring (covers lower CBoxes)UNC_R3_HA_R2_BL_CREDITS_EMPTYNo credits available to send to either HA or R2 on the BL RingUNC_R3_QPI0_AD_CREDITS_EMPTYNo credits available to send to QPI0 on the AD RingUNC_R3_QPI0_BL_CREDITS_EMPTYNo credits available to send to QPI0 on the BL RingUNC_R3_QPI1_AD_CREDITS_EMPTYNo credits available to send to QPI1 on the AD RingUNC_R3_QPI1_BL_CREDITS_EMPTYNo credits available to send to QPI1 on the BL RingUNC_R3_RING_AD_USEDCounts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.UNC_R3_RING_AK_USEDCounts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.UNC_R3_RING_BL_USEDCounts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.UNC_R3_RING_IV_USEDCounts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.UNC_R3_RING_SINK_STARVEDNumber of cycles the ringstop is in starvation (per ring)UNC_R3_RXR_CYCLES_NECounts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.UNC_R3_RXR_CYCLES_NE_VN1Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.UNC_R3_RXR_INSERTSCounts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.UNC_R3_RXR_INSERTS_VN1Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.UNC_R3_RXR_OCCUPANCY_VN1Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.UNC_R3_SBO0_CREDITS_ACQUIREDNumber of Sbo 0 credits acquired in a given cycle, per ring.UNC_R3_SBO1_CREDITS_ACQUIREDNumber of Sbo 1 credits acquired in a given cycle, per ring.UNC_R3_STALL_NO_SBO_CREDITNumber of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.UNC_R3_TXR_NACKTBDUNC_R3_VN0_CREDITS_REJECTNumber of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.UNC_R3_VN0_CREDITS_USEDNumber of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.UNC_R3_VN1_CREDITS_REJECTNumber of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.UNC_R3_VN1_CREDITS_USEDNumber of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.UNC_R3_VNA_CREDITS_ACQUIREDNumber of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event.UNC_R3_VNA_CREDITS_REJECTNumber of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.[UNC_R3QPI=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel BroadwellX R3QPI0 uncorebdx_unc_r3qpi0uncore_r3qpi_0Intel BroadwellX R3QPI1 uncorebdx_unc_r3qpi1uncore_r3qpi_1Intel BroadwellX R3QPI2 uncorebdx_unc_r3qpi2uncore_r3qpi_2TGR0CMS Agent0 AD Credits Acquired -- For Transgress 0TGR1CMS Agent0 AD Credits Acquired -- For Transgress 1TGR2CMS Agent0 AD Credits Acquired -- For Transgress 2TGR3CMS Agent0 AD Credits Acquired -- For Transgress 3TGR4CMS Agent0 AD Credits Acquired -- For Transgress 4TGR5CMS Agent0 AD Credits Acquired -- For Transgress 5CMS Agent0 AD Credits Occupancy -- For Transgress 0CMS Agent0 AD Credits Occupancy -- For Transgress 1CMS Agent0 AD Credits Occupancy -- For Transgress 2CMS Agent0 AD Credits Occupancy -- For Transgress 3CMS Agent0 AD Credits Occupancy -- For Transgress 4CMS Agent0 AD Credits Occupancy -- For Transgress 5CMS Agent0 BL Credits Acquired -- For Transgress 0CMS Agent0 BL Credits Acquired -- For Transgress 1CMS Agent0 BL Credits Acquired -- For Transgress 2CMS Agent0 BL Credits Acquired -- For Transgress 3CMS Agent0 BL Credits Acquired -- For Transgress 4CMS Agent0 BL Credits Acquired -- For Transgress 5CMS Agent0 BL Credits Occupancy -- For Transgress 0CMS Agent0 BL Credits Occupancy -- For Transgress 1CMS Agent0 BL Credits Occupancy -- For Transgress 2CMS Agent0 BL Credits Occupancy -- For Transgress 3CMS Agent0 BL Credits Occupancy -- For Transgress 4CMS Agent0 BL Credits Occupancy -- For Transgress 5CMS Agent1 AD Credits Acquired -- For Transgress 0CMS Agent1 AD Credits Acquired -- For Transgress 1CMS Agent1 AD Credits Acquired -- For Transgress 2CMS Agent1 AD Credits Acquired -- For Transgress 3CMS Agent1 AD Credits Acquired -- For Transgress 4CMS Agent1 AD Credits Acquired -- For Transgress 5CMS Agent1 AD Credits Occupancy -- For Transgress 0CMS Agent1 AD Credits Occupancy -- For Transgress 1CMS Agent1 AD Credits Occupancy -- For Transgress 2CMS Agent1 AD Credits Occupancy -- For Transgress 3CMS Agent1 AD Credits Occupancy -- For Transgress 4CMS Agent1 AD Credits Occupancy -- For Transgress 5CMS Agent1 BL Credits Occupancy -- For Transgress 0CMS Agent1 BL Credits Occupancy -- For Transgress 1CMS Agent1 BL Credits Occupancy -- For Transgress 2CMS Agent1 BL Credits Occupancy -- For Transgress 3CMS Agent1 BL Credits Occupancy -- For Transgress 4CMS Agent1 BL Credits Occupancy -- For Transgress 5CMS Agent1 BL Credits Acquired -- For Transgress 0CMS Agent1 BL Credits Acquired -- For Transgress 1CMS Agent1 BL Credits Acquired -- For Transgress 2CMS Agent1 BL Credits Acquired -- For Transgress 3CMS Agent1 BL Credits Acquired -- For Transgress 4CMS Agent1 BL Credits Acquired -- For Transgress 5INTERMEDIATECHA to iMC Bypass -- Intermediate bypass TakenNOT_TAKENCHA to iMC Bypass -- Not TakenTAKENCHA to iMC Bypass -- TakenC1_STATECore PMA Events -- C1 StateC1_TRANSITIONCore PMA Events -- C1 TransitionC6_STATECore PMA Events -- C6 StateC6_TRANSITIONCore PMA Events -- C6 TransitionGVCore PMA Events -- GVANY_GTONECore Cross Snoops Issued -- Any Cycle with Multiple SnoopsANY_ONECore Cross Snoops Issued -- Any Single SnoopANY_REMOTECore Cross Snoops Issued -- Any Snoop to Remote NodeCORE_GTONECore Cross Snoops Issued -- Multiple Core RequestsCORE_ONECore Cross Snoops Issued -- Single Core RequestsCORE_REMOTECore Cross Snoops Issued -- Core Request to Remote NodeEVICT_GTONECore Cross Snoops Issued -- Multiple EvictionEVICT_ONECore Cross Snoops Issued -- Single EvictionEVICT_REMOTECore Cross Snoops Issued -- Eviction to Remote NodeEXT_GTONECore Cross Snoops Issued -- Multiple External SnoopsEXT_ONECore Cross Snoops Issued -- Single External SnoopsEXT_REMOTECore Cross Snoops Issued -- External Snoop to Remote NodeNO_SNPDirectory Lookups -- Snoop Not NeededSNPDirectory Lookups -- Snoop NeededHADirectory Updates -- from HA pipeTORDirectory Updates -- from TOR pipeIV_SNOOPGO_DNEgress Blocking due to Ordering requirements -- DownIV_SNOOPGO_UPEgress Blocking due to Ordering requirements -- UpHORZFaST wire asserted -- HorizontalVERTFaST wire asserted -- VerticalEX_RDSCounts Number of Hits in HitMe Cache -- Exclusive hit and op is RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*SHARED_OWNREQCounts Number of Hits in HitMe Cache -- Shared hit and op is RdInvOwn, RdInv, Inv*WBMTOECounts Number of Hits in HitMe Cache -- op is WbMtoEWBMTOI_OR_SCounts Number of Hits in HitMe Cache -- op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoSREADCounts Number of times HitMe Cache is accessed -- op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*WRITECounts Number of times HitMe Cache is accessed -- op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoSNOTSHARED_RDINVOWNCounts Number of Misses in HitMe Cache -- No SF/LLC HitS/F and op is RdInvOwnREAD_OR_INVCounts Number of Misses in HitMe Cache -- op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*SHARED_RDINVOWNCounts Number of Misses in HitMe Cache -- SF/LLC HitS/F and op is RdInvOwnDEALLOCATECounts the number of Allocate/Update to HitMe Cache -- Deallocate HtiME Reads without RspFwdI*DEALLOCATE_RSPFWDI_LOCCounts the number of Allocate/Update to HitMe Cache -- op is RspIFwd or RspIFwdWb for a local requestRDINVOWNCounts the number of Allocate/Update to HitMe Cache -- Update HitMe Cache on RdInvOwn even if not RspFwdI*RSPFWDI_REMCounts the number of Allocate/Update to HitMe Cache -- op is RspIFwd or RspIFwdWb for a remote requestSHAREDCounts the number of Allocate/Update to HitMe Cache -- Update HitMe Cache to SHARedLEFT_EVENHorizontal AD Ring In Use -- Left and EvenLEFT_ODDHorizontal AD Ring In Use -- Left and OddRIGHT_EVENHorizontal AD Ring In Use -- Right and EvenRIGHT_ODDHorizontal AD Ring In Use -- Right and OddHorizontal AK Ring In Use -- Left and EvenHorizontal AK Ring In Use -- Left and OddHorizontal AK Ring In Use -- Right and EvenHorizontal AK Ring In Use -- Right and OddHorizontal BL Ring in Use -- Left and EvenHorizontal BL Ring in Use -- Left and OddHorizontal BL Ring in Use -- Right and EvenHorizontal BL Ring in Use -- Right and OddLEFTHorizontal IV Ring in Use -- LeftRIGHTHorizontal IV Ring in Use -- RightNORMALHA to iMC Reads Issued -- NormalPRIORITYHA to iMC Reads Issued -- ISOCHFULLWrites Issued to the iMC by the HA -- Full Line Non-ISOCHFULL_MIGWrites Issued to the iMC by the HA -- Full Line MIGFULL_PRIORITYWrites Issued to the iMC by the HA -- ISOCH Full LinePARTIALWrites Issued to the iMC by the HA -- Partial Non-ISOCHPARTIAL_MIGWrites Issued to the iMC by the HA -- Partial MIGPARTIAL_PRIORITYWrites Issued to the iMC by the HA -- ISOCH PartialINVITOMCounts Number of times IODC entry allocation is attempted -- Number of IODC allocationsIODCFULLCounts Number of times IODC entry allocation is attempted -- Number of IODC allocations dropped due to IODC FullOSBGATEDCounts Number of times IODC entry allocation is attempted -- Number of IDOC allocation dropped due to OSB gateALLCounts number of IODC deallocations -- IODC deallocated due to any reasonSNPOUTCounts number of IODC deallocations -- IODC deallocated due to conflicting transactionCounts number of IODC deallocations -- IODC deallocated due to WbMtoEWBMTOICounts number of IODC deallocations -- IODC deallocated due to WbMtoIWBPUSHMTOICounts number of IODC deallocations -- IODC deallocated due to WbPushMtoIANYCache and Snoop Filter Lookups -- Any RequestDATA_READCache and Snoop Filter Lookups -- Data Read RequestLOCALCache and Snoop Filter Lookups -- LocalREMOTECache and Snoop Filter Lookups -- RemoteREMOTE_SNOOPCache and Snoop Filter Lookups -- External Snoop RequestCache and Snoop Filter Lookups -- Write RequestsSTATE_LLC_ILLC Invalid cacheline stateSTATE_SF_SSF Shared cacheline stateSTATE_SF_ESF Exclusive cacheline stateSTATE_SF_HSF H cacheline stateSTATE_LLC_SLLC Shared cacheline stateSTATE_LLC_ELLC Exclusive cacheline stateSTATE_LLC_MLLC Modified cacheline stateSTATE_LLC_FLLC Forward cacheline stateSTATE_CACHE_ANYAny cache line stateLOCAL_ALLLines Victimized -- Local - All LinesLOCAL_ELines Victimized -- Local - Lines in E StateLOCAL_FLines Victimized -- Local - Lines in F StateLOCAL_MLines Victimized -- Local - Lines in M StateLOCAL_SLines Victimized -- Local - Lines in S StateREMOTE_ALLLines Victimized -- Remote - All LinesREMOTE_ELines Victimized -- Remote - Lines in E StateREMOTE_FLines Victimized -- Remote - Lines in F StateREMOTE_MLines Victimized -- Remote - Lines in M StateREMOTE_SLines Victimized -- Remote - Lines in S StateTOTAL_ELines Victimized -- Lines in E StateTOTAL_FLines Victimized -- Lines in F StateTOTAL_MLines Victimized -- Lines in M StateTOTAL_SLines Victimized -- Lines in S StateCV0_PREF_MISSCbo Misc -- CV0 Prefetch MissCV0_PREF_VICCbo Misc -- CV0 Prefetch VictimRFO_HIT_SCbo Misc -- RFO HitSRSPI_WAS_FSECbo Misc -- Silent Snoop EvictionWC_ALIASINGCbo Misc -- Write Combining AliasingEDC0_SMI2CHA iMC CHNx READ Credits Empty -- EDC0_SMI2EDC1_SMI3CHA iMC CHNx READ Credits Empty -- EDC1_SMI3EDC2_SMI4CHA iMC CHNx READ Credits Empty -- EDC2_SMI4EDC3_SMI5CHA iMC CHNx READ Credits Empty -- EDC3_SMI5MC0_SMI0CHA iMC CHNx READ Credits Empty -- MC0_SMI0MC1_SMI1CHA iMC CHNx READ Credits Empty -- MC1_SMI1INVITOE_LOCALRead and Write Requests -- InvalItoE LocalINVITOE_REMOTERead and Write Requests -- InvalItoE RemoteREADSRead and Write Requests -- ReadsREADS_LOCALRead and Write Requests -- Reads LocalREADS_REMOTERead and Write Requests -- Reads RemoteWRITESRead and Write Requests -- WritesWRITES_LOCALRead and Write Requests -- Writes LocalWRITES_REMOTERead and Write Requests -- Writes RemoteADMessages that bounced on the Horizontal Ring. -- ADAKMessages that bounced on the Horizontal Ring. -- AKBLMessages that bounced on the Horizontal Ring. -- BLIVMessages that bounced on the Horizontal Ring. -- IVMessages that bounced on the Vertical Ring. -- ADMessages that bounced on the Vertical Ring. -- Acknowledgements to coreMessages that bounced on the Vertical Ring. -- Data Responses to coreMessages that bounced on the Vertical Ring. -- Snoops of processors cachee.Sink Starvation on Horizontal Ring -- ADSink Starvation on Horizontal Ring -- AKAK_AG1Sink Starvation on Horizontal Ring -- Acknowledgements to Agent 1Sink Starvation on Horizontal Ring -- BLSink Starvation on Horizontal Ring -- IVSink Starvation on Vertical Ring -- ADSink Starvation on Vertical Ring -- Acknowledgements to coreSink Starvation on Vertical Ring -- Data Responses to coreSink Starvation on Vertical Ring -- Snoops of processors cachee.IPQIngress (from CMS) Allocations -- IPQIRQIngress (from CMS) Allocations -- IRQIRQ_REJIngress (from CMS) Allocations -- IRQ RejectedPRQIngress (from CMS) Allocations -- PRQPRQ_REJRRQIngress (from CMS) Allocations -- RRQWBQIngress (from CMS) Allocations -- WBQAD_REQ_VN0Ingress Probe Queue Rejects -- AD REQ on VN0AD_RSP_VN0Ingress Probe Queue Rejects -- AD RSP on VN0AK_NON_UPIIngress Probe Queue Rejects -- Non UPI AK RequestBL_NCB_VN0Ingress Probe Queue Rejects -- BL NCB on VN0BL_NCS_VN0Ingress Probe Queue Rejects -- BL NCS on VN0BL_RSP_VN0Ingress Probe Queue Rejects -- BL RSP on VN0BL_WB_VN0Ingress Probe Queue Rejects -- BL WB on VN0IV_NON_UPIIngress Probe Queue Rejects -- Non UPI IV RequestALLOW_SNPIngress Probe Queue Rejects -- Allow SnoopANY0Ingress Probe Queue Rejects -- ANY0Ingress Probe Queue Rejects -- HALLC_OR_SF_WAYIngress Probe Queue Rejects -- Merging these two together to make room for ANY_REJECT_*0LLC_VICTIMIngress Probe Queue Rejects -- LLC VictimPA_MATCHIngress Probe Queue Rejects -- PhyAddr MatchSF_VICTIMIngress Probe Queue Rejects -- SF VictimVICTIMIngress Probe Queue Rejects -- VictimIngress (from CMS) Request Queue Rejects -- AD REQ on VN0Ingress (from CMS) Request Queue Rejects -- AD RSP on VN0Ingress (from CMS) Request Queue Rejects -- Non UPI AK RequestIngress (from CMS) Request Queue Rejects -- BL NCB on VN0Ingress (from CMS) Request Queue Rejects -- BL NCS on VN0Ingress (from CMS) Request Queue Rejects -- BL RSP on VN0Ingress (from CMS) Request Queue Rejects -- BL WB on VN0Ingress (from CMS) Request Queue Rejects -- Non UPI IV RequestIngress (from CMS) Request Queue Rejects -- Allow SnoopIngress (from CMS) Request Queue Rejects -- ANY0Ingress (from CMS) Request Queue Rejects -- HAIngress (from CMS) Request Queue Rejects -- Merging these two together to make room for ANY_REJECT_*0Ingress (from CMS) Request Queue Rejects -- LLC VictimIngress (from CMS) Request Queue Rejects -- PhyAddr MatchIngress (from CMS) Request Queue Rejects -- SF VictimIngress (from CMS) Request Queue Rejects -- VictimISMQ Rejects -- AD REQ on VN0ISMQ Rejects -- AD RSP on VN0ISMQ Rejects -- Non UPI AK RequestISMQ Rejects -- BL NCB on VN0ISMQ Rejects -- BL NCS on VN0ISMQ Rejects -- BL RSP on VN0ISMQ Rejects -- BL WB on VN0ISMQ Rejects -- Non UPI IV RequestISMQ Retries -- AD REQ on VN0ISMQ Retries -- AD RSP on VN0ISMQ Retries -- Non UPI AK RequestISMQ Retries -- BL NCB on VN0ISMQ Retries -- BL NCS on VN0ISMQ Retries -- BL RSP on VN0ISMQ Retries -- BL WB on VN0ISMQ Retries -- Non UPI IV RequestISMQ Rejects -- ANY0ISMQ Rejects -- HAISMQ Retries -- ANY0ISMQ Retries -- HAIngress (from CMS) Occupancy -- IPQIngress (from CMS) Occupancy -- IRQIngress (from CMS) Occupancy -- RRQIngress (from CMS) Occupancy -- WBQOther Retries -- AD REQ on VN0Other Retries -- AD RSP on VN0Other Retries -- Non UPI AK RequestOther Retries -- BL NCB on VN0Other Retries -- BL NCS on VN0Other Retries -- BL RSP on VN0Other Retries -- BL WB on VN0Other Retries -- Non UPI IV RequestOther Retries -- Allow SnoopOther Retries -- ANY0Other Retries -- HAOther Retries -- Merging these two together to make room for ANY_REJECT_*0Other Retries -- LLC VictimOther Retries -- PhyAddr MatchOther Retries -- SF VictimOther Retries -- VictimIngress (from CMS) Request Queue Rejects -- LLC OR SF WayRequest Queue Retries -- AD REQ on VN0Request Queue Retries -- AD RSP on VN0Request Queue Retries -- Non UPI AK RequestRequest Queue Retries -- BL NCB on VN0Request Queue Retries -- BL NCS on VN0Request Queue Retries -- BL RSP on VN0Request Queue Retries -- BL WB on VN0Request Queue Retries -- Non UPI IV RequestRequest Queue Retries -- Allow SnoopRequest Queue Retries -- ANY0Request Queue Retries -- HARequest Queue Retries -- Merging these two together to make room for ANY_REJECT_*0Request Queue Retries -- LLC VictimRequest Queue Retries -- PhyAddr MatchRequest Queue Retries -- SF VictimRequest Queue Retries -- VictimRRQ Rejects -- AD REQ on VN0RRQ Rejects -- AD RSP on VN0RRQ Rejects -- Non UPI AK RequestRRQ Rejects -- BL NCB on VN0RRQ Rejects -- BL NCS on VN0RRQ Rejects -- BL RSP on VN0RRQ Rejects -- BL WB on VN0RRQ Rejects -- Non UPI IV RequestRRQ Rejects -- Allow SnoopRRQ Rejects -- ANY0RRQ Rejects -- HARRQ Rejects -- Merging these two together to make room for ANY_REJECT_*0RRQ Rejects -- LLC VictimRRQ Rejects -- PhyAddr MatchRRQ Rejects -- SF VictimRRQ Rejects -- VictimWBQ Rejects -- AD REQ on VN0WBQ Rejects -- AD RSP on VN0WBQ Rejects -- Non UPI AK RequestWBQ Rejects -- BL NCB on VN0WBQ Rejects -- BL NCS on VN0WBQ Rejects -- BL RSP on VN0WBQ Rejects -- BL WB on VN0WBQ Rejects -- Non UPI IV RequestWBQ Rejects -- Allow SnoopWBQ Rejects -- ANY0WBQ Rejects -- HAWBQ Rejects -- Merging these two together to make room for ANY_REJECT_*0WBQ Rejects -- LLC VictimWBQ Rejects -- PhyAddr MatchWBQ Rejects -- SF VictimWBQ Rejects -- VictimAD_BNCTransgress Injection Starvation -- AD - BounceAD_CRDTransgress Injection Starvation -- AD - CreditBL_BNCTransgress Injection Starvation -- BL - BounceBL_CRDTransgress Injection Starvation -- BL - CreditTransgress Ingress Bypass -- AD - BounceTransgress Ingress Bypass -- AD - CreditAK_BNCTransgress Ingress Bypass -- AK - BounceTransgress Ingress Bypass -- BL - BounceTransgress Ingress Bypass -- BL - CreditIV_BNCTransgress Ingress Bypass -- IV - BounceTransgress Injection Starvation -- AK - BounceIFVTransgress Injection Starvation -- IFV - CreditTransgress Injection Starvation -- IV - BounceTransgress Ingress Allocations -- AD - BounceTransgress Ingress Allocations -- AD - CreditTransgress Ingress Allocations -- AK - BounceTransgress Ingress Allocations -- BL - BounceTransgress Ingress Allocations -- BL - CreditTransgress Ingress Allocations -- IV - BounceTransgress Ingress Occupancy -- AD - BounceTransgress Ingress Occupancy -- AD - CreditTransgress Ingress Occupancy -- AK - BounceTransgress Ingress Occupancy -- BL - BounceTransgress Ingress Occupancy -- BL - CreditTransgress Ingress Occupancy -- IV - BounceE_STATESnoop Filter Eviction -- E stateM_STATESnoop Filter Eviction -- M stateS_STATESnoop Filter Eviction -- S stateSnoops Sent -- AllBCST_LOCALSnoops Sent -- Broadcast snoop for Local RequestsBCST_REMOTESnoops Sent -- Broadcast snoops for Remote RequestsDIRECT_LOCALSnoops Sent -- Directed snoops for Local RequestsDIRECT_REMOTESnoops Sent -- Directed snoops for Remote RequestsSnoops Sent -- Broadcast or directed Snoops sent for Local RequestsSnoops Sent -- Broadcast or directed Snoops sent for Remote RequestsRSPCNFLCTSSnoop Responses Received -- RSPCNFLCT*RSPFWDSnoop Responses Received -- RspFwdRSPISnoop Responses Received -- RspIRSPIFWDSnoop Responses Received -- RspIFwdRSPSSnoop Responses Received -- RspSRSPSFWDSnoop Responses Received -- RspSFwdRSP_FWD_WBSnoop Responses Received -- Rsp*Fwd*WBRSP_WBWBSnoop Responses Received -- Rsp*WBSnoop Responses Received Local -- RspFwdSnoop Responses Received Local -- RspISnoop Responses Received Local -- RspIFwdSnoop Responses Received Local -- RspSSnoop Responses Received Local -- RspSFwdSnoop Responses Received Local -- Rsp*FWD*WBRSP_WBSnoop Responses Received Local -- Rsp*WBStall on No AD Agent0 Transgress Credits -- For Transgress 0Stall on No AD Agent0 Transgress Credits -- For Transgress 1Stall on No AD Agent0 Transgress Credits -- For Transgress 2Stall on No AD Agent0 Transgress Credits -- For Transgress 3Stall on No AD Agent0 Transgress Credits -- For Transgress 4Stall on No AD Agent0 Transgress Credits -- For Transgress 5Stall on No AD Agent1 Transgress Credits -- For Transgress 0Stall on No AD Agent1 Transgress Credits -- For Transgress 1Stall on No AD Agent1 Transgress Credits -- For Transgress 2Stall on No AD Agent1 Transgress Credits -- For Transgress 3Stall on No AD Agent1 Transgress Credits -- For Transgress 4Stall on No AD Agent1 Transgress Credits -- For Transgress 5Stall on No BL Agent0 Transgress Credits -- For Transgress 0Stall on No BL Agent0 Transgress Credits -- For Transgress 1Stall on No BL Agent0 Transgress Credits -- For Transgress 2Stall on No BL Agent0 Transgress Credits -- For Transgress 3Stall on No BL Agent0 Transgress Credits -- For Transgress 4Stall on No BL Agent0 Transgress Credits -- For Transgress 5Stall on No BL Agent1 Transgress Credits -- For Transgress 0Stall on No BL Agent1 Transgress Credits -- For Transgress 1Stall on No BL Agent1 Transgress Credits -- For Transgress 2Stall on No BL Agent1 Transgress Credits -- For Transgress 3Stall on No BL Agent1 Transgress Credits -- For Transgress 4Stall on No BL Agent1 Transgress Credits -- For Transgress 5ALL_HITTOR Inserts -- Hits from LocalALL_IO_IATOR Inserts -- All from Local iA and IOALL_MISSTOR Inserts -- Misses from LocalEVICTTOR Inserts -- SF/LLC EvictionsHITTOR Inserts -- Hit (Not a Miss)IATOR Inserts -- All from Local iAIA_HITTOR Inserts -- Hits from Local iAIA_MISSTOR Inserts -- Misses from Local iAIOTOR Inserts -- All from Local IOIO_HITTOR Inserts -- Hits from Local IOIO_MISSTOR Inserts -- Misses from Local IOMISSTOR Inserts -- MissTOR Inserts -- IPQTOR Inserts -- IRQTOR Inserts -- PRQOPC0_SNP_CURIPQ Opcode: Snoop request to get uncacheable 'sanpshot' of dataOPC0_SNP_CODEIPQ Opcode: Snoop request to get cacheline intended to be cached in S-stateOPC0_SNP_DATAIPQ Opcode: Snoop request to get cacheline intended to be cached in E or S-stateOPC0_SNP_DATA_MIGIPQ Opcode: Snoop request to get cacheline intended to be cached in M, E or S-stateOPC0_SNP_INV_OWNIPQ Opcode: Snoop invalidate own. To get cacheline in M or E-stateOPC0_SNP_INVIPQ Opcode: Snoop invalidate. To get cacheline intended to be cached in E-stateOPC1_SNP_CUROPC1_SNP_CODEOPC1_SNP_DATAOPC1_SNP_DATA_MIGOPC1_SNP_INV_OWNOPC1_SNP_INVOPC0_RFOIRQ Opcode: Demand data RFO (line to be cache in E state)OPC0_CRDIRQ Opcode: Demand code readOPC0_DRDIRQ Opcode: Demand data read (line to be cached in S or E states)OPC0_PRDIRQ Opcode: Partial reads 0-32 bytes uncacheable (IIO can be up to 64 bytes)OPC0_WCILFIRQ Opcode: Full cacheline streaming storeOPC0_WCILIRQ Opcode: Partial streaming storeOPC0_UCRDFIRQ Opcode: Uncacheable Reads full cachelineOPC0_WILIRQ Opcode: Write Invalidate Line (Partial)OPC0_WB_PUSH_HINTIRQ Opcode: TBDOPC0_WB_MTOIIRQ Opcode: Request writeback modified invalidate line, evict fill M-state line from coreOPC0_WB_MTOEIRQ Opcode: Request writeback modified set to exclusive (combine with any OPCODE umask)OPC0_WB_EFTOIIRQ Opcode: Request clean E or F state lines writeback, ownership gone when writeback completesOPC0_WB_EFTOEIRQ Opcode: Request clean E or F state lines writeback, core may retain ownership when writeback completesOPC0_ITOMIRQ Opcode: Request invalidate line. Request exclusive ownership of the lineOPC0_LLC_PF_RFOIRQ Opcode: LLC prefetch RFO, uncore first looks up the line in LLC. For a hit, the LRU is updated. For a miss, the RFO is initiatedOPC0_LLC_PF_CODEIRQ Opcode: LLC prefetch code, uncore first looks up the line in LLC. For a hit, the LRU is updated. For a miss, the CRd is initiatedOPC0_LLC_PF_DATAIRQ Opcode: LLC prefetch data, uncore first looks up the line in LLC. For a hit, the LRU is updated. For a miss, the DRd is initiatedOPC0_INT_LOGIRQ Opcode: Interrupts logically addressedOPC0_INT_PHYIRQ Opcode: Interrupts physically addressedOPC0_PRI_UPIRQ Opcode: Interrupt priority updateOPC0_SPLIT_LOCKIRQ Opcode: Request to start split lock sequenceOPC0_LOCKIRQ Opcode: Request to start IDI lock sequenceOPC1_RFOOPC1_CRDOPC1_DRDOPC1_PRDOPC1_WCILFOPC1_WCILOPC1_UCRDFOPC1_WILOPC1_WB_PUSH_HINTOPC1_WB_MTOIOPC1_WB_MTOEOPC1_WB_EFTOIOPC1_WB_EFTOEOPC1_ITOMOPC1_LLC_PF_RFOOPC1_LLC_PF_CODEOPC1_LLC_PF_DATAOPC1_INT_LOGOPC1_INT_PHYOPC1_PRI_UPOPC1_SPLIT_LOCKOPC1_LOCKOPC0_RD_CURPRQ Opcode: Read current. Request cacheline in I-state. Used to obtain a coherent snapshot of an uncached lineOPC0_RD_CODEPRQ Opcode: Read code. Request cacheline in S-stateOPC0_RD_DATAPRQ Opcode: Read data. Request cacheline in E or S-stateOPC0_RD_DATA_MIGPRQ Opcode: Read data migratory. Request cacheline in E or S-state, except peer cache can forward cacheline in M-state without any writeback to memoryOPC0_RD_INV_OWNPRQ Opcode: Read invalidate own. Invalidate cacheline in M or E-stateOPC0_RD_INV_XTOIPRQ Opcode: Read invalidate X to I-stateOPC0_RD_PUSH_HINTPRQ Opcode: Read push hintOPC0_RD_INV_ITOEPRQ Opcode: Read invalidate I to E-stateOPC0_RD_INVPRQ Opcode: Read invalidate. Request cacheline in E-state from home agentOPC0_RD_INV_ITOMPRQ Opcode: Read invalidate I to M-stateOPC1_RD_CUROPC1_RD_CODEOPC1_RD_DATAOPC1_RD_DATA_MIGOPC1_RD_INV_OWNOPC1_RD_INV_XTOIOPC1_RD_PUSH_HINTOPC1_RD_INV_ITOEOPC1_RD_INVOPC1_RD_INV_ITOMTOR Occupancy -- All from LocalTOR Occupancy -- Hits from LocalTOR Occupancy -- Misses from LocalTOR Occupancy -- SF/LLC EvictionsTOR Occupancy -- Hit (Not a Miss)TOR Occupancy -- All from Local iATOR Occupancy -- Hits from Local iATOR Occupancy -- Misses from Local iATOR Occupancy -- All from Local IOTOR Occupancy -- Hits from Local IOTOR Occupancy -- Misses from Local IOTOR Occupancy -- MissTOR Occupancy -- IPQTOR Occupancy -- IRQTOR Occupancy -- PRQCMS Horizontal ADS Used -- AD - BounceCMS Horizontal ADS Used -- AD - CreditCMS Horizontal ADS Used -- AK - BounceCMS Horizontal ADS Used -- BL - BounceCMS Horizontal ADS Used -- BL - CreditCMS Horizontal Bypass Used -- AD - BounceCMS Horizontal Bypass Used -- AD - CreditCMS Horizontal Bypass Used -- AK - BounceCMS Horizontal Bypass Used -- BL - BounceCMS Horizontal Bypass Used -- BL - CreditCMS Horizontal Bypass Used -- IV - BounceCycles CMS Horizontal Egress Queue is Full -- AD - BounceCycles CMS Horizontal Egress Queue is Full -- AD - CreditCycles CMS Horizontal Egress Queue is Full -- AK - BounceCycles CMS Horizontal Egress Queue is Full -- BL - BounceCycles CMS Horizontal Egress Queue is Full -- BL - CreditCycles CMS Horizontal Egress Queue is Full -- IV - BounceCycles CMS Horizontal Egress Queue is Not Empty -- AD - BounceCycles CMS Horizontal Egress Queue is Not Empty -- AD - CreditCycles CMS Horizontal Egress Queue is Not Empty -- AK - BounceCycles CMS Horizontal Egress Queue is Not Empty -- BL - BounceCycles CMS Horizontal Egress Queue is Not Empty -- BL - CreditCycles CMS Horizontal Egress Queue is Not Empty -- IV - BounceCMS Horizontal Egress Inserts -- AD - BounceCMS Horizontal Egress Inserts -- AD - CreditCMS Horizontal Egress Inserts -- AK - BounceCMS Horizontal Egress Inserts -- BL - BounceCMS Horizontal Egress Inserts -- BL - CreditCMS Horizontal Egress Inserts -- IV - BounceCMS Horizontal Egress NACKs -- AD - BounceCMS Horizontal Egress NACKs -- AD - CreditCMS Horizontal Egress NACKs -- AK - BounceCMS Horizontal Egress NACKs -- BL - BounceCMS Horizontal Egress NACKs -- BL - CreditCMS Horizontal Egress NACKs -- IV - BounceCMS Horizontal Egress Occupancy -- AD - BounceCMS Horizontal Egress Occupancy -- AD - CreditCMS Horizontal Egress Occupancy -- AK - BounceCMS Horizontal Egress Occupancy -- BL - BounceCMS Horizontal Egress Occupancy -- BL - CreditCMS Horizontal Egress Occupancy -- IV - BounceCMS Horizontal Egress Injection Starvation -- AD - BounceCMS Horizontal Egress Injection Starvation -- AK - BounceCMS Horizontal Egress Injection Starvation -- BL - BounceCMS Horizontal Egress Injection Starvation -- IV - BounceAD_AG0CMS Vertical ADS Used -- AD - Agent 0AD_AG1CMS Vertical ADS Used -- AD - Agent 1AK_AG0CMS Vertical ADS Used -- AK - Agent 0CMS Vertical ADS Used -- AK - Agent 1BL_AG0CMS Vertical ADS Used -- BL - Agent 0BL_AG1CMS Vertical ADS Used -- BL - Agent 1CMS Vertical ADS Used -- IVCycles CMS Vertical Egress Queue Is Full -- AD - Agent 0Cycles CMS Vertical Egress Queue Is Full -- AD - Agent 1Cycles CMS Vertical Egress Queue Is Full -- AK - Agent 0Cycles CMS Vertical Egress Queue Is Full -- AK - Agent 1Cycles CMS Vertical Egress Queue Is Full -- BL - Agent 0Cycles CMS Vertical Egress Queue Is Full -- BL - Agent 1Cycles CMS Vertical Egress Queue Is Full -- IVCycles CMS Vertical Egress Queue Is Not Empty -- AD - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- AD - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- AK - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- AK - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- BL - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- BL - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- IVCMS Vert Egress Allocations -- AD - Agent 0CMS Vert Egress Allocations -- AD - Agent 1CMS Vert Egress Allocations -- AK - Agent 0CMS Vert Egress Allocations -- AK - Agent 1CMS Vert Egress Allocations -- BL - Agent 0CMS Vert Egress Allocations -- BL - Agent 1CMS Vert Egress Allocations -- IVCMS Vertical Egress NACKs -- AD - Agent 0CMS Vertical Egress NACKs -- AD - Agent 1CMS Vertical Egress NACKs -- AK - Agent 0CMS Vertical Egress NACKs -- AK - Agent 1CMS Vertical Egress NACKs -- BL - Agent 0CMS Vertical Egress NACKs -- BL - Agent 1CMS Vertical Egress NACKs -- IVCMS Vert Egress Occupancy -- AD - Agent 0CMS Vert Egress Occupancy -- AD - Agent 1CMS Vert Egress Occupancy -- AK - Agent 0CMS Vert Egress Occupancy -- AK - Agent 1CMS Vert Egress Occupancy -- BL - Agent 0CMS Vert Egress Occupancy -- BL - Agent 1CMS Vert Egress Occupancy -- IVCMS Vertical Egress Injection Starvation -- AD - Agent 0CMS Vertical Egress Injection Starvation -- AD - Agent 1CMS Vertical Egress Injection Starvation -- AK - Agent 0CMS Vertical Egress Injection Starvation -- AK - Agent 1CMS Vertical Egress Injection Starvation -- BL - Agent 0CMS Vertical Egress Injection Starvation -- BL - Agent 1CMS Vertical Egress Injection Starvation -- IVDN_EVENVertical AD Ring In Use -- Down and EvenDN_ODDVertical AD Ring In Use -- Down and OddUP_EVENVertical AD Ring In Use -- Up and EvenUP_ODDVertical AD Ring In Use -- Up and OddVertical AK Ring In Use -- Down and EvenVertical AK Ring In Use -- Down and OddVertical AK Ring In Use -- Up and EvenVertical AK Ring In Use -- Up and OddVertical BL Ring in Use -- Down and EvenVertical BL Ring in Use -- Down and OddVertical BL Ring in Use -- Up and EvenVertical BL Ring in Use -- Up and OddDNVertical IV Ring in Use -- DownUPVertical IV Ring in Use -- UpLLCWbPushMtoI -- Pushed to LLCMEMWbPushMtoI -- Pushed to MemoryCHA iMC CHNx WRITE Credits Empty -- EDC0_SMI2CHA iMC CHNx WRITE Credits Empty -- EDC1_SMI3CHA iMC CHNx WRITE Credits Empty -- EDC2_SMI4CHA iMC CHNx WRITE Credits Empty -- EDC3_SMI5CHA iMC CHNx WRITE Credits Empty -- MC0_SMI0CHA iMC CHNx WRITE Credits Empty -- MC1_SMI1ANY_RSPI_FWDFECore Cross Snoop Responses -- Any RspIFwdFEANY_RSPS_FWDFECore Cross Snoop Responses -- Any RspSFwdFEANY_RSPS_FWDMCore Cross Snoop Responses -- Any RspSFwdMANY_RSP_HITFSECore Cross Snoop Responses -- Any RspHitFSECORE_RSPI_FWDFECore Cross Snoop Responses -- Core RspIFwdFECORE_RSPI_FWDMCore Cross Snoop Responses -- Core RspIFwdMCORE_RSPS_FWDFECore Cross Snoop Responses -- Core RspSFwdFECORE_RSPS_FWDMCore Cross Snoop Responses -- Core RspSFwdMCORE_RSP_HITFSECore Cross Snoop Responses -- Core RspHitFSEEVICT_RSPI_FWDFECore Cross Snoop Responses -- Evict RspIFwdFEEVICT_RSPI_FWDMCore Cross Snoop Responses -- Evict RspIFwdMEVICT_RSPS_FWDFECore Cross Snoop Responses -- Evict RspSFwdFEEVICT_RSPS_FWDMCore Cross Snoop Responses -- Evict RspSFwdMEVICT_RSP_HITFSECore Cross Snoop Responses -- Evict RspHitFSEEXT_RSPI_FWDFECore Cross Snoop Responses -- External RspIFwdFEEXT_RSPI_FWDMCore Cross Snoop Responses -- External RspIFwdMEXT_RSPS_FWDFECore Cross Snoop Responses -- External RspSFwdFEEXT_RSPS_FWDMCore Cross Snoop Responses -- External RspSFwdMEXT_RSP_HITFSECore Cross Snoop Responses -- External RspHitFSEUNC_C_AG0_AD_CRD_ACQUIREDNumber of CMS Agent 0 AD credits acquired in a given cycle, per transgress.UNC_C_AG0_AD_CRD_OCCUPANCYNumber of CMS Agent 0 AD credits in use in a given cycle, per transgressUNC_C_AG0_BL_CRD_ACQUIREDNumber of CMS Agent 0 BL credits acquired in a given cycle, per transgress.UNC_C_AG0_BL_CRD_OCCUPANCYNumber of CMS Agent 0 BL credits in use in a given cycle, per transgressUNC_C_AG1_AD_CRD_ACQUIREDNumber of CMS Agent 1 AD credits acquired in a given cycle, per transgress.UNC_C_AG1_AD_CRD_OCCUPANCYNumber of CMS Agent 1 AD credits in use in a given cycle, per transgressUNC_C_AG1_BL_CRD_OCCUPANCYNumber of CMS Agent 1 BL credits in use in a given cycle, per transgressUNC_C_AG1_BL_CREDITS_ACQUIREDNumber of CMS Agent 1 BL credits acquired in a given cycle, per transgress.UNC_C_BYPASS_CHA_IMCCounts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.UNC_C_CLOCKTICKSTBDUNC_C_CMS_CLOCKTICKSUNC_C_CORE_PMAUNC_C_CORE_SNPCounts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).UNC_C_COUNTER0_OCCUPANCYSince occupancy counts can only be captured in the Cbos 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entryy.UNC_C_DIR_LOOKUPCounts the number of transactions that looked up the Home Agent directory. Can be filtered by requests that had to snoop and those that did not have to.UNC_C_DIR_UPDATECounts the number of directory updates that were required. These result in writes to the memory controller.UNC_C_EGRESS_ORDERINGCounts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirementsUNC_C_FAST_ASSERTEDCounts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.UNC_C_HITME_HITUNC_C_HITME_LOOKUPUNC_C_HITME_MISSUNC_C_HITME_UPDATEUNC_C_HORZ_RING_AD_IN_USECounts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_C_HORZ_RING_AK_IN_USECounts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_C_HORZ_RING_BL_IN_USECounts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_C_HORZ_RING_IV_IN_USECounts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.UNC_C_IMC_READS_COUNTCount of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.UNC_C_IMC_WRITES_COUNTCounts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.UNC_C_IODC_ALLOCUNC_C_IODC_DEALLOCUNC_C_LLC_LOOKUPCounts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.UNC_C_LLC_VICTIMSCounts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.UNC_C_MISCMiscellaneous events in the CHA.UNC_C_OSBCount of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.UNC_C_READ_NO_CREDITSCounts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMCs AD Ingress queuee.UNC_C_REQUESTSCounts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).UNC_C_RING_BOUNCES_HORZNumber of cycles incoming messages from the Horizontal ring that were bounced, by ring type.UNC_C_RING_BOUNCES_VERTNumber of cycles incoming messages from the Vertical ring that were bounced, by ring type.UNC_C_RING_SINK_STARVED_HORZUNC_C_RING_SINK_STARVED_VERTUNC_C_RING_SRC_THRTLUNC_C_RXC_INSERTSCounts number of allocations per cycle into the specified Ingress queue.UNC_C_RXC_IPQ0_REJECTUNC_C_RXC_IPQ1_REJECTUNC_C_RXC_IRQ0_REJECTUNC_C_RXC_IRQ1_REJECTUNC_C_RXC_ISMQ0_REJECTNumber of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.UNC_C_RXC_ISMQ0_RETRYUNC_C_RXC_ISMQ1_REJECTUNC_C_RXC_ISMQ1_RETRYUNC_C_RXC_OCCUPANCYCounts number of entries in the specified Ingress queue in each cycle.UNC_C_RXC_OTHER0_RETRYRetry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)UNC_C_RXC_OTHER1_RETRYUNC_C_RXC_PRQ0_REJECTUNC_C_RXC_PRQ1_REJECTUNC_C_RXC_REQ_Q0_RETRYREQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMSMQ)UNC_C_RXC_REQ_Q1_RETRYUNC_C_RXC_RRQ0_REJECTNumber of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.UNC_C_RXC_RRQ1_REJECTUNC_C_RXC_WBQ0_REJECTNumber of times a transaction flowing through the WBQ (Writeback Queue) had to retry.UNC_C_RXC_WBQ1_REJECTUNC_C_RXR_BUSY_STARVEDCounts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priorityUNC_C_RXR_BYPASSNumber of packets bypassing the CMS IngressUNC_C_RXR_CRD_STARVEDCounts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.UNC_C_RXR_INSERTSNumber of allocations into the CMS Ingress The Ingress is used to queue up requests received from the meshUNC_C_RXR_OCCUPANCYOccupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the meshUNC_C_SF_EVICTIONUNC_C_SNOOPS_SENTCounts the number of snoops issued by the HA.UNC_C_SNOOP_RESPCounts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.UNC_C_SNOOP_RESP_LOCALNumber of snoop responses received for a Local requestUNC_C_STALL_NO_TXR_HORZ_CRD_AD_AG0Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_C_STALL_NO_TXR_HORZ_CRD_AD_AG1Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_C_STALL_NO_TXR_HORZ_CRD_BL_AG0Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_C_STALL_NO_TXR_HORZ_CRD_BL_AG1Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_C_TOR_INSERTSCounts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.UNC_C_TOR_OCCUPANCYFor each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. TUNC_C_TXR_HORZ_ADS_USEDNumber of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.UNC_C_TXR_HORZ_BYPASSNumber of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.UNC_C_TXR_HORZ_CYCLES_FULLCycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_C_TXR_HORZ_CYCLES_NECycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_C_TXR_HORZ_INSERTSNumber of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_C_TXR_HORZ_NACKCounts number of Egress packets NACKed on to the Horizontal RinngUNC_C_TXR_HORZ_OCCUPANCYOccupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_C_TXR_HORZ_STARVEDCounts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.UNC_C_TXR_VERT_ADS_USEDNumber of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.UNC_C_TXR_VERT_BYPASSNumber of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.UNC_C_TXR_VERT_CYCLES_FULLNumber of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_C_TXR_VERT_CYCLES_NENumber of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_C_TXR_VERT_INSERTSNumber of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_C_TXR_VERT_NACKCounts number of Egress packets NACKed on to the Vertical RinngUNC_C_TXR_VERT_OCCUPANCYOccupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_C_TXR_VERT_STARVEDCounts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.UNC_C_VERT_RING_AD_IN_USECounts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_C_VERT_RING_AK_IN_USECounts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_C_VERT_RING_BL_IN_USECounts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_C_VERT_RING_IV_IN_USECounts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.UNC_C_WB_PUSH_MTOICounts the number of times when the CHA was received WbPushMtoIUNC_C_WRITE_NO_CREDITSCounts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMCs BL Ingress queuee.UNC_C_XSNP_RESPCounts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.[UNC_CHA=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d tid_en=%d] %s [UNC_CHA_FILTER0=0x%lx thread_id=%d source=0x%x state=0x%x state=0x%x] [UNC_CHA_FILTER1=0x%lx rem=%d loc=%d all_opc=%d nm=%d not_nm=%d opc0=0x%x opc1=0x%x nc=%d isoc=%d] Intel SkylakeX CHA0 uncoreskx_unc_cha0uncore_cha_0Intel SkylakeX CHA1 uncoreskx_unc_cha1uncore_cha_1Intel SkylakeX CHA2 uncoreskx_unc_cha2uncore_cha_2Intel SkylakeX CHA3 uncoreskx_unc_cha3uncore_cha_3Intel SkylakeX CHA4 uncoreskx_unc_cha4uncore_cha_4Intel SkylakeX CHA5 uncoreskx_unc_cha5uncore_cha_5Intel SkylakeX CHA6 uncoreskx_unc_cha6uncore_cha_6Intel SkylakeX CHA7 uncoreskx_unc_cha7uncore_cha_7Intel SkylakeX CHA8 uncoreskx_unc_cha8uncore_cha_8Intel SkylakeX CHA9 uncoreskx_unc_cha9uncore_cha_9Intel SkylakeX CHA10 uncoreskx_unc_cha10uncore_cha_10Intel SkylakeX CHA11 uncoreskx_unc_cha11uncore_cha_11Intel SkylakeX CHA12 uncoreskx_unc_cha12uncore_cha_12Intel SkylakeX CHA13 uncoreskx_unc_cha13uncore_cha_13Intel SkylakeX CHA14 uncoreskx_unc_cha14uncore_cha_14Intel SkylakeX CHA15 uncoreskx_unc_cha15uncore_cha_15Intel SkylakeX CHA16 uncoreskx_unc_cha16uncore_cha_16Intel SkylakeX CHA17 uncoreskx_unc_cha17uncore_cha_17Intel SkylakeX CHA18 uncoreskx_unc_cha18uncore_cha_18Intel SkylakeX CHA19 uncoreskx_unc_cha19uncore_cha_19Intel SkylakeX CHA20 uncoreskx_unc_cha20uncore_cha_20Intel SkylakeX CHA21 uncoreskx_unc_cha21uncore_cha_21Intel SkylakeX CHA22 uncoreskx_unc_cha22uncore_cha_22Intel SkylakeX CHA23 uncoreskx_unc_cha23uncore_cha_23Intel SkylakeX CHA24 uncoreskx_unc_cha24uncore_cha_24Intel SkylakeX CHA25 uncoreskx_unc_cha25uncore_cha_25Intel SkylakeX CHA26 uncoreskx_unc_cha26uncore_cha_26Intel SkylakeX CHA27 uncoreskx_unc_cha27uncore_cha_27PORT0PCIe Completion Buffer Inserts -- Port 0PORT1PCIe Completion Buffer Inserts -- Port 1PORT2PCIe Completion Buffer Inserts -- Port 2PORT3PCIe Completion Buffer Inserts -- Port 3ANY_PORTPCIe Completion Buffer Inserts -- Any portPORT0:PORT1:PORT2:PORT3FC_POSTED_REQPosted requestsFC_NON_POSTED_REQNon-Posted requestsFC_CMPLCompletion requestsFC_ANYAny type of requestsFC_POSTED_REQ:FC_NON_POSTED_REQ:FC_CMPLCFG_READ_PART0Data requested by the CPU -- Core reading from Cards PCICFG spacceCFG_READ_PART1CFG_READ_PART2CFG_READ_PART3CFG_READ_VTD0CFG_READ_VTD1CFG_WRITE_PART0Data requested by the CPU -- Core writing to Cards PCICFG spacceCFG_WRITE_PART1CFG_WRITE_PART2CFG_WRITE_PART3CFG_WRITE_VTD0CFG_WRITE_VTD1IO_READ_PART0Data requested by the CPU -- Core reading from Cards IO spacceIO_READ_PART1IO_READ_PART2IO_READ_PART3IO_READ_VTD0IO_READ_VTD1IO_WRITE_PART0Data requested by the CPU -- Core writing to Cards IO spacceIO_WRITE_PART1IO_WRITE_PART2IO_WRITE_PART3IO_WRITE_VTD0IO_WRITE_VTD1MEM_READ_PART0Data requested by the CPU -- Core reading from Cards MMIO spacceMEM_READ_PART1MEM_READ_PART2MEM_READ_PART3MEM_READ_VTD0MEM_READ_VTD1MEM_READ_ANYData requested by the CPU -- Core reading from any sourceMEM_READ_PART0:MEM_READ_PART1:MEM_READ_PART2:MEM_READ_PART3:MEM_READ_VTD0:MEM_READ_VTD1MEM_WRITE_PART0Data requested by the CPU -- Core writing to Cards MMIO spacceMEM_WRITE_PART1MEM_WRITE_PART2MEM_WRITE_PART3MEM_WRITE_VTD0MEM_WRITE_VTD1MEM_WRITE_ANYData requested by the CPU -- Core writingMEM_WRITE_PART0:MEM_WRITE_PART1:MEM_WRITE_PART2:MEM_WRITE_PART3:MEM_WRITE_VTD0:MEM_WRITE_VTD1PEER_READ_PART0Another card (different IIO stack) reading from this card.PEER_READ_PART1PEER_READ_PART2PEER_READ_PART3PEER_READ_VTD0PEER_READ_VTD1PEER_READ_ANYPEER_READ_PART0:PEER_READ_PART1:PEER_READ_PART2:PEER_READ_PART3:PEER_READ_VTD0:PEER_READ_VTD1PEER_WRITE_PART0Another card (different IIO stack) writing to this card.PEER_WRITE_PART1PEER_WRITE_PART2PEER_WRITE_PART3PEER_WRITE_VTD0PEER_WRITE_VTD1PEER_WRITE_ANYPEER_WRITE_PART0:PEER_WRITE_PART1:PEER_WRITE_PART2:PEER_WRITE_PART3:PEER_WRITE_VTD0:PEER_WRITE_VTD1ATOMIC_PART0Data requested of the CPU -- Atomic requests targeting DRAMATOMIC_PART1ATOMIC_PART2ATOMIC_PART3ATOMIC_VTD0ATOMIC_VTD1ATOMICCMP_PART0Data requested of the CPU -- Completion of atomic requests targeting DRAMATOMICCMP_PART1ATOMICCMP_PART2ATOMICCMP_PART3Data requested of the CPU -- Card reading from DRAMData requested by the CPU -- Core reading from any DRAM sourceData requested of the CPU -- Card writing to DRAMMSG_PART0Data requested of the CPU -- MessagesMSG_PART1MSG_PART2MSG_PART3MSG_VTD0MSG_VTD1Data requested of the CPU -- Card reading from another Card (same or different stack)Data requested of the CPU -- Card writing to another Card (same or different stack)BUS0AND Mask/match for debug bus -- Non-PCIE busBUS0_BUS1AND Mask/match for debug bus -- Non-PCIE bus and PCIE busBUS0_NOT_BUS1AND Mask/match for debug bus -- Non-PCIE bus and !(PCIE bus)BUS1AND Mask/match for debug bus -- PCIE busNOT_BUS0_BUS1AND Mask/match for debug bus -- !(Non-PCIE bus) and PCIE busNOT_BUS0_NOT_BUS1AND Mask/match for debug bus -- OR Mask/match for debug bus -- Non-PCIE busOR Mask/match for debug bus -- Non-PCIE bus and PCIE busOR Mask/match for debug bus -- Non-PCIE bus and !(PCIE bus)OR Mask/match for debug bus -- PCIE busOR Mask/match for debug bus -- !(Non-PCIE bus) and PCIE busOR Mask/match for debug bus -- !(Non-PCIE bus) and !(PCIE bus)CTXT_MISSVTd Access -- context cache missL1_MISSVTd Access -- L1 missL2_MISSVTd Access -- L2 missL3_MISSVTd Access -- L3 missL4_PAGE_HITVTd Access -- Vtd hitTLB1_MISSVTd Access -- TLB missTLB_FULLVTd Access -- TLB is fullTLB_MISSUNC_IO_CLOCKTICKSIIO clockticksUNC_IO_COMP_BUF_INSERTSTBDUNC_IO_COMP_BUF_OCCUPANCYUNC_IO_DATA_REQ_BY_CPUNumber of double word (4 bytes) requests initiated by the main die to the attached device.UNC_IO_DATA_REQ_OF_CPUNumber of double word (4 bytes) requests the attached device made of the main die.UNC_IO_LINK_NUM_CORR_ERRUNC_IO_LINK_NUM_RETRIESUNC_IO_MASK_MATCHUNC_IO_MASK_MATCH_ANDAsserted if all bits specified by mask matchUNC_IO_MASK_MATCH_ORAsserted if any bits specified by mask matchUNC_IO_NOTHINGUNC_IO_SYMBOL_TIMESGen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nSUNC_IO_TXN_REQ_BY_CPUAlso known as Outbound. Number of requests, to the attached device, initiated by the main die.UNC_IO_TXN_REQ_OF_CPUAlso known as Inbound. Number of 64 byte cache line requests initiated by the attached device.UNC_IO_VTD_ACCESSUNC_IO_VTD_OCCUPANCY[UNC_IIO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d chmask=0x%x fcmsk=0x%x] %s Intel SkylakeX IIO0 uncoreskx_unc_iio0uncore_iio_0Intel SkylakeX IIO1 uncoreskx_unc_iio1uncore_iio_1Intel SkylakeX IIO2 uncoreskx_unc_iio2uncore_iio_2Intel SkylakeX IIO3 uncoreskx_unc_iio3uncore_iio_3Intel SkylakeX IIO4 uncoreskx_unc_iio4uncore_iio_4Intel SkylakeX IIO5 uncoreskx_unc_iio5uncore_iio_5BYPDRAM Activate Count -- Activate due to BypassRDDRAM Activate Count -- Activate due to ReadWRDRAM Activate Count -- Activate due to WriteACTACT command issued by 2 cycle bypassCASCAS command issued by 2 cycle bypassPREPRE command issued by 2 cycle bypassALLDRAM CAS (Column Address Strobe) Commands. -- All CASes issued.DRAM CAS (Column Address Strobe) Commands. -- All DRAM Reads (includes underfills)RD_ISOCHDRAM CAS (Column Address Strobe) Commands. -- Read CAS issued in Read ISOCH ModeRD_REGDRAM CAS (Column Address Strobe) Commands. -- All read CAS (w/ and w/out auto-pre)RD_RMMDRAM CAS (Column Address Strobe) Commands. -- Read CAS issued in RMMRD_UNDERFILLDRAM CAS (Column Address Strobe) Commands. -- Underfill Read IssuedRD_WMMDRAM CAS (Column Address Strobe) Commands. -- Read CAS issued in WMMDRAM CAS (Column Address Strobe) Commands. -- All DRAM WR_CAS (both Modes)WR_ISOCHDRAM CAS (Column Address Strobe) Commands. -- Read CAS issued in Write ISOCH ModeWR_RMMDRAM CAS (Column Address Strobe) Commands. -- DRAM WR_CAS (w/ and w/out auto-pre) in Read Major ModeWR_WMMDRAM CAS (Column Address Strobe) Commands. -- DRAM WR_CAS (w/ and w/out auto-pre) in Write Major ModeHIGHNumber of DRAM Refreshes Issued -- PANICISOCHCycles in a Major Mode -- Isoch Major ModePARTIALCycles in a Major Mode -- Partial Major ModeREADCycles in a Major Mode -- Read Major ModeWRITECycles in a Major Mode -- Write Major ModeRANK0Rank0 -- DIMM IDRANK1Rank1 -- DIMM IDRANK2Rank2 -- DIMM IDRANK3Rank3 -- DIMM IDRANK4Rank4 -- DIMM IDRANK5Rank5 -- DIMM IDRANK6Rank6 -- DIMM IDRANK7Rank7 -- DIMM IDRD_PREEMPT_RDRead Preemption Count -- Read over Read PreemptionRD_PREEMPT_WRRead Preemption Count -- Read over Write PreemptionDRAM Precharge commands. -- Precharge due to bypassPAGE_CLOSEDRAM Precharge commands. -- Precharge due to timer expirationPAGE_MISSDRAM Precharge commands. -- Precharges due to page missDRAM Precharge commands. -- Precharge due to readDRAM Precharge commands. -- Precharge due to write -- Read CAS issued with HIGH priorityLOW -- Read CAS issued with LOW priorityMED -- Read CAS issued with MEDIUM priority -- Read CAS issued with PANIC NON ISOCH priority (starved)ALLBANKSAccess to all banksBANK0Access to Bank 0BANK1Access to Bank 1BANK2Access to Bank 2BANK3Access to Bank 3BANK4Access to Bank 4BANK5Access to Bank 5BANK6Access to Bank 6BANK7Access to Bank 7BANK8Access to Bank 8BANK9Access to Bank 9BANK10Access to Bank 10BANK11Access to Bank 11BANK12Access to Bank 12BANK13Access to Bank 13BANK14Access to Bank 14BANK15Access to Bank 15BANKG0Access to Bank Group 0 (Banks 0-3)BANKG1Access to Bank Group 1 (Banks 4-7)BANKG2Access to Bank Group 2 (Banks 8-11)BANKG3Access to Bank Group 3 (Banks 12-15)LOW_THRESHTransition from WMM to RMM because of low threshold -- Transition from WMM to RMM because of starve counterSTARVETransition from WMM to RMM because of low threshold -- VMSE_RETRYUNC_M_ACT_COUNTCounts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.UNC_M_BYP_CMDSTBDUNC_M_CAS_COUNTUNC_M_DCLOCKTICKSDRAM Clock ticks, fixed counter. Counts at half the DDR speed. Speed never changesUNC_M_CLOCKTICKSDRAM Clock ticks, generic countersUNC_M_DRAM_PRE_ALLCounts the number of times that the precharge all command was sent.UNC_M_DRAM_REFRESHCounts the number of refreshes issued.UNC_M_ECC_CORRECTABLE_ERRORSCounts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.UNC_M_MAJOR_MODESCounts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.UNC_M_POWER_CHANNEL_DLLOFFNumber of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.UNC_M_POWER_CHANNEL_PPDNumber of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.UNC_M_POWER_CKE_CYCLESNumber of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).UNC_M_POWER_CRITICAL_THROTTLE_CYCLESCounts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event.UNC_M_POWER_PCU_THROTTLINGUNC_M_POWER_SELF_REFRESHCounts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.UNC_M_POWER_THROTTLE_CYCLESCounts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.UNC_M_PREEMPTIONCounts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.UNC_M_PRE_COUNTCounts the number of DRAM Precharge commands sent on this channel.UNC_M_RD_CAS_PRIOUNC_M_RD_CAS_RANK0Read Cass Access to RankUNC_M_RD_CAS_RANK1UNC_M_RD_CAS_RANK2UNC_M_RD_CAS_RANK3UNC_M_RD_CAS_RANK4UNC_M_RD_CAS_RANK5UNC_M_RD_CAS_RANK6UNC_M_RD_CAS_RANK7UNC_M_RPQ_CYCLES_FULLCounts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries.UNC_M_RPQ_CYCLES_NECounts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.UNC_M_RPQ_INSERTSCounts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.UNC_M_RPQ_OCCUPANCYAccumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.UNC_M_WMM_TO_RMMTransitions from WMM to RMM because of low thresholdUNC_M_WPQ_CYCLES_FULLCounts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.UNC_M_WPQ_CYCLES_NECounts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencieies.UNC_M_WPQ_INSERTSCounts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMiMC.UNC_M_WPQ_READ_HITCounts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.UNC_M_WPQ_WRITE_HITUNC_M_WRONG_MMNumber of times not getting the requested major modeUNC_M_WR_CAS_RANK0Write VAS to RankUNC_M_WR_CAS_RANK1UNC_M_WR_CAS_RANK2UNC_M_WR_CAS_RANK3UNC_M_WR_CAS_RANK4UNC_M_WR_CAS_RANK5UNC_M_WR_CAS_RANK6UNC_M_WR_CAS_RANK7Intel SkylakeX IMC0 uncoreskx_unc_imc0uncore_imc_0Intel SkylakeX IMC1 uncoreskx_unc_imc1uncore_imc_1Intel SkylakeX IMC2 uncoreskx_unc_imc2uncore_imc_2Intel SkylakeX IMC3 uncoreskx_unc_imc3uncore_imc_3Intel SkylakeX IMC4 uncoreskx_unc_imc4uncore_imc_4Intel SkylakeX IMC5 uncoreskx_unc_imc5uncore_imc_5ANYTotal Write Cache Occupancy -- Any SourceIV_QTotal Write Cache Occupancy -- SnoopsMEMTotal Write Cache Occupancy -- MemCLFLUSHCoherent Ops -- CLFlushCRDCoherent Ops -- CRdDRDCoherent Ops -- DRdPCIDCAHINTCoherent Ops -- PCIDCAHin5tPCIRDCURCoherent Ops -- PCIRdCurPCITOMCoherent Ops -- PCIItoMRFOCoherent Ops -- RFOWBMTOICoherent Ops -- WbMtoIINBOUND_INSERTS -- All Inserts Inbound (p2p + faf + cset)OUTBOUND_INSERTS -- All Inserts Outbound (BL, AK, Snoops)2ND_ATOMIC_INSERTMisc Events - Set 0 -- Cache Inserts of Atomic Transactions as Secondary2ND_RD_INSERTMisc Events - Set 0 -- Cache Inserts of Read Transactions as Secondary2ND_WR_INSERTMisc Events - Set 0 -- Cache Inserts of Write Transactions as SecondaryFAST_REJMisc Events - Set 0 -- Fastpath RejectsFAST_REQMisc Events - Set 0 -- Fastpath RequestsFAST_XFERMisc Events - Set 0 -- Fastpath Transfers From Primary to SecondaryPF_ACK_HINTMisc Events - Set 0 -- Prefetch Ack Hints From Primary to SecondaryUNKNOWNMisc Events - Set 0 -- LOST_FWDMisc Events - Set 1 -- Lost ForwardSEC_RCVD_INVLDMisc Events - Set 1 -- Received InvalidSEC_RCVD_VLDMisc Events - Set 1 -- Received ValidSLOW_EMisc Events - Set 1 -- Slow Transfer of E LineSLOW_IMisc Events - Set 1 -- Slow Transfer of I LineSLOW_MMisc Events - Set 1 -- Slow Transfer of M LineSLOW_SMisc Events - Set 1 -- Slow Transfer of S LineCMPLP2P Transactions -- P2P completionsLOCP2P Transactions -- match if local onlyLOC_AND_TGT_MATCHP2P Transactions -- match if local and target matchesMSGP2P Transactions -- P2P MessageRDP2P Transactions -- P2P readsREMP2P Transactions -- Match if remote onlyREM_AND_TGT_MATCHP2P Transactions -- match if remote and target matchesWRP2P Transactions -- P2P WritesHIT_ESSnoop Responses -- Hit E or SHIT_ISnoop Responses -- Hit IHIT_MSnoop Responses -- Hit MMISSSnoop Responses -- MissSNPCODESnoop Responses -- SnpCodeSNPDATASnoop Responses -- SnpDataSNPINVSnoop Responses -- SnpInvATOMICInbound Transaction Count -- AtomicOTHERInbound Transaction Count -- OtherRD_PREFInbound Transaction Count -- Read PrefetchesREADSInbound Transaction Count -- ReadsWRITESInbound Transaction Count -- WritesWR_PREFInbound Transaction Count -- Write PrefetchesUNC_I_CACHE_TOTAL_OCCUPANCYAccumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.UNC_I_CLOCKTICKSIRP ClocksUNC_I_COHERENT_OPSCounts the number of coherency related operations servied by the IRPUNC_I_FAF_FULLTBDUNC_I_FAF_INSERTSUNC_I_FAF_OCCUPANCYUNC_I_FAF_TRANSACTIONSUNC_I_IRP_ALLUNC_I_MISC0UNC_I_MISC1UNC_I_P2P_INSERTSP2P requests from the ITCUNC_I_P2P_OCCUPANCYP2P B & S Queue OccupancyUNC_I_P2P_TRANSACTIONSUNC_I_SNOOP_RESPUNC_I_TRANSACTIONSCounts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portItID.UNC_I_TXC_AK_INSERTSUNC_I_TXC_BL_DRS_CYCLES_FULLUNC_I_TXC_BL_DRS_INSERTSUNC_I_TXC_BL_DRS_OCCUPANCYUNC_I_TXC_BL_NCB_CYCLES_FULLUNC_I_TXC_BL_NCB_INSERTSUNC_I_TXC_BL_NCB_OCCUPANCYUNC_I_TXC_BL_NCS_CYCLES_FULLUNC_I_TXC_BL_NCS_INSERTSUNC_I_TXC_BL_NCS_OCCUPANCYUNC_I_TXR2_AD_STALL_CREDIT_CYCLESCounts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.UNC_I_TXR2_BL_STALL_CREDIT_CYCLESCounts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.UNC_I_TXS_DATA_INSERTS_NCBCounts the number of requests issued to the switch (towards the devices).UNC_I_TXS_DATA_INSERTS_NCSUNC_I_TXS_REQUEST_OCCUPANCYAccumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.[UNC_IRP=0x%lx event=0x%x umask=0x%x en=%d edge=%d thres=%d] %s Intel SkylakeX IRP uncoreskx_unc_irpuncore_irpTGR0CMS Agent0 Credits Acquired -- For Transgress 0TGR1CMS Agent0 Credits Acquired -- For Transgress 1TGR2CMS Agent0 Credits Acquired -- For Transgress 2TGR3CMS Agent0 Credits Acquired -- For Transgress 3TGR4CMS Agent0 Credits Acquired -- For Transgress 4TGR5CMS Agent0 Credits Acquired -- For Transgress 5CMS Agent0 Credits Occupancy -- For Transgress 0CMS Agent0 Credits Occupancy -- For Transgress 1CMS Agent0 Credits Occupancy -- For Transgress 2CMS Agent0 Credits Occupancy -- For Transgress 3CMS Agent0 Credits Occupancy -- For Transgress 4CMS Agent0 Credits Occupancy -- For Transgress 5NOT_TAKENM2M to iMC Bypass -- Not TakenTAKENM2M to iMC Bypass -- TakenCLEAN_ADirectory Hit -- On NonDirty Line in A StateCLEAN_IDirectory Hit -- On NonDirty Line in I StateCLEAN_PDirectory Hit -- On NonDirty Line in L StateCLEAN_SDirectory Hit -- On NonDirty Line in S StateDIRTY_ADirectory Hit -- On Dirty Line in A StateDIRTY_IDirectory Hit -- On Dirty Line in I StateDIRTY_PDirectory Hit -- On Dirty Line in L StateDIRTY_SDirectory Hit -- On Dirty Line in S StateANYDirectory Lookups -- Any stateSTATE_ADirectory Lookups -- A StateSTATE_IDirectory Lookups -- I StateSTATE_SDirectory Lookups -- S StateDirectory Miss -- On NonDirty Line in A StateDirectory Miss -- On NonDirty Line in I StateDirectory Miss -- On NonDirty Line in L StateDirectory Miss -- On NonDirty Line in S StateDirectory Miss -- On Dirty Line in A StateDirectory Miss -- On Dirty Line in I StateDirectory Miss -- On Dirty Line in L StateDirectory Miss -- On Dirty Line in S StateA2IDirectory Updates -- A2IA2SDirectory Updates -- A2SDirectory Updates -- AnyI2ADirectory Updates -- I2AI2SDirectory Updates -- I2SS2ADirectory Updates -- S2AS2IDirectory Updates -- S2IIV_SNOOPGO_DNEgress Blocking due to Ordering requirements -- DownIV_SNOOPGO_UPEgress Blocking due to Ordering requirements -- UpHORZFaST wire asserted -- HorizontalVERTFaST wire asserted -- VerticalLEFT_EVENHorizontal AD Ring In Use -- Left and EvenLEFT_ODDHorizontal AD Ring In Use -- Left and OddRIGHT_EVENHorizontal AD Ring In Use -- Right and EvenRIGHT_ODDHorizontal AD Ring In Use -- Right and OddHorizontal AK Ring In Use -- Left and EvenHorizontal AK Ring In Use -- Left and OddHorizontal AK Ring In Use -- Right and EvenHorizontal AK Ring In Use -- Right and OddHorizontal BL Ring in Use -- Left and EvenHorizontal BL Ring in Use -- Left and OddHorizontal BL Ring in Use -- Right and EvenHorizontal BL Ring in Use -- Right and OddLEFTHorizontal IV Ring in Use -- LeftRIGHTHorizontal IV Ring in Use -- RightALLM2M Reads Issued to iMC -- All, regardless of priority.FROM_TRANSGRESSISOCHM2M Reads Issued to iMC -- Critical PriorityNORMALM2M Reads Issued to iMC -- Normal PriorityM2M Writes Issued to iMC -- All WritesM2M Writes Issued to iMC -- All, regardless of priority.FULLM2M Writes Issued to iMC -- Full Line Non-ISOCHFULL_ISOCHM2M Writes Issued to iMC -- ISOCH Full LineNIPARTIALM2M Writes Issued to iMC -- Partial Non-ISOCHPARTIAL_ISOCHM2M Writes Issued to iMC -- ISOCH PartialMCNumber Packet Header Matches -- MC MatchMESHNumber Packet Header Matches -- Mesh MatchADMessages that bounced on the Horizontal Ring. -- ADAKMessages that bounced on the Horizontal Ring. -- AKBLMessages that bounced on the Horizontal Ring. -- BLIVMessages that bounced on the Horizontal Ring. -- IVMessages that bounced on the Vertical Ring. -- ADMessages that bounced on the Vertical Ring. -- Acknowledgements to coreMessages that bounced on the Vertical Ring. -- Data Responses to coreMessages that bounced on the Vertical Ring. -- Snoops of processors cachee.Sink Starvation on Horizontal Ring -- ADSink Starvation on Horizontal Ring -- AKAK_AG1Sink Starvation on Horizontal Ring -- Acknowledgements to Agent 1Sink Starvation on Horizontal Ring -- BLSink Starvation on Horizontal Ring -- IVSink Starvation on Vertical Ring -- ADSink Starvation on Vertical Ring -- Acknowledgements to coreSink Starvation on Vertical Ring -- Data Responses to coreSink Starvation on Vertical Ring -- Snoops of processors cachee.CHN0M2M to iMC RPQ Cycles w/Credits - Regular -- Channel 0CHN1M2M to iMC RPQ Cycles w/Credits - Regular -- Channel 1CHN2M2M to iMC RPQ Cycles w/Credits - Regular -- Channel 2M2M to iMC RPQ Cycles w/Credits - Special -- Channel 0M2M to iMC RPQ Cycles w/Credits - Special -- Channel 1M2M to iMC RPQ Cycles w/Credits - Special -- Channel 2AD_BNCTransgress Injection Starvation -- AD - BounceAD_CRDTransgress Injection Starvation -- AD - CreditBL_BNCTransgress Injection Starvation -- BL - BounceBL_CRDTransgress Injection Starvation -- BL - CreditTransgress Ingress Bypass -- AD - BounceTransgress Ingress Bypass -- AD - CreditAK_BNCTransgress Ingress Bypass -- AK - BounceTransgress Ingress Bypass -- BL - BounceTransgress Ingress Bypass -- BL - CreditIV_BNCTransgress Ingress Bypass -- IV - BounceTransgress Injection Starvation -- AK - BounceIFVTransgress Injection Starvation -- IFV - CreditTransgress Injection Starvation -- IV - BounceTransgress Ingress Allocations -- AD - BounceTransgress Ingress Allocations -- AD - CreditTransgress Ingress Allocations -- AK - BounceTransgress Ingress Allocations -- BL - BounceTransgress Ingress Allocations -- BL - CreditTransgress Ingress Allocations -- IV - BounceTransgress Ingress Occupancy -- AD - BounceTransgress Ingress Occupancy -- AD - CreditTransgress Ingress Occupancy -- AK - BounceTransgress Ingress Occupancy -- BL - BounceTransgress Ingress Occupancy -- BL - CreditTransgress Ingress Occupancy -- IV - BounceStall on No AD Agent0 Transgress Credits -- For Transgress 0Stall on No AD Agent0 Transgress Credits -- For Transgress 1Stall on No AD Agent0 Transgress Credits -- For Transgress 2Stall on No AD Agent0 Transgress Credits -- For Transgress 3Stall on No AD Agent0 Transgress Credits -- For Transgress 4Stall on No AD Agent0 Transgress Credits -- For Transgress 5Stall on No AD Agent1 Transgress Credits -- For Transgress 0Stall on No AD Agent1 Transgress Credits -- For Transgress 1Stall on No AD Agent1 Transgress Credits -- For Transgress 2Stall on No AD Agent1 Transgress Credits -- For Transgress 3Stall on No AD Agent1 Transgress Credits -- For Transgress 4Stall on No AD Agent1 Transgress Credits -- For Transgress 5Stall on No BL Agent0 Transgress Credits -- For Transgress 0Stall on No BL Agent0 Transgress Credits -- For Transgress 1Stall on No BL Agent0 Transgress Credits -- For Transgress 2Stall on No BL Agent0 Transgress Credits -- For Transgress 3Stall on No BL Agent0 Transgress Credits -- For Transgress 4Stall on No BL Agent0 Transgress Credits -- For Transgress 5Stall on No BL Agent1 Transgress Credits -- For Transgress 0Stall on No BL Agent1 Transgress Credits -- For Transgress 1Stall on No BL Agent1 Transgress Credits -- For Transgress 2Stall on No BL Agent1 Transgress Credits -- For Transgress 3Stall on No BL Agent1 Transgress Credits -- For Transgress 4Stall on No BL Agent1 Transgress Credits -- For Transgress 5CH0Tracker Cycles Full -- Channel 0CH1Tracker Cycles Full -- Channel 1CH2Tracker Cycles Full -- Channel 2Tracker Cycles Not Empty -- Channel 0Tracker Cycles Not Empty -- Channel 1Tracker Cycles Not Empty -- Channel 2Tracker Inserts -- Channel 0Tracker Inserts -- Channel 1Tracker Inserts -- Channel 2Tracker Occupancy -- Channel 0Tracker Occupancy -- Channel 1Tracker Occupancy -- Channel 2CRD_CBOOutbound Ring Transactions on AK -- CRD Transactions to CboNDROutbound Ring Transactions on AK -- NDR TransactionsCMS0AK Egress (to CMS) Credit Acquired -- Common Mesh Stop - Near SideCMS1AK Egress (to CMS) Credit Acquired -- Common Mesh Stop - Far SideAK Egress (to CMS) Credits Occupancy -- Common Mesh Stop - Near SideAK Egress (to CMS) Credits Occupancy -- Common Mesh Stop - Far SideAK Egress (to CMS) Full -- AllAK Egress (to CMS) Full -- Common Mesh Stop - Near SideAK Egress (to CMS) Full -- Common Mesh Stop - Far SideRDCRD0AK Egress (to CMS) Full -- Read Credit RequestRDCRD1WRCMP0AK Egress (to CMS) Full -- Write Compare RequestWRCMP1WRCRD0AK Egress (to CMS) Full -- Write Credit RequestWRCRD1AK Egress (to CMS) Not Empty -- AllAK Egress (to CMS) Not Empty -- Common Mesh Stop - Near SideAK Egress (to CMS) Not Empty -- Common Mesh Stop - Far SideRDCRDAK Egress (to CMS) Not Empty -- Read Credit RequestWRCMPAK Egress (to CMS) Not Empty -- Write Compare RequestWRCRDAK Egress (to CMS) Not Empty -- Write Credit RequestAK Egress (to CMS) Allocations -- AllAK Egress (to CMS) Allocations -- Common Mesh Stop - Near SideAK Egress (to CMS) Allocations -- Common Mesh Stop - Far SidePREF_RD_CAM_HITAK Egress (to CMS) Allocations -- Prefetch Read Cam HitAK Egress (to CMS) Allocations -- Read Credit RequestAK Egress (to CMS) Allocations -- Write Compare RequestAK Egress (to CMS) Allocations -- Write Credit RequestCycles with No AK Egress (to CMS) Credits -- Common Mesh Stop - Near SideCycles with No AK Egress (to CMS) Credits -- Common Mesh Stop - Far SideCycles Stalled with No AK Egress (to CMS) Credits -- Common Mesh Stop - Near SideCycles Stalled with No AK Egress (to CMS) Credits -- Common Mesh Stop - Far SideAK Egress (to CMS) Occupancy -- AllAK Egress (to CMS) Occupancy -- Common Mesh Stop - Near SideAK Egress (to CMS) Occupancy -- Common Mesh Stop - Far SideAK Egress (to CMS) Occupancy -- Read Credit RequestAK Egress (to CMS) Occupancy -- Write Compare RequestAK Egress (to CMS) Occupancy -- Write Credit RequestRDAK Egress (to CMS) Sideband -- WRDRS_CACHEOutbound DRS Ring Transactions to Cache -- Data to CacheDRS_COREOutbound DRS Ring Transactions to Cache -- Data to CoreDRS_UPIOutbound DRS Ring Transactions to Cache -- Data to QPIBL Egress (to CMS) Credit Acquired -- Common Mesh Stop - Near SideBL Egress (to CMS) Credit Acquired -- Common Mesh Stop - Far SideBL Egress (to CMS) Credits Occupancy -- Common Mesh Stop - Near SideBL Egress (to CMS) Credits Occupancy -- Common Mesh Stop - Far SideBL Egress (to CMS) Full -- AllBL Egress (to CMS) Full -- Common Mesh Stop - Near SideBL Egress (to CMS) Full -- Common Mesh Stop - Far SideBL Egress (to CMS) Not Empty -- AllBL Egress (to CMS) Not Empty -- Common Mesh Stop - Near SideBL Egress (to CMS) Not Empty -- Common Mesh Stop - Far SideBL Egress (to CMS) Allocations -- AllBL Egress (to CMS) Allocations -- Common Mesh Stop - Near SideBL Egress (to CMS) Allocations -- Common Mesh Stop - Far SideCycles with No BL Egress (to CMS) Credits -- Common Mesh Stop - Near SideCycles with No BL Egress (to CMS) Credits -- Common Mesh Stop - Far SideCycles Stalled with No BL Egress (to CMS) Credits -- Common Mesh Stop - Near SideCycles Stalled with No BL Egress (to CMS) Credits -- Common Mesh Stop - Far SideBL Egress (to CMS) Occupancy -- AllBL Egress (to CMS) Occupancy -- Common Mesh Stop - Near SideBL Egress (to CMS) Occupancy -- Common Mesh Stop - Far SideCMS Horizontal ADS Used -- AD - BounceCMS Horizontal ADS Used -- AD - CreditCMS Horizontal ADS Used -- AK - BounceCMS Horizontal ADS Used -- BL - BounceCMS Horizontal ADS Used -- BL - CreditCMS Horizontal Bypass Used -- AD - BounceCMS Horizontal Bypass Used -- AD - CreditCMS Horizontal Bypass Used -- AK - BounceCMS Horizontal Bypass Used -- BL - BounceCMS Horizontal Bypass Used -- BL - CreditCMS Horizontal Bypass Used -- IV - BounceCycles CMS Horizontal Egress Queue is Full -- AD - BounceCycles CMS Horizontal Egress Queue is Full -- AD - CreditCycles CMS Horizontal Egress Queue is Full -- AK - BounceCycles CMS Horizontal Egress Queue is Full -- BL - BounceCycles CMS Horizontal Egress Queue is Full -- BL - CreditCycles CMS Horizontal Egress Queue is Full -- IV - BounceCycles CMS Horizontal Egress Queue is Not Empty -- AD - BounceCycles CMS Horizontal Egress Queue is Not Empty -- AD - CreditCycles CMS Horizontal Egress Queue is Not Empty -- AK - BounceCycles CMS Horizontal Egress Queue is Not Empty -- BL - BounceCycles CMS Horizontal Egress Queue is Not Empty -- BL - CreditCycles CMS Horizontal Egress Queue is Not Empty -- IV - BounceCMS Horizontal Egress Inserts -- AD - BounceCMS Horizontal Egress Inserts -- AD - CreditCMS Horizontal Egress Inserts -- AK - BounceCMS Horizontal Egress Inserts -- BL - BounceCMS Horizontal Egress Inserts -- BL - CreditCMS Horizontal Egress Inserts -- IV - BounceCMS Horizontal Egress NACKs -- AD - BounceCMS Horizontal Egress NACKs -- AD - CreditCMS Horizontal Egress NACKs -- AK - BounceCMS Horizontal Egress NACKs -- BL - BounceCMS Horizontal Egress NACKs -- BL - CreditCMS Horizontal Egress NACKs -- IV - BounceCMS Horizontal Egress Occupancy -- AD - BounceCMS Horizontal Egress Occupancy -- AD - CreditCMS Horizontal Egress Occupancy -- AK - BounceCMS Horizontal Egress Occupancy -- BL - BounceCMS Horizontal Egress Occupancy -- BL - CreditCMS Horizontal Egress Occupancy -- IV - BounceCMS Horizontal Egress Injection Starvation -- AD - BounceCMS Horizontal Egress Injection Starvation -- AK - BounceCMS Horizontal Egress Injection Starvation -- BL - BounceCMS Horizontal Egress Injection Starvation -- IV - BounceAD_AG0CMS Vertical ADS Used -- AD - Agent 0AD_AG1CMS Vertical ADS Used -- AD - Agent 1AK_AG0CMS Vertical ADS Used -- AK - Agent 0CMS Vertical ADS Used -- AK - Agent 1BL_AG0CMS Vertical ADS Used -- BL - Agent 0BL_AG1CMS Vertical ADS Used -- BL - Agent 1CMS Vertical ADS Used -- IVCycles CMS Vertical Egress Queue Is Full -- AD - Agent 0Cycles CMS Vertical Egress Queue Is Full -- AD - Agent 1Cycles CMS Vertical Egress Queue Is Full -- AK - Agent 0Cycles CMS Vertical Egress Queue Is Full -- AK - Agent 1Cycles CMS Vertical Egress Queue Is Full -- BL - Agent 0Cycles CMS Vertical Egress Queue Is Full -- BL - Agent 1Cycles CMS Vertical Egress Queue Is Full -- IVCycles CMS Vertical Egress Queue Is Not Empty -- AD - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- AD - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- AK - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- AK - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- BL - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- BL - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- IVCMS Vert Egress Allocations -- AD - Agent 0CMS Vert Egress Allocations -- AD - Agent 1CMS Vert Egress Allocations -- AK - Agent 0CMS Vert Egress Allocations -- AK - Agent 1CMS Vert Egress Allocations -- BL - Agent 0CMS Vert Egress Allocations -- BL - Agent 1CMS Vert Egress Allocations -- IVCMS Vertical Egress NACKs -- AD - Agent 0CMS Vertical Egress NACKs -- AD - Agent 1CMS Vertical Egress NACKs -- AK - Agent 0CMS Vertical Egress NACKs -- AK - Agent 1CMS Vertical Egress NACKs -- BL - Agent 0CMS Vertical Egress NACKs -- BL - Agent 1CMS Vertical Egress NACKs -- IVCMS Vert Egress Occupancy -- AD - Agent 0CMS Vert Egress Occupancy -- AD - Agent 1CMS Vert Egress Occupancy -- AK - Agent 0CMS Vert Egress Occupancy -- AK - Agent 1CMS Vert Egress Occupancy -- BL - Agent 0CMS Vert Egress Occupancy -- BL - Agent 1CMS Vert Egress Occupancy -- IVCMS Vertical Egress Injection Starvation -- AD - Agent 0CMS Vertical Egress Injection Starvation -- AD - Agent 1CMS Vertical Egress Injection Starvation -- AK - Agent 0CMS Vertical Egress Injection Starvation -- AK - Agent 1CMS Vertical Egress Injection Starvation -- BL - Agent 0CMS Vertical Egress Injection Starvation -- BL - Agent 1CMS Vertical Egress Injection Starvation -- IVDN_EVENVertical AD Ring In Use -- Down and EvenDN_ODDVertical AD Ring In Use -- Down and OddUP_EVENVertical AD Ring In Use -- Up and EvenUP_ODDVertical AD Ring In Use -- Up and OddVertical AK Ring In Use -- Down and EvenVertical AK Ring In Use -- Down and OddVertical AK Ring In Use -- Up and EvenVertical AK Ring In Use -- Up and OddVertical BL Ring in Use -- Down and EvenVertical BL Ring in Use -- Down and OddVertical BL Ring in Use -- Up and EvenVertical BL Ring in Use -- Up and OddDNVertical IV Ring in Use -- DownUPVertical IV Ring in Use -- UpM2M->iMC WPQ Cycles w/Credits - Regular -- Channel 0M2M->iMC WPQ Cycles w/Credits - Regular -- Channel 1M2M->iMC WPQ Cycles w/Credits - Regular -- Channel 2M2M->iMC WPQ Cycles w/Credits - Special -- Channel 0M2M->iMC WPQ Cycles w/Credits - Special -- Channel 1M2M->iMC WPQ Cycles w/Credits - Special -- Channel 2Write Tracker Cycles Full -- Channel 0Write Tracker Cycles Full -- Channel 1Write Tracker Cycles Full -- Channel 2Write Tracker Cycles Not Empty -- Channel 0Write Tracker Cycles Not Empty -- Channel 1Write Tracker Cycles Not Empty -- Channel 2Write Tracker Inserts -- Channel 0Write Tracker Inserts -- Channel 1Write Tracker Inserts -- Channel 2Write Tracker Occupancy -- Channel 0Write Tracker Occupancy -- Channel 1Write Tracker Occupancy -- Channel 2UNC_M2_AG0_AD_CRD_ACQUIREDNumber of CMS Agent 0 AD credits acquired in a given cycle, per transgress.UNC_M2_AG0_AD_CRD_OCCUPANCYNumber of CMS Agent 0 AD credits in use in a given cycle, per transgressUNC_M2_AG0_BL_CRD_ACQUIREDNumber of CMS Agent 0 BL credits acquired in a given cycle, per transgress.UNC_M2_AG0_BL_CRD_OCCUPANCYNumber of CMS Agent 0 BL credits in use in a given cycle, per transgressUNC_M2_AG1_AD_CRD_ACQUIREDNumber of CMS Agent 1 AD credits acquired in a given cycle, per transgress.UNC_M2_AG1_AD_CRD_OCCUPANCYNumber of CMS Agent 1 AD credits in use in a given cycle, per transgressUNC_M2_AG1_BL_CRD_OCCUPANCYNumber of CMS Agent 1 BL credits in use in a given cycle, per transgressUNC_M2_AG1_BL_CREDITS_ACQUIREDNumber of CMS Agent 1 BL credits acquired in a given cycle, per transgress.UNC_M2_BYPASS_M2M_EGRESSTBDUNC_M2_BYPASS_M2M_INGRESSUNC_M2_CLOCKTICKSUNC_M2_CMS_CLOCKTICKSUNC_M2_DIRECT2CORE_NOT_TAKEN_DIRSTATEUNC_M2_DIRECT2CORE_TAKENUNC_M2_DIRECT2CORE_TXN_OVERRIDEUNC_M2_DIRECT2UPI_NOT_TAKEN_CREDITSUNC_M2_DIRECT2UPI_NOT_TAKEN_DIRSTATEUNC_M2_DIRECT2UPI_TAKENUNC_M2_DIRECT2UPI_TXN_OVERRIDEUNC_M2_DIRECTORY_HITUNC_M2_DIRECTORY_LOOKUPUNC_M2_DIRECTORY_MISSUNC_M2_DIRECTORY_UPDATEUNC_M2_EGRESS_ORDERINGCounts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirementsUNC_M2_FAST_ASSERTEDCounts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.UNC_M2_HORZ_RING_AD_IN_USECounts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M2_HORZ_RING_AK_IN_USECounts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M2_HORZ_RING_BL_IN_USECounts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M2_HORZ_RING_IV_IN_USECounts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.UNC_M2_IMC_READSUNC_M2_IMC_WRITESUNC_M2_PKT_MATCHUNC_M2_PREFCAM_CYCLES_FULLUNC_M2_PREFCAM_CYCLES_NEUNC_M2_PREFCAM_DEMAND_PROMOTIONSUNC_M2_PREFCAM_INSERTSUNC_M2_PREFCAM_OCCUPANCYUNC_M2_RING_BOUNCES_HORZNumber of cycles incoming messages from the Horizontal ring that were bounced, by ring type.UNC_M2_RING_BOUNCES_VERTNumber of cycles incoming messages from the Vertical ring that were bounced, by ring type.UNC_M2_RING_SINK_STARVED_HORZUNC_M2_RING_SINK_STARVED_VERTUNC_M2_RING_SRC_THRTLUNC_M2_RPQ_CYCLES_REG_CREDITSUNC_M2_RPQ_CYCLES_SPEC_CREDITSUNC_M2_RXC_AD_CYCLES_FULLUNC_M2_RXC_AD_CYCLES_NEUNC_M2_RXC_AD_INSERTSUNC_M2_RXC_AD_OCCUPANCYUNC_M2_RXC_BL_CYCLES_FULLUNC_M2_RXC_BL_CYCLES_NEUNC_M2_RXC_BL_INSERTSUNC_M2_RXC_BL_OCCUPANCYUNC_M2_RXR_BUSY_STARVEDCounts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priorityUNC_M2_RXR_BYPASSNumber of packets bypassing the CMS IngressUNC_M2_RXR_CRD_STARVEDCounts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.UNC_M2_RXR_INSERTSNumber of allocations into the CMS Ingress The Ingress is used to queue up requests received from the meshUNC_M2_RXR_OCCUPANCYOccupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the meshUNC_M2_STALL_NO_TXR_HORZ_CRD_AD_AG0Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_M2_STALL_NO_TXR_HORZ_CRD_AD_AG1Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_M2_STALL_NO_TXR_HORZ_CRD_BL_AG0Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_M2_STALL_NO_TXR_HORZ_CRD_BL_AG1Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_M2_TGR_AD_CREDITSUNC_M2_TGR_BL_CREDITSUNC_M2_TRACKER_CYCLES_FULLUNC_M2_TRACKER_CYCLES_NEUNC_M2_TRACKER_INSERTSUNC_M2_TRACKER_OCCUPANCYUNC_M2_TRACKER_PENDING_OCCUPANCYUNC_M2_TXC_AD_CREDITS_ACQUIREDUNC_M2_TXC_AD_CREDIT_OCCUPANCYUNC_M2_TXC_AD_CYCLES_FULLUNC_M2_TXC_AD_CYCLES_NEUNC_M2_TXC_AD_INSERTSUNC_M2_TXC_AD_NO_CREDIT_CYCLESUNC_M2_TXC_AD_NO_CREDIT_STALLEDUNC_M2_TXC_AD_OCCUPANCYUNC_M2_TXC_AKUNC_M2_TXC_AK_CREDITS_ACQUIREDUNC_M2_TXC_AK_CREDIT_OCCUPANCYUNC_M2_TXC_AK_CYCLES_FULLUNC_M2_TXC_AK_CYCLES_NEUNC_M2_TXC_AK_INSERTSUNC_M2_TXC_AK_NO_CREDIT_CYCLESUNC_M2_TXC_AK_NO_CREDIT_STALLEDUNC_M2_TXC_AK_OCCUPANCYUNC_M2_TXC_AK_SIDEBANDUNC_M2_TXC_BLUNC_M2_TXC_BL_CREDITS_ACQUIREDUNC_M2_TXC_BL_CREDIT_OCCUPANCYUNC_M2_TXC_BL_CYCLES_FULLUNC_M2_TXC_BL_CYCLES_NEUNC_M2_TXC_BL_INSERTSUNC_M2_TXC_BL_NO_CREDIT_CYCLESUNC_M2_TXC_BL_NO_CREDIT_STALLEDUNC_M2_TXC_BL_OCCUPANCYUNC_M2_TXR_HORZ_ADS_USEDNumber of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.UNC_M2_TXR_HORZ_BYPASSNumber of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.UNC_M2_TXR_HORZ_CYCLES_FULLCycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_M2_TXR_HORZ_CYCLES_NECycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_M2_TXR_HORZ_INSERTSNumber of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_M2_TXR_HORZ_NACKCounts number of Egress packets NACKed on to the Horizontal RinngUNC_M2_TXR_HORZ_OCCUPANCYOccupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_M2_TXR_HORZ_STARVEDCounts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.UNC_M2_TXR_VERT_ADS_USEDNumber of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.UNC_M2_TXR_VERT_BYPASSNumber of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.UNC_M2_TXR_VERT_CYCLES_FULLNumber of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_M2_TXR_VERT_CYCLES_NENumber of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_M2_TXR_VERT_INSERTSNumber of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_M2_TXR_VERT_NACKCounts number of Egress packets NACKed on to the Vertical RinngUNC_M2_TXR_VERT_OCCUPANCYOccupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_M2_TXR_VERT_STARVEDCounts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.UNC_M2_VERT_RING_AD_IN_USECounts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M2_VERT_RING_AK_IN_USECounts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M2_VERT_RING_BL_IN_USECounts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M2_VERT_RING_IV_IN_USECounts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.UNC_M2_WPQ_CYCLES_REG_CREDITSUNC_M2_WPQ_CYCLES_SPEC_CREDITSUNC_M2_WRITE_TRACKER_CYCLES_FULLUNC_M2_WRITE_TRACKER_CYCLES_NEUNC_M2_WRITE_TRACKER_INSERTSUNC_M2_WRITE_TRACKER_OCCUPANCY[UNC_M2M=0x%lx event=0x%x umask=0x%x en=%d edge=%d thres=%d] %s Intel SkylakeX M2M0 uncoreskx_unc_m2m0uncore_m2m_0Intel SkylakeX M2M1 uncoreskx_unc_m2m1uncore_m2m_1TGR0CMS Agent0 Credits Acquired -- For Transgress 0TGR1CMS Agent0 Credits Acquired -- For Transgress 1TGR2CMS Agent0 Credits Acquired -- For Transgress 2TGR3CMS Agent0 Credits Acquired -- For Transgress 3TGR4CMS Agent0 Credits Acquired -- For Transgress 4TGR5CMS Agent0 Credits Acquired -- For Transgress 5CMS Agent0 Credits Occupancy -- For Transgress 0CMS Agent0 Credits Occupancy -- For Transgress 1CMS Agent0 Credits Occupancy -- For Transgress 2CMS Agent0 Credits Occupancy -- For Transgress 3CMS Agent0 Credits Occupancy -- For Transgress 4CMS Agent0 Credits Occupancy -- For Transgress 5REQCBox AD Credits Empty -- RequestsSNPCBox AD Credits Empty -- SnoopsVNACBox AD Credits Empty -- VNA MessagesWBCBox AD Credits Empty -- WritebacksIV_SNOOPGO_DNEgress Blocking due to Ordering requirements -- DownIV_SNOOPGO_UPEgress Blocking due to Ordering requirements -- UpHORZFaST wire asserted -- HorizontalVERTFaST wire asserted -- VerticalLEFT_EVENHorizontal AD Ring In Use -- Left and EvenLEFT_ODDHorizontal AD Ring In Use -- Left and OddRIGHT_EVENHorizontal AD Ring In Use -- Right and EvenRIGHT_ODDHorizontal AD Ring In Use -- Right and OddHorizontal AK Ring In Use -- Left and EvenHorizontal AK Ring In Use -- Left and OddHorizontal AK Ring In Use -- Right and EvenHorizontal AK Ring In Use -- Right and OddHorizontal BL Ring in Use -- Left and EvenHorizontal BL Ring in Use -- Left and OddHorizontal BL Ring in Use -- Right and EvenHorizontal BL Ring in Use -- Right and OddLEFTHorizontal IV Ring in Use -- LeftRIGHTHorizontal IV Ring in Use -- RightIIO0_IIO1_NCBM2 BL Credits Empty -- IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)IIO2_NCBM2 BL Credits Empty -- IIO2IIO3_NCBM2 BL Credits Empty -- IIO3IIO4_NCBM2 BL Credits Empty -- IIO4IIO5_NCBM2 BL Credits Empty -- IIO5NCSM2 BL Credits Empty -- All IIO targets for NCS are in single mask. ORs them togetherNCS_SELM2 BL Credits Empty -- Selected M2p BL NCS creditsAD_SLOT0Multi Slot Flit Received -- AD - Slot 0AD_SLOT1Multi Slot Flit Received -- AD - Slot 1AD_SLOT2Multi Slot Flit Received -- AD - Slot 2AK_SLOT0Multi Slot Flit Received -- AK - Slot 0AK_SLOT2Multi Slot Flit Received -- AK - Slot 2BL_SLOT0Multi Slot Flit Received -- BL - Slot 0ADMessages that bounced on the Horizontal Ring. -- ADAKMessages that bounced on the Horizontal Ring. -- AKBLMessages that bounced on the Horizontal Ring. -- BLIVMessages that bounced on the Horizontal Ring. -- IVMessages that bounced on the Vertical Ring. -- ADMessages that bounced on the Vertical Ring. -- Acknowledgements to coreMessages that bounced on the Vertical Ring. -- Data Responses to coreMessages that bounced on the Vertical Ring. -- Snoops of processors cachee.Sink Starvation on Horizontal Ring -- ADSink Starvation on Horizontal Ring -- AKAK_AG1Sink Starvation on Horizontal Ring -- Acknowledgements to Agent 1Sink Starvation on Horizontal Ring -- BLSink Starvation on Horizontal Ring -- IVSink Starvation on Vertical Ring -- ADSink Starvation on Vertical Ring -- Acknowledgements to coreSink Starvation on Vertical Ring -- Data Responses to coreSink Starvation on Vertical Ring -- Snoops of processors cachee.AD_REQLost Arb for VN0 -- REQ on ADAD_RSPLost Arb for VN0 -- RSP on ADAD_SNPLost Arb for VN0 -- SNP on ADBL_NCBLost Arb for VN0 -- NCB on BLBL_NCSLost Arb for VN0 -- NCS on BLBL_RSPLost Arb for VN0 -- RSP on BLBL_WBLost Arb for VN0 -- WB on BLLost Arb for VN1 -- REQ on ADLost Arb for VN1 -- RSP on ADLost Arb for VN1 -- SNP on ADLost Arb for VN1 -- NCB on BLLost Arb for VN1 -- NCS on BLLost Arb for VN1 -- RSP on BLLost Arb for VN1 -- WB on BLADBL_PARALLEL_WINArb Miscellaneous -- AD, BL Parallel WinNO_PROG_AD_VN0Arb Miscellaneous -- No Progress on Pending AD VN0NO_PROG_AD_VN1Arb Miscellaneous -- No Progress on Pending AD VN1NO_PROG_BL_VN0Arb Miscellaneous -- No Progress on Pending BL VN0NO_PROG_BL_VN1Arb Miscellaneous -- No Progress on Pending BL VN1PAR_BIAS_VN0Arb Miscellaneous -- Parallel Bias to VN0PAR_BIAS_VN1Arb Miscellaneous -- Parallel Bias to VN1Cant Arb for VN0 -- REQ on AADCant Arb for VN0 -- RSP on AADCant Arb for VN0 -- SNP on AADCant Arb for VN0 -- NCB on BBLCant Arb for VN0 -- NCS on BBLCant Arb for VN0 -- RSP on BBLCant Arb for VN0 -- WB on BBLCant Arb for VN1 -- REQ on AADCant Arb for VN1 -- RSP on AADCant Arb for VN1 -- SNP on AADCant Arb for VN1 -- NCB on BBLCant Arb for VN1 -- NCS on BBLCant Arb for VN1 -- RSP on BBLCant Arb for VN1 -- WB on BBLNo Credits to Arb for VN0 -- REQ on ADNo Credits to Arb for VN0 -- RSP on ADNo Credits to Arb for VN0 -- SNP on ADNo Credits to Arb for VN0 -- NCB on BLNo Credits to Arb for VN0 -- NCS on BLNo Credits to Arb for VN0 -- RSP on BLNo Credits to Arb for VN0 -- WB on BLNo Credits to Arb for VN1 -- REQ on ADNo Credits to Arb for VN1 -- RSP on ADNo Credits to Arb for VN1 -- SNP on ADNo Credits to Arb for VN1 -- NCB on BLNo Credits to Arb for VN1 -- NCS on BLNo Credits to Arb for VN1 -- RSP on BLNo Credits to Arb for VN1 -- WB on BLAD_S0_BL_ARBIngress Queue Bypasses -- AD to Slot 0 on BL ArbAD_S0_IDLEIngress Queue Bypasses -- AD to Slot 0 on IdleAD_S1_BL_SLOTIngress Queue Bypasses -- AD + BL to Slot 1AD_S2_BL_SLOTIngress Queue Bypasses -- AD + BL to Slot 2VN0 message lost contest for flit -- REQ on ADVN0 message lost contest for flit -- RSP on ADVN0 message lost contest for flit -- SNP on ADVN0 message lost contest for flit -- NCB on BLVN0 message lost contest for flit -- NCS on BLVN0 message lost contest for flit -- RSP on BLVN0 message lost contest for flit -- WB on BLVN1 message lost contest for flit -- REQ on ADVN1 message lost contest for flit -- RSP on ADVN1 message lost contest for flit -- SNP on ADVN1 message lost contest for flit -- NCB on BLVN1 message lost contest for flit -- NCS on BLVN1 message lost contest for flit -- RSP on BLVN1 message lost contest for flit -- WB on BLANY_BGF_FIFOMiscellaneous Credit Events -- Any In BGF FIFOANY_BGF_PATHMiscellaneous Credit Events -- Any in BGF PathNO_D2K_FOR_ARBMiscellaneous Credit Events -- No D2K For ArbD2K_CRDCredit Occupancy -- D2K CreditsFLITS_IN_FIFOCredit Occupancy -- Packets in BGF FIFOFLITS_IN_PATHCredit Occupancy -- Packets in BGF PathP1P_FIFOCredit Occupancy -- P1P_TOTALTxQ_CRDCredit Occupancy -- Transmit CreditsVNA_IN_USECredit Occupancy -- VNA In UseVN0 Ingress (from CMS) Queue - Cycles Not Empty -- REQ on ADVN0 Ingress (from CMS) Queue - Cycles Not Empty -- RSP on ADVN0 Ingress (from CMS) Queue - Cycles Not Empty -- SNP on ADVN0 Ingress (from CMS) Queue - Cycles Not Empty -- NCB on BLVN0 Ingress (from CMS) Queue - Cycles Not Empty -- NCS on BLVN0 Ingress (from CMS) Queue - Cycles Not Empty -- RSP on BLVN0 Ingress (from CMS) Queue - Cycles Not Empty -- WB on BLVN1 Ingress (from CMS) Queue - Cycles Not Empty -- REQ on ADVN1 Ingress (from CMS) Queue - Cycles Not Empty -- RSP on ADVN1 Ingress (from CMS) Queue - Cycles Not Empty -- SNP on ADVN1 Ingress (from CMS) Queue - Cycles Not Empty -- NCB on BLVN1 Ingress (from CMS) Queue - Cycles Not Empty -- NCS on BLVN1 Ingress (from CMS) Queue - Cycles Not Empty -- RSP on BLVN1 Ingress (from CMS) Queue - Cycles Not Empty -- WB on BLALLData Flit Not Sent -- AllNO_BGFData Flit Not Sent -- No BGF CreditsNO_TXQData Flit Not Sent -- No TxQ CreditsP0_WAITGenerating BL Data Flit Sequence -- Wait on Pump 0P1P_AT_LIMITGenerating BL Data Flit Sequence -- P1P_BUSYP1P_FIFO_FULLP1P_HOLD_P0P1P_TO_LIMBOP1_WAITGenerating BL Data Flit Sequence -- Wait on Pump 11_MSGSent Header Flit -- One Message1_MSG_VNXSent Header Flit -- One Message in non-VNA2_MSGSSent Header Flit -- Two Messages3_MSGSSent Header Flit -- Three MessagesSLOTS_1Sent Header Flit -- SLOTS_2SLOTS_3Slotting BL Message Into Header Flit -- AllNEED_DATASlotting BL Message Into Header Flit -- Needs Data FlitSlotting BL Message Into Header Flit -- Wait on Pump 0P1_NOT_REQSlotting BL Message Into Header Flit -- Dont Need Pump 1P1_NOT_REQ_BUT_BUBBLESlotting BL Message Into Header Flit -- Dont Need Pump 1 - BubblleP1_NOT_REQ_NOT_AVAILSlotting BL Message Into Header Flit -- Dont Need Pump 1 - Not AvaiilSlotting BL Message Into Header Flit -- Wait on Pump 1ACCUMFlit Gen - Header 1 -- AcumullateACCUM_READFlit Gen - Header 1 -- Accumulate ReadyACCUM_WASTEDFlit Gen - Header 1 -- Accumulate WastedAHEAD_BLOCKEDFlit Gen - Header 1 -- Run-Ahead - BlockedAHEAD_MSGFlit Gen - Header 1 -- Run-Ahead - MessagePARFlit Gen - Header 1 -- Parallel OkPAR_FLITFlit Gen - Header 1 -- Parallel Flit FinishedPAR_MSGFlit Gen - Header 1 -- Parallel MessageRMSTALLFlit Gen - Header 2 -- Rate-matching StallRMSTALL_NOMSGFlit Gen - Header 2 -- Rate-matching Stall - No MessageHeader Not Sent -- AllNO_BGF_CRDHeader Not Sent -- No BGF CreditsNO_BGF_NO_MSGHeader Not Sent -- No BGF Credits + No Extra Message SlottedNO_TXQ_CRDHeader Not Sent -- No TxQ CreditsNO_TXQ_NO_MSGHeader Not Sent -- No TxQ Credits + No Extra Message SlottedONE_TAKENHeader Not Sent -- Sent - One Slot TakenTHREE_TAKENHeader Not Sent -- Sent - Three Slots TakenTWO_TAKENHeader Not Sent -- Sent - Two Slots TakenCANT_SLOT_ADMessage Held -- Cant Slot AADCANT_SLOT_BLMessage Held -- Cant Slot BBLPARALLEL_AD_LOSTMessage Held -- Parallel AD LostPARALLEL_ATTEMPTMessage Held -- Parallel AttemptPARALLEL_BL_LOSTMessage Held -- Parallel BL LostPARALLEL_SUCCESSMessage Held -- Parallel SuccessVN0Message Held -- VN0VN1Message Held -- VN1VN0 Ingress (from CMS) Queue - Inserts -- REQ on ADVN0 Ingress (from CMS) Queue - Inserts -- RSP on ADVN0 Ingress (from CMS) Queue - Inserts -- SNP on ADVN0 Ingress (from CMS) Queue - Inserts -- NCB on BLVN0 Ingress (from CMS) Queue - Inserts -- NCS on BLVN0 Ingress (from CMS) Queue - Inserts -- RSP on BLVN0 Ingress (from CMS) Queue - Inserts -- WB on BLVN1 Ingress (from CMS) Queue - Inserts -- REQ on ADVN1 Ingress (from CMS) Queue - Inserts -- RSP on ADVN1 Ingress (from CMS) Queue - Inserts -- SNP on ADVN1 Ingress (from CMS) Queue - Inserts -- NCB on BLVN1 Ingress (from CMS) Queue - Inserts -- NCS on BLVN1 Ingress (from CMS) Queue - Inserts -- RSP on BLVN1 Ingress (from CMS) Queue - Inserts -- WB on BLVN0 Ingress (from CMS) Queue - Occupancy -- REQ on ADVN0 Ingress (from CMS) Queue - Occupancy -- RSP on ADVN0 Ingress (from CMS) Queue - Occupancy -- SNP on ADVN0 Ingress (from CMS) Queue - Occupancy -- NCB on BLVN0 Ingress (from CMS) Queue - Occupancy -- NCS on BLVN0 Ingress (from CMS) Queue - Occupancy -- RSP on BLVN0 Ingress (from CMS) Queue - Occupancy -- WB on BLVN1 Ingress (from CMS) Queue - Occupancy -- REQ on ADVN1 Ingress (from CMS) Queue - Occupancy -- RSP on ADVN1 Ingress (from CMS) Queue - Occupancy -- SNP on ADVN1 Ingress (from CMS) Queue - Occupancy -- NCB on BLVN1 Ingress (from CMS) Queue - Occupancy -- NCS on BLVN1 Ingress (from CMS) Queue - Occupancy -- RSP on BLVN1 Ingress (from CMS) Queue - Occupancy -- WB on BLVN0 message cant slot into flit -- REQ on AADVN0 message cant slot into flit -- RSP on AADVN0 message cant slot into flit -- SNP on AADVN0 message cant slot into flit -- NCB on BBLVN0 message cant slot into flit -- NCS on BBLVN0 message cant slot into flit -- RSP on BBLVN0 message cant slot into flit -- WB on BBLVN1 message cant slot into flit -- REQ on AADVN1 message cant slot into flit -- RSP on AADVN1 message cant slot into flit -- SNP on AADVN1 message cant slot into flit -- NCB on BBLVN1 message cant slot into flit -- NCS on BBLVN1 message cant slot into flit -- RSP on BBLVN1 message cant slot into flit -- WB on BBLARB_LOSTSMI3 Prefetch Messages -- Lost ArbitrationARRIVEDSMI3 Prefetch Messages -- ArrivedDROP_OLDSMI3 Prefetch Messages -- Dropped - OldDROP_WRAPSMI3 Prefetch Messages -- Dropped - WrapSLOTTEDSMI3 Prefetch Messages -- SlottedANY_IN_USERemote VNA Credits -- Any In UseCORRECTEDRemote VNA Credits -- CorrectedLT1Remote VNA Credits -- Level < 1LT4Remote VNA Credits -- Level < 4LT5Remote VNA Credits -- Level < 5USEDRemote VNA Credits -- UsedAD_BNCTransgress Injection Starvation -- AD - BounceAD_CRDTransgress Injection Starvation -- AD - CreditBL_BNCTransgress Injection Starvation -- BL - BounceBL_CRDTransgress Injection Starvation -- BL - CreditTransgress Ingress Bypass -- AD - BounceTransgress Ingress Bypass -- AD - CreditAK_BNCTransgress Ingress Bypass -- AK - BounceTransgress Ingress Bypass -- BL - BounceTransgress Ingress Bypass -- BL - CreditIV_BNCTransgress Ingress Bypass -- IV - BounceTransgress Injection Starvation -- AK - BounceIFVTransgress Injection Starvation -- IFV - CreditTransgress Injection Starvation -- IV - BounceTransgress Ingress Allocations -- AD - BounceTransgress Ingress Allocations -- AD - CreditTransgress Ingress Allocations -- AK - BounceTransgress Ingress Allocations -- BL - BounceTransgress Ingress Allocations -- BL - CreditTransgress Ingress Allocations -- IV - BounceTransgress Ingress Occupancy -- AD - BounceTransgress Ingress Occupancy -- AD - CreditTransgress Ingress Occupancy -- AK - BounceTransgress Ingress Occupancy -- BL - BounceTransgress Ingress Occupancy -- BL - CreditTransgress Ingress Occupancy -- IV - BounceStall on No AD Agent0 Transgress Credits -- For Transgress 0Stall on No AD Agent0 Transgress Credits -- For Transgress 1Stall on No AD Agent0 Transgress Credits -- For Transgress 2Stall on No AD Agent0 Transgress Credits -- For Transgress 3Stall on No AD Agent0 Transgress Credits -- For Transgress 4Stall on No AD Agent0 Transgress Credits -- For Transgress 5Stall on No AD Agent1 Transgress Credits -- For Transgress 0Stall on No AD Agent1 Transgress Credits -- For Transgress 1Stall on No AD Agent1 Transgress Credits -- For Transgress 2Stall on No AD Agent1 Transgress Credits -- For Transgress 3Stall on No AD Agent1 Transgress Credits -- For Transgress 4Stall on No AD Agent1 Transgress Credits -- For Transgress 5Stall on No BL Agent0 Transgress Credits -- For Transgress 0Stall on No BL Agent0 Transgress Credits -- For Transgress 1Stall on No BL Agent0 Transgress Credits -- For Transgress 2Stall on No BL Agent0 Transgress Credits -- For Transgress 3Stall on No BL Agent0 Transgress Credits -- For Transgress 4Stall on No BL Agent0 Transgress Credits -- For Transgress 5Stall on No BL Agent1 Transgress Credits -- For Transgress 0Stall on No BL Agent1 Transgress Credits -- For Transgress 1Stall on No BL Agent1 Transgress Credits -- For Transgress 2Stall on No BL Agent1 Transgress Credits -- For Transgress 3Stall on No BL Agent1 Transgress Credits -- For Transgress 4Stall on No BL Agent1 Transgress Credits -- For Transgress 5VN0_REQFailed ARB for AD -- VN0 REQ MessagesVN0_RSPFailed ARB for AD -- VN0 RSP MessagesVN0_SNPFailed ARB for AD -- VN0 SNP MessagesVN0_WBFailed ARB for AD -- VN0 WB MessagesVN1_REQFailed ARB for AD -- VN1 REQ MessagesVN1_RSPFailed ARB for AD -- VN1 RSP MessagesVN1_SNPFailed ARB for AD -- VN1 SNP MessagesVN1_WBFailed ARB for AD -- VN1 WB MessagesAD FlowQ Bypass -- BL_EARLY_RSPAD Flow Q Not Empty -- VN0 REQ MessagesAD Flow Q Not Empty -- VN0 RSP MessagesAD Flow Q Not Empty -- VN0 SNP MessagesAD Flow Q Not Empty -- VN0 WB MessagesAD Flow Q Not Empty -- VN1 REQ MessagesAD Flow Q Not Empty -- VN1 RSP MessagesAD Flow Q Not Empty -- VN1 SNP MessagesAD Flow Q Not Empty -- VN1 WB MessagesAD Flow Q Inserts -- VN0 REQ MessagesAD Flow Q Inserts -- VN0 RSP MessagesAD Flow Q Inserts -- VN0 SNP MessagesAD Flow Q Inserts -- VN0 WB MessagesAD Flow Q Inserts -- VN1 REQ MessagesAD Flow Q Inserts -- VN1 RSP MessagesAD Flow Q Inserts -- VN1 SNP MessagesAD Flow Q Occupancy -- VN0 REQ MessagesAD Flow Q Occupancy -- VN0 RSP MessagesAD Flow Q Occupancy -- VN0 SNP MessagesAD Flow Q Occupancy -- VN0 WB MessagesAD Flow Q Occupancy -- VN1 REQ MessagesAD Flow Q Occupancy -- VN1 RSP MessagesAD Flow Q Occupancy -- VN1 SNP MessagesVN0_CHANumber of Snoop Targets -- CHA on VN0VN0_NON_IDLENumber of Snoop Targets -- Non Idle cycles on VN0VN0_PEER_UPI0Number of Snoop Targets -- Peer UPI0 on VN0VN0_PEER_UPI1Number of Snoop Targets -- Peer UPI1 on VN0VN1_CHANumber of Snoop Targets -- CHA on VN1VN1_NON_IDLENumber of Snoop Targets -- Non Idle cycles on VN1VN1_PEER_UPI0Number of Snoop Targets -- Peer UPI0 on VN1VN1_PEER_UPI1Number of Snoop Targets -- Peer UPI1 on VN1VN0_SNPFP_NONSNPSnoop Arbitration -- FlowQ WonVN0_SNPFP_VN2SNPSnoop Arbitration -- FlowQ SnpF WonVN1_SNPFP_NONSNPVN1_SNPFP_VN0SNPSpeculative ARB for AD - Credit Available -- VN0 REQ MessagesSpeculative ARB for AD - Credit Available -- VN0 SNP MessagesSpeculative ARB for AD - Credit Available -- VN0 WB MessagesSpeculative ARB for AD - Credit Available -- VN1 REQ MessagesSpeculative ARB for AD - Credit Available -- VN1 SNP MessagesSpeculative ARB for AD - Credit Available -- VN1 WB MessagesSpeculative ARB for AD - New Message -- VN0 REQ MessagesSpeculative ARB for AD - New Message -- VN0 SNP MessagesSpeculative ARB for AD - New Message -- VN0 WB MessagesSpeculative ARB for AD - New Message -- VN1 REQ MessagesSpeculative ARB for AD - New Message -- VN1 SNP MessagesSpeculative ARB for AD - New Message -- VN1 WB MessagesSpeculative ARB for AD - No Credit -- VN0 REQ MessagesSpeculative ARB for AD - No Credit -- VN0 RSP MessagesSpeculative ARB for AD - No Credit -- VN0 SNP MessagesSpeculative ARB for AD - No Credit -- VN0 WB MessagesSpeculative ARB for AD - No Credit -- VN1 REQ MessagesSpeculative ARB for AD - No Credit -- VN1 RSP MessagesSpeculative ARB for AD - No Credit -- VN1 SNP MessagesSpeculative ARB for AD - No Credit -- VN1 WB MessagesVN0_NCBFailed ARB for BL -- VN0 NCB MessagesVN0_NCSFailed ARB for BL -- VN0 NCS MessagesFailed ARB for BL -- VN0 RSP MessagesFailed ARB for BL -- VN0 WB MessagesVN1_NCBFailed ARB for BL -- VN1 NCS MessagesVN1_NCSFailed ARB for BL -- VN1 NCB MessagesFailed ARB for BL -- VN1 RSP MessagesFailed ARB for BL -- VN1 WB MessagesBL Flow Q Not Empty -- VN0 REQ MessagesBL Flow Q Not Empty -- VN0 RSP MessagesBL Flow Q Not Empty -- VN0 SNP MessagesBL Flow Q Not Empty -- VN0 WB MessagesBL Flow Q Not Empty -- VN1 REQ MessagesBL Flow Q Not Empty -- VN1 RSP MessagesBL Flow Q Not Empty -- VN1 SNP MessagesBL Flow Q Not Empty -- VN1 WB MessagesBL Flow Q Inserts -- VN0 RSP MessagesBL Flow Q Inserts -- VN0 WB MessagesBL Flow Q Inserts -- VN0 NCS MessagesBL Flow Q Inserts -- VN0 NCB MessagesBL Flow Q Inserts -- VN1 RSP MessagesBL Flow Q Inserts -- VN1 WB MessagesBL Flow Q Inserts -- VN1_NCB MessagesBL Flow Q Inserts -- VN1_NCS MessagesBL Flow Q Occupancy -- VN0 NCB MessagesBL Flow Q Occupancy -- VN0 NCS MessagesBL Flow Q Occupancy -- VN0 RSP MessagesBL Flow Q Occupancy -- VN0 WB MessagesBL Flow Q Occupancy -- VN1_NCS MessagesBL Flow Q Occupancy -- VN1_NCB MessagesBL Flow Q Occupancy -- VN1 RSP MessagesBL Flow Q Occupancy -- VN1 WB MessagesSpeculative ARB for BL - New Message -- VN0 WB MessagesSpeculative ARB for BL - New Message -- VN0 NCS MessagesSpeculative ARB for BL - New Message -- VN1 WB MessagesSpeculative ARB for BL - New Message -- VN1 NCB MessagesSpeculative ARB for BL - New Message -- VN1 RSP MessagesSpeculative ARB for AD Failed - No Credit -- VN0 NCB MessagesSpeculative ARB for AD Failed - No Credit -- VN0 NCS MessagesSpeculative ARB for AD Failed - No Credit -- VN0 RSP MessagesSpeculative ARB for AD Failed - No Credit -- VN0 WB MessagesSpeculative ARB for AD Failed - No Credit -- VN1 NCS MessagesSpeculative ARB for AD Failed - No Credit -- VN1 NCB MessagesSpeculative ARB for AD Failed - No Credit -- VN1 RSP MessagesSpeculative ARB for AD Failed - No Credit -- VN1 WB MessagesCMS Horizontal ADS Used -- AD - BounceCMS Horizontal ADS Used -- AD - CreditCMS Horizontal ADS Used -- AK - BounceCMS Horizontal ADS Used -- BL - BounceCMS Horizontal ADS Used -- BL - CreditCMS Horizontal Bypass Used -- AD - BounceCMS Horizontal Bypass Used -- AD - CreditCMS Horizontal Bypass Used -- AK - BounceCMS Horizontal Bypass Used -- BL - BounceCMS Horizontal Bypass Used -- BL - CreditCMS Horizontal Bypass Used -- IV - BounceCycles CMS Horizontal Egress Queue is Full -- AD - BounceCycles CMS Horizontal Egress Queue is Full -- AD - CreditCycles CMS Horizontal Egress Queue is Full -- AK - BounceCycles CMS Horizontal Egress Queue is Full -- BL - BounceCycles CMS Horizontal Egress Queue is Full -- BL - CreditCycles CMS Horizontal Egress Queue is Full -- IV - BounceCycles CMS Horizontal Egress Queue is Not Empty -- AD - BounceCycles CMS Horizontal Egress Queue is Not Empty -- AD - CreditCycles CMS Horizontal Egress Queue is Not Empty -- AK - BounceCycles CMS Horizontal Egress Queue is Not Empty -- BL - BounceCycles CMS Horizontal Egress Queue is Not Empty -- BL - CreditCycles CMS Horizontal Egress Queue is Not Empty -- IV - BounceCMS Horizontal Egress Inserts -- AD - BounceCMS Horizontal Egress Inserts -- AD - CreditCMS Horizontal Egress Inserts -- AK - BounceCMS Horizontal Egress Inserts -- BL - BounceCMS Horizontal Egress Inserts -- BL - CreditCMS Horizontal Egress Inserts -- IV - BounceCMS Horizontal Egress NACKs -- AD - BounceCMS Horizontal Egress NACKs -- AD - CreditCMS Horizontal Egress NACKs -- AK - BounceCMS Horizontal Egress NACKs -- BL - BounceCMS Horizontal Egress NACKs -- BL - CreditCMS Horizontal Egress NACKs -- IV - BounceCMS Horizontal Egress Occupancy -- AD - BounceCMS Horizontal Egress Occupancy -- AD - CreditCMS Horizontal Egress Occupancy -- AK - BounceCMS Horizontal Egress Occupancy -- BL - BounceCMS Horizontal Egress Occupancy -- BL - CreditCMS Horizontal Egress Occupancy -- IV - BounceCMS Horizontal Egress Injection Starvation -- AD - BounceCMS Horizontal Egress Injection Starvation -- AK - BounceCMS Horizontal Egress Injection Starvation -- BL - BounceCMS Horizontal Egress Injection Starvation -- IV - BounceAD_AG0CMS Vertical ADS Used -- AD - Agent 0AD_AG1CMS Vertical ADS Used -- AD - Agent 1AK_AG0CMS Vertical ADS Used -- AK - Agent 0CMS Vertical ADS Used -- AK - Agent 1BL_AG0CMS Vertical ADS Used -- BL - Agent 0BL_AG1CMS Vertical ADS Used -- BL - Agent 1CMS Vertical ADS Used -- IVCycles CMS Vertical Egress Queue Is Full -- AD - Agent 0Cycles CMS Vertical Egress Queue Is Full -- AD - Agent 1Cycles CMS Vertical Egress Queue Is Full -- AK - Agent 0Cycles CMS Vertical Egress Queue Is Full -- AK - Agent 1Cycles CMS Vertical Egress Queue Is Full -- BL - Agent 0Cycles CMS Vertical Egress Queue Is Full -- BL - Agent 1Cycles CMS Vertical Egress Queue Is Full -- IVCycles CMS Vertical Egress Queue Is Not Empty -- AD - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- AD - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- AK - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- AK - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- BL - Agent 0Cycles CMS Vertical Egress Queue Is Not Empty -- BL - Agent 1Cycles CMS Vertical Egress Queue Is Not Empty -- IVCMS Vert Egress Allocations -- AD - Agent 0CMS Vert Egress Allocations -- AD - Agent 1CMS Vert Egress Allocations -- AK - Agent 0CMS Vert Egress Allocations -- AK - Agent 1CMS Vert Egress Allocations -- BL - Agent 0CMS Vert Egress Allocations -- BL - Agent 1CMS Vert Egress Allocations -- IVCMS Vertical Egress NACKs -- AD - Agent 0CMS Vertical Egress NACKs -- AD - Agent 1CMS Vertical Egress NACKs -- AK - Agent 0CMS Vertical Egress NACKs -- AK - Agent 1CMS Vertical Egress NACKs -- BL - Agent 0CMS Vertical Egress NACKs -- BL - Agent 1CMS Vertical Egress NACKs -- IVCMS Vert Egress Occupancy -- AD - Agent 0CMS Vert Egress Occupancy -- AD - Agent 1CMS Vert Egress Occupancy -- AK - Agent 0CMS Vert Egress Occupancy -- AK - Agent 1CMS Vert Egress Occupancy -- BL - Agent 0CMS Vert Egress Occupancy -- BL - Agent 1CMS Vert Egress Occupancy -- IVCMS Vertical Egress Injection Starvation -- AD - Agent 0CMS Vertical Egress Injection Starvation -- AD - Agent 1CMS Vertical Egress Injection Starvation -- AK - Agent 0CMS Vertical Egress Injection Starvation -- AK - Agent 1CMS Vertical Egress Injection Starvation -- BL - Agent 0CMS Vertical Egress Injection Starvation -- BL - Agent 1CMS Vertical Egress Injection Starvation -- IVUPI0 AD Credits Empty -- VN0 REQ MessagesUPI0 AD Credits Empty -- VN0 RSP MessagesUPI0 AD Credits Empty -- VN0 SNP MessagesUPI0 AD Credits Empty -- VN1 REQ MessagesUPI0 AD Credits Empty -- VN1 RSP MessagesUPI0 AD Credits Empty -- VN1 SNP MessagesUPI0 AD Credits Empty -- VNAVN0_NCS_NCBUPI0 BL Credits Empty -- VN0 RSP MessagesUPI0 BL Credits Empty -- VN0 REQ MessagesUPI0 BL Credits Empty -- VN0 SNP MessagesVN1_NCS_NCBUPI0 BL Credits Empty -- VN1 RSP MessagesUPI0 BL Credits Empty -- VN1 REQ MessagesUPI0 BL Credits Empty -- VN1 SNP MessagesUPI0 BL Credits Empty -- VNADN_EVENVertical AD Ring In Use -- Down and EvenDN_ODDVertical AD Ring In Use -- Down and OddUP_EVENVertical AD Ring In Use -- Up and EvenUP_ODDVertical AD Ring In Use -- Up and OddVertical AK Ring In Use -- Down and EvenVertical AK Ring In Use -- Down and OddVertical AK Ring In Use -- Up and EvenVertical AK Ring In Use -- Up and OddVertical BL Ring in Use -- Down and EvenVertical BL Ring in Use -- Down and OddVertical BL Ring in Use -- Up and EvenVertical BL Ring in Use -- Up and OddDNVertical IV Ring in Use -- DownUPVertical IV Ring in Use -- UpNCBVN0 Credit Used -- WB on BLVN0 Credit Used -- NCB on BLVN0 Credit Used -- REQ on ADRSPVN0 Credit Used -- RSP on ADVN0 Credit Used -- SNP on ADVN0 Credit Used -- RSP on BLVN0 No Credits -- WB on BLVN0 No Credits -- NCB on BLVN0 No Credits -- REQ on ADVN0 No Credits -- RSP on ADVN0 No Credits -- SNP on ADVN0 No Credits -- RSP on BLVN1 Credit Used -- WB on BLVN1 Credit Used -- NCB on BLVN1 Credit Used -- REQ on ADVN1 Credit Used -- RSP on ADVN1 Credit Used -- SNP on ADVN1 Credit Used -- RSP on BLVN1 No Credits -- WB on BLVN1 No Credits -- NCB on BLVN1 No Credits -- REQ on ADVN1 No Credits -- RSP on ADVN1 No Credits -- SNP on ADVN1 No Credits -- RSP on BLUNC_M3_AG0_AD_CRD_ACQUIREDNumber of CMS Agent 0 AD credits acquired in a given cycle, per transgress.UNC_M3_AG0_AD_CRD_OCCUPANCYNumber of CMS Agent 0 AD credits in use in a given cycle, per transgressUNC_M3_AG0_BL_CRD_ACQUIREDNumber of CMS Agent 0 BL credits acquired in a given cycle, per transgress.UNC_M3_AG0_BL_CRD_OCCUPANCYNumber of CMS Agent 0 BL credits in use in a given cycle, per transgressUNC_M3_AG1_AD_CRD_ACQUIREDNumber of CMS Agent 1 AD credits acquired in a given cycle, per transgress.UNC_M3_AG1_AD_CRD_OCCUPANCYNumber of CMS Agent 1 AD credits in use in a given cycle, per transgressUNC_M3_AG1_BL_CRD_OCCUPANCYNumber of CMS Agent 1 BL credits in use in a given cycle, per transgressUNC_M3_AG1_BL_CREDITS_ACQUIREDNumber of CMS Agent 1 BL credits acquired in a given cycle, per transgress.UNC_M3_CHA_AD_CREDITS_EMPTYNo credits available to send to Cbox on the AD Ring (covers higher CBoxes)UNC_M3_CLOCKTICKSCounts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.UNC_M3_CMS_CLOCKTICKSTBDUNC_M3_D2C_SENTCount cases BL sends direct to coreUNC_M3_D2U_SENTCases where SMI3 sends D2U commandUNC_M3_EGRESS_ORDERINGCounts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirementsUNC_M3_FAST_ASSERTEDCounts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.UNC_M3_HORZ_RING_AD_IN_USECounts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M3_HORZ_RING_AK_IN_USECounts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M3_HORZ_RING_BL_IN_USECounts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M3_HORZ_RING_IV_IN_USECounts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.UNC_M3_M2_BL_CREDITS_EMPTYNo vn0 and vna credits available to send to M2UNC_M3_MULTI_SLOT_RCVDMulti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)UNC_M3_RING_BOUNCES_HORZNumber of cycles incoming messages from the Horizontal ring that were bounced, by ring type.UNC_M3_RING_BOUNCES_VERTNumber of cycles incoming messages from the Vertical ring that were bounced, by ring type.UNC_M3_RING_SINK_STARVED_HORZUNC_M3_RING_SINK_STARVED_VERTUNC_M3_RING_SRC_THRTLUNC_M3_RXC_ARB_LOST_VN0VN0 message requested but lost arbitrationUNC_M3_RXC_ARB_LOST_VN1VN1 message requested but lost arbitrationUNC_M3_RXC_ARB_MISCUNC_M3_RXC_ARB_NOAD_REQ_VN0VN0 message was not able to request arbitration while some other message won arbitrationUNC_M3_RXC_ARB_NOAD_REQ_VN1VN1 message was not able to request arbitration while some other message won arbitrationUNC_M3_RXC_ARB_NOCRED_VN0VN0 message is blocked from requesting arbitration due to lack of remote UPI creditsUNC_M3_RXC_ARB_NOCRED_VN1VN1 message is blocked from requesting arbitration due to lack of remote UPI creditsUNC_M3_RXC_BYPASSEDNumber ot times message is bypassed around the Ingress QueueUNC_M3_RXC_COLLISION_VN0Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.UNC_M3_RXC_COLLISION_VN1Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.UNC_M3_RXC_CRD_MISCUNC_M3_RXC_CRD_OCCUNC_M3_RXC_CYCLES_NE_VN0Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.UNC_M3_RXC_CYCLES_NE_VN1Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.UNC_M3_RXC_FLITS_DATA_NOT_SENTData flit is ready for transmission but could not be sentUNC_M3_RXC_FLITS_GEN_BLUNC_M3_RXC_FLITS_MISCUNC_M3_RXC_FLITS_SENTUNC_M3_RXC_FLITS_SLOT_BLUNC_M3_RXC_FLIT_GEN_HDR1Events related to Header Flit Generation - Set 1UNC_M3_RXC_FLIT_GEN_HDR2Events related to Header Flit Generation - Set 2UNC_M3_RXC_FLIT_NOT_SENTheader flit is ready for transmission but could not be sentUNC_M3_RXC_HELDUNC_M3_RXC_INSERTS_VN0Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.UNC_M3_RXC_INSERTS_VN1UNC_M3_RXC_OCCUPANCY_VN0Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.UNC_M3_RXC_OCCUPANCY_VN1UNC_M3_RXC_PACKING_MISS_VN0Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.UNC_M3_RXC_PACKING_MISS_VN1UNC_M3_RXC_SMI3_PFTCHUNC_M3_RXC_VNA_CRDUNC_M3_RXR_BUSY_STARVEDCounts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priorityUNC_M3_RXR_BYPASSNumber of packets bypassing the CMS IngressUNC_M3_RXR_CRD_STARVEDCounts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.UNC_M3_RXR_INSERTSNumber of allocations into the CMS Ingress The Ingress is used to queue up requests received from the meshUNC_M3_RXR_OCCUPANCYOccupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the meshUNC_M3_STALL_NO_TXR_HORZ_CRD_AD_AG0Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_M3_STALL_NO_TXR_HORZ_CRD_AD_AG1Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_M3_STALL_NO_TXR_HORZ_CRD_BL_AG0Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_M3_STALL_NO_TXR_HORZ_CRD_BL_AG1Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.UNC_M3_TXC_AD_ARB_FAILAD arb but no win; arb request asserted but not wonUNC_M3_TXC_AD_FLQ_BYPASSCounts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)UNC_M3_TXC_AD_FLQ_CYCLES_NENumber of cycles the AD Egress queue is Not EmptyUNC_M3_TXC_AD_FLQ_INSERTSCounts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.UNC_M3_TXC_AD_FLQ_OCCUPANCYUNC_M3_TXC_AD_SNPF_GRP1_VN1Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latencyUNC_M3_TXC_AD_SNPF_GRP2_VN1Outcome of SnpF pending arbitrationUNC_M3_TXC_AD_SPEC_ARB_CRD_AVAILAD speculative arb request with prior cycle credit check complete and credit availUNC_M3_TXC_AD_SPEC_ARB_NEW_MSGAD speculative arb request due to new message arriving on a specific channel (MC/VN)UNC_M3_TXC_AD_SPEC_ARB_NO_OTHER_PENDAD speculative arb request asserted due to no other channel being active (have a valid entry but dont have credits to sendd)UNC_M3_TXC_AK_FLQ_INSERTSUNC_M3_TXC_AK_FLQ_OCCUPANCYUNC_M3_TXC_BL_ARB_FAILBL arb but no win; arb request asserted but not wonUNC_M3_TXC_BL_FLQ_CYCLES_NENumber of cycles the BL Egress queue is Not EmptyUNC_M3_TXC_BL_FLQ_INSERTSUNC_M3_TXC_BL_FLQ_OCCUPANCYUNC_M3_TXC_BL_SPEC_ARB_NEW_MSGBL speculative arb request due to new message arriving on a specific channel (MC/VN)UNC_M3_TXC_BL_SPEC_ARB_NO_OTHER_PENDBL speculative arb request asserted due to no other channel being active (have a valid entry but dont have credits to sendd)UNC_M3_TXR_HORZ_ADS_USEDNumber of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.UNC_M3_TXR_HORZ_BYPASSNumber of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.UNC_M3_TXR_HORZ_CYCLES_FULLCycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_M3_TXR_HORZ_CYCLES_NECycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_M3_TXR_HORZ_INSERTSNumber of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_M3_TXR_HORZ_NACKCounts number of Egress packets NACKed on to the Horizontal RinngUNC_M3_TXR_HORZ_OCCUPANCYOccupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.UNC_M3_TXR_HORZ_STARVEDCounts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.UNC_M3_TXR_VERT_ADS_USEDNumber of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.UNC_M3_TXR_VERT_BYPASSNumber of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.UNC_M3_TXR_VERT_CYCLES_FULLNumber of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_M3_TXR_VERT_CYCLES_NENumber of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_M3_TXR_VERT_INSERTSNumber of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_M3_TXR_VERT_NACKCounts number of Egress packets NACKed on to the Vertical RinngUNC_M3_TXR_VERT_OCCUPANCYOccupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.UNC_M3_TXR_VERT_STARVEDCounts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.UNC_M3_UPI_PEER_AD_CREDITS_EMPTYNo credits available to send to UPIs on the AD RingUNC_M3_UPI_PEER_BL_CREDITS_EMPTYNo credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)UNC_M3_UPI_PREFETCH_SPAWNCount cases where FlowQ causes spawn of Prefetch to iMC/SMI3 targetUNC_M3_VERT_RING_AD_IN_USECounts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M3_VERT_RING_AK_IN_USECounts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M3_VERT_RING_BL_IN_USECounts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the rhe ring.UNC_M3_VERT_RING_IV_IN_USECounts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ DN_ODD.UNC_M3_VN0_CREDITS_USEDNumber of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.UNC_M3_VN0_NO_CREDITSNumber of Cycles there were no VN0 CreditsUNC_M3_VN1_CREDITS_USEDNumber of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.UNC_M3_VN1_NO_CREDITSNumber of Cycles there were no VN1 Credits[UNC_M3UPI=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel SkylakeX M3UPI0 uncoreskx_unc_m3upi0uncore_m3upi_0Intel SkylakeX M3UPI1 uncoreskx_unc_m3upi1uncore_m3upi_1Intel SkylakeX M3UPI2 uncoreskx_unc_m3upi2uncore_m3upi_2CORES_C0Number of cores in C-State -- C0 and C1CORES_C3Number of cores in C-State -- C3CORES_C6Number of cores in C-State -- C6 and C7UNC_P_CLOCKTICKSThe PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controllers dclk, counts at a constant rate making it a good measure of actual wall timee.UNC_P_CORE_TRANSITION_CYCLESTBDUNC_P_CTS_EVENT0UNC_P_CTS_EVENT1UNC_P_DEMOTIONSUNC_P_FIVR_PS_PS0_CYCLESCycles spent in phase-shedding power state 0UNC_P_FIVR_PS_PS1_CYCLESCycles spent in phase-shedding power state 1UNC_P_FIVR_PS_PS2_CYCLESCycles spent in phase-shedding power state 2UNC_P_FIVR_PS_PS3_CYCLESCycles spent in phase-shedding power state 3UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLESCounts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.UNC_P_FREQ_MAX_POWER_CYCLESCounts the number of cycles when power is the upper limit on frequency.UNC_P_FREQ_MIN_IO_P_CYCLESCounts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.UNC_P_FREQ_TRANS_CYCLESCounts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.UNC_P_MCP_PROCHOT_CYCLESUNC_P_MEMORY_PHASE_SHEDDING_CYCLESCounts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.UNC_P_PKG_RESIDENCY_C0_CYCLESCounts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.UNC_P_PKG_RESIDENCY_C2E_CYCLESCounts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.UNC_P_PKG_RESIDENCY_C3_CYCLESCounts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.UNC_P_PKG_RESIDENCY_C6_CYCLESCounts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.UNC_P_PMAX_THROTTLED_CYCLESUNC_P_PROCHOT_EXTERNAL_CYCLESCounts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.UNC_P_PROCHOT_INTERNAL_CYCLESCounts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.UNC_P_TOTAL_TRANSITION_CYCLESNumber of cycles spent performing core C state transitions across all cores.UNC_P_FREQ_BAND0_CYCLESFrequency ResidencyUNC_P_FREQ_BAND1_CYCLESUNC_P_FREQ_BAND2_CYCLESUNC_P_FREQ_BAND3_CYCLESUNC_P_VR_HOT_CYCLESUNC_P_POWER_STATE_OCCUPANCYThis is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.[UNC_PCU=0x%lx event=0x%x sel_ext=%d occ_sel=0x%x en=%d edge=%d thres=%d occ_inv=%d occ_edge=%d] %s [UNC_PCU_FILTER=0x%lx band0=%u band1=%u band2=%u band3=%u] Intel SkylakeX PCU uncoreskx_unc_pcuuncore_pcuDOORBELL_RCVDMessage Received -- INT_PRIOIPI_RCVDMessage Received -- IPIMSI_RCVDMessage Received -- MSIVLW_RCVDMessage Received -- VLWASSERT_TO_ACKCycles PHOLD Assert to Ack -- Assert to ACKPFTCH_BUF_EMPTYTBDRDRANDRDSEEDUNC_U_EVENT_MSGVirtual Logical Wire (legacy) message were received from Uncore.UNC_U_LOCK_CYCLESNumber of times an IDI Lock/SplitLock sequence was startedUNC_U_PHOLD_CYCLESPHOLD cycles.UNC_U_RACU_DRNGUNC_U_RACU_REQUESTSNumber outstanding register requests within message channel tracker[UNC_UBO=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel SkylakeX U-Box uncoreskx_unc_ubouncore_uboxD2CDirect packet attempts -- Direct 2 CoreD2UDirect packet attempts -- Direct 2 UPIAD_VNA_EQ0TBDAD_VNA_EQ1AD_VNA_EQ2AK_VNA_EQ0AK_VNA_EQ1AK_VNA_EQ2AK_VNA_EQ3BL_VNA_EQ0BGF_CRDFLOWQ_AD_VNA_LE2FLOWQ_AK_VNA_LE3FLOWQ_BL_VNA_EQ0GV_BLOCKFLOWQ_AD_VNA_BTW_2_THRESHFLOWQ_BL_VNA_BTW_0_THRESHACKVN0VN1VNANCBMatches on Receive path of a UPI Port -- Non-Coherent BypassNCB_OPC_NCWRMatches on Receive path of a UPI Port -- Non-Coherent Bypass - NCWRNCB_OPC_WCWRMatches on Receive path of a UPI Port -- Non-Coherent Bypass - WCWRNCB_OPC_NCMSGBNCB_OPC_INTLOGICALNCB_OPC_INTPHYSICALMatches on Receive path of a UPI Port -- Non-Coherent Bypass - INTPHYSICALNCB_OPC_INTPRIOUPDMatches on Receive path of a UPI Port -- Non-Coherent Bypass - INTPRIOUPDNCB_OPC_NCWRPTLMatches on Receive path of a UPI Port -- Non-Coherent Bypass - NCWRPTLNCB_OPC_NCP2PBMatches on Receive path of a UPI Port -- Non-Coherent Bypass - NCP2PBNCSMatches on Receive path of a UPI Port -- Non-Coherent StandardNCS_OPC_NCRDMatches on Receive path of a UPI Port -- Non-Coherent Standard - NCRDNCS_OPC_INTACKMatches on Receive path of a UPI Port -- Non-Coherent Standard - INTACKNCS_OPC_NCRDPTLMatches on Receive path of a UPI Port -- Non-Coherent Standard - NCRDPTLNCS_OPC_NCCFGRDNCS - NCCFGRDNCS_OPC_NCLTRDMatches on Receive path of a UPI Port -- Non-Coherent Standard - NCLTRDNCS_OPC_IORDMatches on Receive path of a UPI Port -- Non-Coherent Standard - IORDNCS_OPC_MSGSNCS - MSGSNCS_OPC_CFGWRMatches on Receive path of a UPI Port -- Non-Coherent Standard - CFGWRNCS_OPC_LTWRMatches on Receive path of a UPI Port -- Non-Coherent Standard - LTWRNCS_OPC_NCIOWRMatches on Receive path of a UPI Port -- Non-Coherent Standard - NCIOWRNCS_OPC_NCP2PSMatches on Receive path of a UPI Port -- Non-Coherent Standard - NCP2PSREQMatches on Receive path of a UPI Port -- RequestREQ_OPC_INVITOEMatches on Receive path of a UPI Port -- Request Opcode - ITOEREQ_OPC_RDINVMatches on Receive path of a UPI Port -- Request Opcode - ReadInvRSPCNFLTMatches on Receive path of a UPI Port -- Response - ConflictRSPIMatches on Receive path of a UPI Port -- Response - InvalidRSP_DATAMatches on Receive path of a UPI Port -- Response - DataRSP_DATA_OPC_DATA_MMatches on Receive path of a UPI Port -- Response - Data - DATA_MRSP_DATA_OPC_DATA_EMatches on Receive path of a UPI Port -- Response - Data - DATA_ERSP_DATA_OPC_DATA_SIMatches on Receive path of a UPI Port -- Response - Data - DATA_SIRSP_DATA_OPC_DATA_M_CMPORSP4 - DATA_M_CMPORSP_DATA_OPC_DATA_E_CMPOMatches on Receive path of a UPI Port -- Response - Data - DATA_E_CMPORSP_DATA_OPC_DATA_SI_CMPOMatches on Receive path of a UPI Port -- Response - Data - DATA_SI_CMPORSP_DATA_OPC_RSPFWDIWBMatches on Receive path of a UPI Port -- Response - Data - RSPFWDIWBRSP_DATA_OPC_RSPFWDSWBRSP_DATA_OPC_RSPIWBMatches on Receive path of a UPI Port -- Response - Data - RSPIWBRSP_DATA_OPC_RSPSWBMatches on Receive path of a UPI Port -- Response - Data - RSPSWBRSP_DATA_OPC_DEBUG_DATAMatches on Receive path of a UPI Port -- Response - Data - DEBUGDATARSP_NODATAMatches on Receive path of a UPI Port -- Response - No DataRSP_NODATA_OPC_FWDSMatches on Receive path of a UPI Port -- Response - No Data - FWDSRSP_NODATA_OPC_MIRCMPUMatches on Receive path of a UPI Port -- Response - No Data - MIRCMPURSP_NODATA_OPC_CNFLTMatches on Receive path of a UPI Port -- Response - No Data - CNFLTRSP_NODATA_OPC_FWDCNFLTOMatches on Receive path of a UPI Port -- Response - No Data - FWDCNFLTORSP_NODATA_OPC_CMPOMatches on Receive path of a UPI Port -- Response - No Data - CMPOSNPMatches on Receive path of a UPI Port -- SnoopSNP_OPC_FCURMatches on Receive path of a UPI Port -- Snoop Opcode - FCURSNP_OPC_FCODEMatches on Receive path of a UPI Port -- Snoop Opcode - FCODESNP_OPC_FDATAMatches on Receive path of a UPI Port -- Snoop Opcode - FDATASNP_OPC_FDATAMIGMatches on Receive path of a UPI Port -- Snoop Opcode - FDATAMIGSNP_OPC_FINVOWNSNP_OPC_FINVMatches on Receive path of a UPI Port -- Snoop Opcode - FINVWBMatches on Receive path of a UPI Port -- WritebackWB_OPC_WBMTOIMatches on Receive path of a UPI Port -- Writeback - MTOIWB_OPC_WBMTOSMatches on Receive path of a UPI Port -- Writeback - MTOSWB_OPC_WBMTOEMatches on Receive path of a UPI Port -- Writeback - MTOEWB_OPC_NONSNPWRMatches on Receive path of a UPI Port -- Writeback - NONSNPWRWB_OPC_MTOIPTLMatches on Receive path of a UPI Port -- Writeback - MTOIPTLWB_OPC_MTOEPTLMatches on Receive path of a UPI Port -- Writeback - MTOEPTLWB_OPC_NONSNPWRTLMatches on Receive path of a UPI Port -- Writeback - NONSNPWRTLWB_OPC_PUSHMTOIMatches on Receive path of a UPI Port -- Writeback - PUSHMTOIWB_OPC_FLUSHMatches on Receive path of a UPI Port -- Writeback - FLUSHWB_OPC_EVCTCLNMatches on Receive path of a UPI Port -- Writeback - EVCTCLNWB_OPC_NONSNPRDWB - NONSNPRDFILT_NONENo extra filterFILT_LOCALFilter packets targeting this socketFILT_REMOTEFilter packets targeting another socketFILT_DATAFilter on Data packets (mutually exclusive with FILT_NON_DATA)FILT_NON_DATAFilter on non-Data packets (mutually exclusive with FILT_DATA)FILT_DUAL_SLOTFilter on dual-slot packets (mutually exclusive with FILT_SINGLE_SLOT)FILT_SINGLE_SLOTFilter on single-slot packets (mutually exclusive with FILT_DUAL_SLOT)FILT_ISOCHFilter on isochronous packetsFILT_SLOT0Filter on slot0 packetsFILT_SLOT1Filter on slot1 packetsFILT_SLOT2Filter on slot2 packetsFILT_LLCRD_NON_ZEROFilter on LLCRD nonzero (only applies to slot2 with opcode match)FILT_IMPL_NULLFilter on implied NULL (only applies to slot2 with opcode match)SLOT0RxQ Flit Buffer Bypassed -- Slot 0SLOT1RxQ Flit Buffer Bypassed -- Slot 1SLOT2RxQ Flit Buffer Bypassed -- Slot 2ALL_DATAValid Flits Received -- All DataALL_NULLValid Flits Received -- All Null SlotsDATAValid Flits Received -- DataIDLEValid Flits Received -- IdleLLCRDValid Flits Received -- LLCRD Not EmptyLLCTRLValid Flits Received -- LLCTRLNON_DATAValid Flits Received -- All Non DataNULLValid Flits Received -- Slot NULL or LLCRD EmptyPROTHDRValid Flits Received -- Protocol HeaderValid Flits Received -- Slot 0Valid Flits Received -- Slot 1Valid Flits Received -- Slot 2RxQ Flit Buffer Allocations -- Slot 0RxQ Flit Buffer Allocations -- Slot 1RxQ Flit Buffer Allocations -- Slot 2RxQ Occupancy - All Packets -- Slot 0RxQ Occupancy - All Packets -- Slot 1RxQ Occupancy - All Packets -- Slot 2S0_RXQ1S0_RXQ2S1_RXQ0S1_RXQ2S2_RXQ0S2_RXQ1CFG_CTLDFXRETRYRXQRXQ_BYPASSRXQ_CREDSPARETXQValid Flits Sent -- All DataValid Flits Sent -- All Null SlotsValid Flits Sent -- DataValid Flits Sent -- IdleValid Flits Sent -- LLCRD Not EmptyValid Flits Sent -- LLCTRLValid Flits Sent -- All Non DataValid Flits Sent -- Slot NULL or LLCRD EmptyValid Flits Sent -- Protocol HeaderValid Flits Sent -- Slot 0Valid Flits Sent -- Slot 1Valid Flits Sent -- Slot 2UNC_UPI_CLOCKTICKSCounts the number of clocks in the UPI LL. This clock runs at 1/8th the GT/s speed of the UPI link. For example, a 8GT/s link will have qfclk or 1GHz. Current products do not support dynamic link speeds, so this frequency is fixexed.UNC_UPI_DIRECT_ATTEMPTSCounts the number of Data Response(DRS) packets UPI attempted to send directly to the core or to a different UPI link. Note: This only counts attempts on valid candidates such as DRS packets destined for CHAs.UNC_UPI_FLOWQ_NO_VNA_CRDUNC_UPI_L1_POWER_CYCLESNumber of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.UNC_UPI_M3_BYP_BLOCKEDUNC_UPI_M3_CRD_RETURN_BLOCKEDUNC_UPI_M3_RXQ_BLOCKEDUNC_UPI_PHY_INIT_CYCLESUNC_UPI_POWER_L1_NACKCounts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agents Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agents Tx originally requested the power change and this agent accepted itit).UNC_UPI_POWER_L1_REQCounts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agents Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agents Tx originally requested the power change and this agent accepted itit).UNC_UPI_REQ_SLOT2_FROM_M3UNC_UPI_RXL0P_POWER_CYCLESNumber of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.UNC_UPI_RXL0_POWER_CYCLESNumber of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.UNC_UPI_RXL_BASIC_HDR_MATCHUNC_UPI_RXL_BYPASSEDCounts the number of times that an incoming flit was able to bypass the flit buffer and pass directly and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.UNC_UPI_RXL_CREDITS_CONSUMED_VN0Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.UNC_UPI_RXL_CREDITS_CONSUMED_VN1Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.UNC_UPI_RXL_CREDITS_CONSUMED_VNACounts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.UNC_UPI_RXL_FLITSShows legal flit time (hides impact of L0p and L0c).UNC_UPI_RXL_INSERTSNumber of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.UNC_UPI_RXL_OCCUPANCYAccumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.UNC_UPI_RXL_SLOT_BYPASSUNC_UPI_TXL0P_CLK_ACTIVEUNC_UPI_TXL0P_POWER_CYCLESUNC_UPI_TXL0P_POWER_CYCLES_LL_ENTERUNC_UPI_TXL0P_POWER_CYCLES_M3_EXITUNC_UPI_TXL0_POWER_CYCLESUNC_UPI_TXL_BASIC_HDR_MATCHUNC_UPI_TXL_BYPASSEDCounts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.UNC_UPI_TXL_FLITSUNC_UPI_TXL_INSERTSNumber of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.UNC_UPI_TXL_OCCUPANCYAccumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCYNumber of VNA credits in the Rx side that are waitng to be returned back across the link.[UNC_UPI=0x%lx event=0x%x sel_ext=%d umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel SkylakeX UPI0 uncoreskx_unc_upi0uncore_upi_0Intel SkylakeX UPI1 uncoreskx_unc_upi1uncore_upi_1Intel SkylakeX UPI2 uncoreskx_unc_upi2uncore_upi_2BANK_CONFLICTSNumber of actual bank conflictsBRANCHESNumber of taken and not taken branches, including: conditional branches, jumps, calls, returns, software interrupts, and interrupt returnsBRANCHES_MISPREDICTEDNumber of branch mispredictions that occurred on BTB hits. BTB misses are not considered branch mispredicts because no prediction exists for them yet.CODE_CACHE_MISSNumber of instruction reads that miss the internal code cache; whether the read is cacheable or noncacheableCODE_PAGE_WALKNumber of code page walksCODE_READNumber of instruction reads; whether the read is cacheable or noncacheableCPU_CLK_UNHALTEDNumber of cycles during which the processor is not halted.DATA_CACHE_LINES_WRITTEN_BACKNumber of dirty lines (all) that are written back, regardless of the causeDATA_PAGE_WALKNumber of data page walksDATA_READNumber of successful memory data reads committed by the K-unit (L1). Cache accesses resulting from prefetch instructions are included for A0 stepping.DATA_READ_MISSNumber of memory read accesses that miss the internal data cache whether or not the access is cacheable or noncacheable. Cache accesses resulting from prefetch instructions are not included.DATA_READ_MISS_OR_WRITE_MISSNumber of memory read and/or write accesses that miss the internal data cache, whether or not the access is cacheable or noncacheableDATA_READ_OR_WRITENumber of memory data reads and/or writes (internal data cache hit and miss combined). Read cache accesses resulting from prefetch instructions are included for A0 stepping.DATA_WRITENumber of successful memory data writes committed by the K-unit (L1). Streaming stores (hit/miss L1), cacheable write partials, and UC promotions are all included.DATA_WRITE_MISSNumber of memory write accesses that miss the internal data cache whether or not the access is cacheable. Non-cacheable misses are not included.EXEC_STAGE_CYCLESNumber of E-stage cycles that were successfully completed. Includes cycles generated by multi-cycle E-stage instructions. For instructions destined for the FPU or VPU pipelines, this event only counts occupancy in the integer E-stage.FE_STALLEDNumber of cycles where the front-end could not advance. Any multi-cycle instructions which delay pipeline advance and apply backpressure to the front-end will be included, e.g. read-modify-write instructions. Includes cycles when the front-end did not have any instructions to issue.INSTRUCTIONS_EXECUTEDNumber of instructions executed (up to two per clock)INSTRUCTIONS_EXECUTED_V_PIPENumber of instructions executed in the V_pipe. The event indicates the number of instructions that were paired.L1_DATA_HIT_INFLIGHT_PF1Number of data requests which hit an in-flight vprefetch0. The in-flight vprefetch0 was not necessarily issued from the same thread as the data request.L1_DATA_PF1Number of data vprefetch0 requests seen by the L1.L1_DATA_PF1_DROPNumber of data vprefetch0 requests seen by the L1 which were dropped for any reason. A vprefetch0 can be dropped if the requested address matches another in-flight request or if it has a UC memtype.L1_DATA_PF1_MISSNumber of data vprefetch0 requests seen by the L1 which missed L1. Does not include vprefetch1 requests which are counted in L1_DATA_PF1_DROP.L1_DATA_PF2Number of data vprefetch1 requests seen by the L1. This is not necessarily the same number as seen by the L2 because this count includes requests that are dropped by the core. A vprefetch1 can be dropped by the core if the requested address matches another in-flight request or if it has a UC memtype.L2_CODE_READ_MISS_CACHE_FILLNumber of code read accesses that missed the L2 cache and were satisfied by another L2 cache. Can include promoted read misses that started as DATA accesses.L2_CODE_READ_MISS_MEM_FILLNumber of code read accesses that missed the L2 cache and were satisfied by main memory. Can include promoted read misses that started as DATA accesses.L2_DATA_HIT_INFLIGHT_PF2Number of data requests which hit an in-flight vprefetch1. The in-flight vprefetch1 was not necessarily issued from the same thread as the data request.L2_DATA_PF1_MISSNumber of data vprefetch0 requests seen by the L2 which missed L2.L2_DATA_PF2Number of data vprefetch1 requests seen by the L2. Only counts vprefetch1 hits on A0 stepping.L2_DATA_PF2_DROPNumber of data vprefetch1 requests seen by the L2 which were dropped for any reason.L2_DATA_PF2_MISSNumber of data vprefetch1 requests seen by the L2 which missed L2. Does not include vprefetch2 requests which are counted in L2_DATA_PF2_DROP.L2_DATA_READ_MISS_CACHE_FILLNumber of data read accesses that missed the L2 cache and were satisfied by another L2 cache. Can include promoted read misses that started as CODE accesses.L2_DATA_READ_MISS_MEM_FILLNumber of data read accesses that missed the L2 cache and were satisfied by main memory. Can include promoted read misses that started as CODE accesses.L2_DATA_WRITE_MISS_CACHE_FILLNumber of data write (RFO) accesses that missed the L2 cache and were satisfied by another L2 cache.L2_DATA_WRITE_MISS_MEM_FILLNumber of data write (RFO) accesses that missed the L2 cache and were satisfied by main memory.L2_READ_HIT_EL2 Read Hit E State, may include prefetches on A0 stepping.L2_READ_HIT_ML2 Read Hit M StateL2_READ_HIT_SL2 Read Hit S StateL2_READ_MISSL2 Read Misses. Prefetch and demand requests to the same address will produce double counting.L2_VICTIM_REQ_WITH_DATAL2 received a victim request and responded with dataL2_WRITE_HITL2 Write HIT, may undercount on A0 stepping.LONG_CODE_PAGE_WALKNumber of long code page walks, i.e. page walks that also missed the L2 uTLB. Subset of DATA_CODE_WALK eventLONG_DATA_PAGE_WALKNumber of long data page walks, i.e. page walks that also missed the L2 uTLB. Subset of DATA_PAGE_WALK eventMEMORY_ACCESSES_IN_BOTH_PIPESNumber of data memory reads or writes that are paired in both pipes of the pipelineMICROCODE_CYCLESThe number of cycles microcode is executing. While microcode is executing, all other threads are stalled.PIPELINE_AGI_STALLSNumber of address generation interlock (AGI) stalls. An AGI occurring in both the U- and V- pipelines in the same clock signals this event twice.PIPELINE_FLUSHESNumber of pipeline flushes that occur. Pipeline flushes are caused by BTB misses on taken branches, mispredictions, exceptions, interrupts, and some segment descriptor loads.PIPELINE_SG_AGI_STALLSNumber of address generation interlock (AGI) stalls due to vscatter* and vgather* instructions.SNP_HITM_BUNITSnoop HITM in BUNITSNP_HITM_L2Snoop HITM in L2SNP_HIT_L2Snoop HIT in L2VPU_DATA_READNumber of read transactions that were issued. In general each read transaction will read 1 64B cacheline. If there are alignment issues, then reads against multiple cache lines will each be counted individually.VPU_DATA_READ_MISSVPU L1 data cache readmiss. Counts the number of occurrences.VPU_DATA_WRITENumber of write transactions that were issued. . In general each write transaction will write 1 64B cacheline. If there are alignment issues, then write against multiple cache lines will each be counted individually.VPU_DATA_WRITE_MISSVPU L1 data cache write miss. Counts the number of occurrences.VPU_ELEMENTS_ACTIVECounts the cumulative number of elements active (via mask) for VPU instructions issued.VPU_INSTRUCTIONS_EXECUTEDCounts the number of VPU instructions executed in both u- and v-pipes.VPU_INSTRUCTIONS_EXECUTED_V_PIPECounts the number of VPU instructions that paired and executed in the v-pipe.VPU_STALL_REGVPU stall on Register Dependency. Counts the number of occurrences. Dependencies will include RAW, WAW, WAR.Intel Knights CornerkncACCESSESInstruction fetches, including uncacheacble fetchesMISSESCount all instructions fetches that miss the icache or produce memory requests. This includes uncacheache fetches. Any instruction fetch miss is counted only once and not once for every cycle it is outstandingHITCount all instructions fetches from the instruction cacheANYMicro-ops retiredMSMicro-ops retired that were supplied fro MSROMSTALLED_CYCLESCycles no micro-ops retiredSTALLSPeriods no micro-ops retiredANY_PInstructions retired using generic counter (precise event)ALLNumber of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims)SMCSelf-Modifying Code detectedMEMORY_ORDERINGNumber of stalled cycles due to memory orderingFP_ASSISTNumber of stalled cycle due to FPU assistCount any the machine clearsAny retired branch instruction (Precise Event)ALL_BRANCHESAny Retired branch instruction (Precise Event)ALL_TAKEN_BRANCHESRetired branch instructions (Precise Event)JCCJCC instructions retired (Precise Event)TAKEN_JCCTaken JCC instructions retired (Precise Event)CALLNear call instructions retired (Precise Event)REL_CALLNear relative call instructions retired (Precise Event)IND_CALLNear indirect call instructions retired (Precise Event)RETURNNear ret instructions retired (Precise Event)NON_RETURN_INDNumber of near indirect jmp and near indirect call instructions retired (Precise Event)FAR_BRANCHFar branch instructions retired (Precise Event)FARBACLEARS assertedNumber of baclears for return branchesCONDNumber of baclears for conditional branchesCORE_PCore cycles when core is not haltedBUSBus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratioREFNumber of reference cycles that the core is not in a halted state. The core enters the halted state when it is running the HLT instruction. In mobile systems, the core frequency may change from time to time. This event is not affected by core frequency changes but counts as if the core is running a the same maximum frequency all the timeLD_DCU_MISSNumber of load uops retired that miss in L1 data cache. Note that prefetch misses will not be countedLD_L2_HITNumber of load uops retired that hit L2 (Precise Event)LD_L2_MISSNumber of load uops retired that missed L2 (Precise Event)LD_DTLB_MISSNumber of load uops retired that had a DTLB miss (Precise Event)LD_UTLB_MISSNumber of load uops retired that had a UTLB missHITMNumber of load uops retired that got data from the other core or from the other module and the line was modified (Precise Event)ANY_LDNumber of load uops retiredANY_STNumber of store uops retiredMISSNumber of L2 cache missesNumber of L2 cache referencesLD_BLOCK_ST_FORWARDNumber of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch (Precise Event)LD_BLOCK_STD_NOTREADYNumber of times forward was technically possible but did not occur because the store data was not available at the right timeST_SPLITSNumber of retired stores that experienced cache line boundary splitsLD_SPLITSNumber of retired loads that experienced cache line boundary splits (Precise Event)LOCKNumber of retired memory operations with lock semantics. These are either implicit locked instructions such as XCHG or instructions with an explicit LOCK prefixSTA_FULLNumber of retired stores that are delayed because there is not a store address buffer availableNumber of load uops reissued from RehabQNumber of store uops reissued from RehabQDMND_DATA_RDRequest: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetchesDMND_IFETCHRequest: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesWBRequest: number of writebacks (modified to exclusive) transactionsPF_L2_DATA_RDRequest: number of data cacheline reads generated by L2 prefetchersPF_RFORequest: number of RFO requests generated by L2 prefetchersPF_IFETCHRequest: number of code reads generated by L2 prefetchersPARTIAL_READRequest: number of demand reads of partial cachelines (including UC, WC)PARTIAL_WRITERequest: number of demand RFO requests to write to partial cache lines (includes UC, WT, WP)UC_IFETCHRequest: number of UC instruction fetchesBUS_LOCKSRequest: number bus lock and split lock requestsSTRM_STRequest: number of streaming store requestsSW_PREFETCHRequest: number of software prefetch requestsPF_L1_DATA_RDRequest: number of data cacheline reads generated by L1 prefetchersPARTIAL_STRM_STRequest: number of partial streaming store requestsOTHERRequest: counts one any other request that crosses IDI, including I/OANY_IFETCHRequest: combination of PF_IFETCH | DMND_IFETCH | UC_IFETCHPF_IFETCH:DMND_IFETCH:UC_IFETCHANY_REQUESTRequest: combination of all request umasksDMND_DATA_RD:DMND_RFO:DMND_IFETCH:WB:PF_L2_DATA_RD:PF_RFO:PF_IFETCH:PARTIAL_READ:PARTIAL_WRITE:UC_IFETCH:BUS_LOCKS:STRM_ST:SW_PREFETCH:PF_L1_DATA_RD:PARTIAL_STRM_ST:OTHERANY_DATARequest: combination of DMND_DATA | PF_L1_DATA_RD | PF_L2_DATA_RDDMND_DATA_RD:PF_L1_DATA_RD:PF_L2_DATA_RDANY_RFORequest: combination of DMND_RFO | PF_RFODMND_RFO:PF_RFOANY_RESPONSEResponse: count any response typeL2_HITSupplier: counts L2 hits in M/E/S statesSNP_NONESnoop: counts number of times no snoop-related information is availableSNP_MISSSnoop: counts number of times a snoop was needed and it missed all snooped cachesSNP_HITSnoop: counts number of times a snoop hits in the other module where no modified copies were found in the L1 cache of the other coreSNP_HITMSnoop: counts number of times a snoop hits in the other module where modified copies were found in the L1 cache of the other coreNON_DRAMSnoop: counts number of times target was a non-DRAM system address. This includes MMIO transactionsSNP_ANYSnoop: any snoop reasonSNP_NONE:SNP_MISS:SNP_HIT:SNP_HITM:NON_DRAMAll mispredicted branches (Precise Event)Number of mispredicted conditional branch instructions retired (Precise Event)Number of mispredicted non-return branch instructions retired (Precise Event)Number of mispredicted return branch instructions retired (Precise Event)Number of mispredicted indirect call branch instructions retired (Precise Event)Number of mispredicted taken conditional branch instructions retired (Precise Event)Number of cycles when the front-end does not provide any instructions to be allocated for any reasonNOT_DELIVEREDNumber of cycles when the front-end does not provide any instructions to be allocated but the back-end is not stalledMISPREDICTSNumber of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retireRAT_STALLNumber of cycles when no uops are allocated and a RAT stall is assertedROB_FULLNumber of cycles when no uops are allocated and the ROB is full (less than 2 entries available)MECNumber of cycles when the allocation pipeline is stalled due to the RS for the MEC cluster is fullNumber of cycles when the allocation pipeline is stalled due any one of the RS being fullNumber of cycles the divider is busyENTRYNumber of times the MSROM starts a flow of uopsPREDECODE_WRONGNumber of times the prediction (from the predecode cache) for instruction length is incorrectICACHE_FILL_PENDING_CYCLESNumber of cycles the NIP stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache missesNumber of requests that were not accepted into the L2Q because the L2Q was FULLCYCLESTotal cycles for all the page walks. (I-side and D-side)WALKSTotal number of page walks. (I-side and D-side)D_SIDE_WALKS:I_SIDE_WALKSD_SIDE_CYCLESNumber of cycles when a D-side page walk is in progressD_SIDE_WALKSNumber of D-side page walksD_SIDE_CYCLES:eI_SIDE_CYCLESNumber of cycles when a I-side page walk is in progressI_SIDE_WALKSNumber of I-side page walksI_SIDE_CYCLES:eUNHALTED_CORE_CYCLESUnhalted core cyclesUNHALTED_REFERENCE_CYCLESUnhalted reference cycleINSTRUCTION_RETIREDInstructions retiredINSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIREDLLC_REFERENCESLast level of cache referencesLAST_LEVEL_CACHE_REFERENCESThis is an alias for LLC_REFERENCESLLC_MISSESLast level of cache missesLAST_LEVEL_CACHE_MISSESThis is an alias for LLC_MISSESBRANCH_INSTRUCTIONS_RETIREDBranch instructions retiredBR_INST_RETIRED:ANYMISPREDICTED_BRANCH_RETIREDMispredicted branch instruction retiredBR_MISP_RETIREDDECODE_RESTRICTIONInstruction length prediction delayL2_REJECT_XQRejected L2 requests to XQICACHEInstruction fetchesUOPS_RETIREDINST_RETIREDCYCLES_DIV_BUSYCycles the divider is busyRS_FULL_STALLRS fullLLC_RQSTSL2 cache requestsMACHINE_CLEARSBR_INST_RETIREDRetired branch instructionsMispredicted retired branch instructions (Precise Event)BR_MISP_INST_RETIREDMS_DECODEDMS decoderBACLEARSBranch address calculatorNO_ALLOC_CYCLESFront-end allocationCPU_CLK_UNHALTEDMEM_UOP_RETIREDRetired loads micro-opsCORE_REJECT_L2QDemand and L1 prefetcher requests rejected by L2REHABQMemory reference queueFETCH_STALLFetch stallsPAGE_WALKSPage walkerOFFCORE_RESPONSE_0Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)OFFCORE_RESPONSE_17MLIntel SilvermontslmHITCounts all instruction fetches that hit the instruction cache.MISSESCounts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.ACCESSESCounts all instruction fetches, including uncacheable fetches.ALLCounts the number of micro-ops retired.MSCounts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS).SCALAR_SIMDCounts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.PACKED_SIMDCounts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.ANY_PInstructions retired using generic counter (precise event)ANYCounts the number of MEC requests from the L2Q that reference a cache line excluding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times.Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative pathSMCCounts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page.MEMORY_ORDERINGCounts the number of times the machine clears due to memory ordering hazardsFP_ASSISTCounts the number of floating operations retired that required microcode assistsCounts all nukesCounts the number of branch instructions retired (Precise Event)ALL_BRANCHESCounts the number of branch instructions retiredJCCCounts the number of branch instructions retired that were conditional jumps.TAKEN_JCCCounts the number of branch instructions retired that were conditional jumps and predicted taken.CALLCounts the number of near CALL branch instructions retired.REL_CALLCounts the number of near relative CALL branch instructions retired.IND_CALLCounts the number of near indirect CALL branch instructions retired. (Precise Event)RETURNCounts the number of near RET branch instructions retired. (Precise Event)NON_RETURN_INDCounts the number of branch instructions retired that were near indirect CALL or near indirect JMP. (Precise Event)FAR_BRANCHCounts the number of far branch instructions retired. (Precise Event)FARICACHE_FILL_PENDING_CYCLESCounts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of core cycles the fetch stalled for all icache missesCounts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.CONDCounts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.THREAD_Pthread cycles when core is not haltedBUSBus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratioREF_PNumber of reference cycles that the cpu is not in a halted state. The core enters the halted state when it is running the HLT instruction. In mobile systems, the core frequency may change from time to time. This event is not affected by core frequency changes but counts as if the core is running a the same maximum frequency all the timeL1_MISS_LOADSCounts the number of load micro-ops retired that miss in L1 D cache.LD_DCU_MISSL2_HIT_LOADSCounts the number of load micro-ops retired that hit in the L2.L2_MISS_LOADSCounts the number of load micro-ops retired that miss in the L2.LD_L2_MISSDTLB_MISS_LOADSCounts the number of load micro-ops retired that cause a DTLB miss.UTLB_MISS_LOADSCounts the number of load micro-ops retired that caused micro TLB miss.LD_UTLB_MISSHITMCounts the loads retired that get the data from the other core in the same tile in M state.ALL_LOADSCounts all the load micro-ops retired.ANY_LDALL_STORESCounts all the store micro-ops retired.ANY_STD_SIDE_CYCLESCounts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted.D_SIDE_WALKSCounts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included.I_SIDE_CYCLESCounts the total I-side page walks that are completed.I_SIDE_WALKSCounts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included.CYCLESCounts the total page walks completed (I-side and D-side)WALKSCounts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included.MISSCounts the number of L2 cache missesREFERENCECounts the total number of L2 cache references.LD_BLOCK_ST_FORWARDCounts the number of occurrences a retired load gets blocked because its address partially overlaps with a store (Precise Event).LD_BLOCK_STD_NOTREADYCounts the number of occurrences a retired load gets blocked because its address overlaps with a store whose data is not ready.ST_SPLITSCounts the number of occurrences a retired store that is a cache line split. Each split should be counted only once.LD_SPLITSCounts the number of occurrences a retired load that is a cache line split. Each split should be counted only once (Precise Event).LOCKCounts all the retired locked loads. It does not include stores because we would double count if we count stores.STA_FULLCounts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full.Counts any retired load that was pushed into the recycle queue for any reason.Counts any retired store that was pushed into the recycle queue for any reason.DMND_DATA_RDCounts demand cacheable data and L1 prefetch data readsDMND_RFOCounts Demand cacheable data writesDMND_CODE_RDCounts demand code reads and prefetch code readsPF_L2_RFOCounts L2 data RFO prefetches (includes PREFETCHW instruction)PF_L2_CODE_RDRequest: number of code reads generated by L2 prefetchersPARTIAL_READSCounts Partial reads (UC or WC and is valid only for Outstanding response type).PARTIAL_WRITESCounts Partial writes (UC or WT or WP and should be programmed on PMC1)UC_CODE_READSCounts UC code reads (valid only for Outstanding response type)BUS_LOCKSCounts Bus locks and split lock requestsFULL_STREAMING_STORESCounts Full streaming stores (WC and should be programmed on PMC1)PF_SOFTWARECounts Software prefetchesPF_L1_DATA_RDCounts L1 data HW prefetchesPARTIAL_STREAMING_STORESCounts Partial streaming stores (WC and should be programmed on PMC1)STREAMING_STORESCounts all streaming stores (WC and should be programmed on PMC1)PARTIAL_STREAMING_STORES:FULL_STREAMING_STORESANY_REQUESTCounts any requestANY_DATA_RDCounts Demand cacheable data and L1 prefetch data read requestsDMND_DATA_RD:PARTIAL_READS:PF_SOFTWARE:PF_L1_DATA_RDANY_RFOCounts Demand cacheable data write requestsANY_CODE_RDCounts Demand code reads and prefetch code read requestsDMND_CODE_RD:PF_L2_CODE_RDANY_READCounts any Read requestDMND_DATA_RD:DMND_RFO:DMND_CODE_RD:PF_L2_RFO:PF_L2_CODE_RD:PARTIAL_READS:UC_CODE_READS:PF_SOFTWARE:PF_L1_DATA_RDANY_PF_L2Counts any Prefetch requestsPF_L2_RFO:PF_L2_CODE_RDANY_RESPONSEAccounts for any responseDDR_NEARAccounts for data responses from DRAM Local.DDR_FARAccounts for data responses from DRAM Far.MCDRAM_NEARAccounts for data responses from MCDRAM Local.MCDRAM_FARAccounts for data responses from MCDRAM Far or Other tile L2 hit far.L2_HIT_NEAR_TILE_E_FAccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.L2_HIT_NEAR_TILE_MAccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.L2_HIT_FAR_TILE_E_FAccounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.L2_HIT_FAR_TILE_MAccounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.NON_DRAMaccounts for responses from any NON_DRAM system address. This includes MMIO transactionsMCDRAMaccounts for responses from MCDRAM (local and far)DDRaccounts for responses from DDR (local and far)L2_HIT_NEAR_TILE accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M stateL2_HIT_FAR_TILEaccounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.OUTSTANDINGoutstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.All mispredicted branches (Precise Event)Number of mispredicted conditional branch instructions retired (Precise Event)Number of mispredicted non-return branch instructions retired (Precise Event)Number of mispredicted return branch instructions retired (Precise Event)Number of mispredicted indirect call branch instructions retired (Precise Event)Number of mispredicted taken conditional branch instructions retired (Precise Event)Counts the number of mispredicted near CALL branch instructions retired.Counts the number of mispredicted near relative CALL branch instructions retired.Counts the number of mispredicted far branch instructions retired.ROB_FULLCounts the number of core cycles when no micro-ops are allocated and the ROB is fullMISPREDICTSCounts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.RAT_STALLCounts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted.NOT_DELIVEREDCounts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation.Counts the total number of core cycles when no micro-ops are allocated for any reason.MECCounts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry.Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full.Counts the number of core cycles when divider is busy. Does not imply a stall waiting for the divider.ENTRYCounts the number of times the MSROM starts a flow of uops.PREDECODE_WRONGNumber of times the prediction (from the predecode cache) for instruction length is incorrectUNHALTED_CORE_CYCLESUnhalted core cyclesUNHALTED_REFERENCE_CYCLESUnhalted reference cycleINSTRUCTION_RETIREDInstructions retired (any thread modifier supported in fixed counter)INSTRUCTIONS_RETIREDThis is an alias for INSTRUCTION_RETIRED (any thread modifier supported in fixed counter)LLC_REFERENCESLast level of cache referencesLAST_LEVEL_CACHE_REFERENCESThis is an alias for LLC_REFERENCESLLC_MISSESLast level of cache missesLAST_LEVEL_CACHE_MISSESThis is an alias for LLC_MISSESBRANCH_INSTRUCTIONS_RETIREDBranch instructions retiredBR_INST_RETIRED:ANYMISPREDICTED_BRANCH_RETIREDMispredicted branch instruction retiredBR_MISP_RETIRED:ANYICACHEInstruction fetchesUOPS_RETIREDMicro-ops retiredINST_RETIREDInstructions retiredCYCLES_DIV_BUSYCounts the number of core cycles when divider is busy.RS_FULL_STALLCounts the number of core cycles when allocation pipeline is stalled.L2_REQUESTSL2 cache requestsMACHINE_CLEARSCounts the number of times that the machine clears.BR_INST_RETIREDRetired branch instructionsBR_MISP_RETIREDCounts the number of mispredicted branch instructions retired.MS_DECODEDNumber of times the MSROM starts a flow of uops.FETCH_STALLCounts the number of core cycles the fetch stalls.BACLEARSBranch address calculatorNO_ALLOC_CYCLESFront-end allocationCPU_CLK_UNHALTEDCore cycles when core is not haltedMEM_UOPS_RETIREDCounts the number of load micro-ops retired.PAGE_WALKSNumber of page-walks executedL2_REQUESTS_REJECTCounts the number of MEC requests from the L2Q that reference a cache line were rejected.CORE_REJECT_L2QNumber of requests not accepted into the L2Q because of any L2 queue reject condition.RECYCLEQCounts the number of occurrences a retired load gets blocked.OFFCORE_RESPONSE_0Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)OFFCORE_RESPONSE_1WIntel Knights LandingknlIntel Knights MillknmALLCounts total number of DRAM CAS commands issued on this channelRDCounts all DRAM reads on this channel, incl. underfillsWRCounts number of DRAM write CAS commands on this channelUNC_M_D_CLOCKTICKSIMC Uncore DCLK countsUNC_M_CAS_COUNTDRAM RD_CAS and WR_CAS Commands.UNC_M_U_CLOCKTICKSIMC UCLK countsIntel KnightLanding IMC 0 uncoreknl_unc_imc0uncore_imc_0Intel Knights Mill IMC 0 uncoreknm_unc_imc0Intel KnightLanding IMC 1 uncoreknl_unc_imc1uncore_imc_1Intel Knights Mill IMC 1 uncoreknm_unc_imc1Intel KnightLanding IMC 2 uncoreknl_unc_imc2uncore_imc_2Intel Knights Mill IMC 2 uncoreknm_unc_imc2Intel KnightLanding IMC 3 uncoreknl_unc_imc3uncore_imc_3Intel Knights Mill IMC 3 uncoreknm_unc_imc3Intel KnightLanding IMC 4 uncoreknl_unc_imc4uncore_imc_4Intel Knights Mill IMC 4 uncoreknm_unc_imc4Intel KnightLanding IMC 5 uncoreknl_unc_imc5uncore_imc_5Intel Knights Mill IMC 5 uncoreknm_unc_imc5Intel KnightLanding IMC UCLK 0 uncoreknl_unc_imc_uclk0uncore_mc_uclk_0Intel Knights Mill IMC UCLK 0 uncoreknm_unc_imc_uclk0Intel KnightLanding IMC UCLK 1 uncoreknl_unc_imc_uclk1uncore_mc_uclk_1Intel Knights Mill IMC UCLK 1 uncoreknm_unc_imc_uclk1HIT_CLEANHit EHIT_DIRTYHit MMISS_CLEANMiss EMISS_DIRTYMiss MMISS_INVALIDMiss IMISS_GARBAGEMiss GUNC_E_U_CLOCKTICKSEDC UCLK clockticks (generic counters)UNC_E_EDC_ACCESSNumber of EDC Access Hits or Misses.UNC_E_E_CLOCKTICKSEDC ECLK clockticks (generic counters)UNC_E_RPQ_INSERTSCounts total number of EDC RPQ insersUNC_E_WPQ_INSERTSCounts total number of EDC WPQ insersIntel KnightLanding EDC_UCLK_0 uncoreknl_unc_edc_uclk0uncore_edc_uclk_0Intel Knights Mill EDC_UCLK_0 uncoreknm_unc_edc_uclk0Intel KnightLanding EDC_UCLK_1 uncoreknl_unc_edc_uclk1uncore_edc_uclk_1Intel Knights Mill EDC_UCLK_1 uncoreknm_unc_edc_uclk1Intel KnightLanding EDC_UCLK_2 uncoreknl_unc_edc_uclk2uncore_edc_uclk_2Intel Knights Mill EDC_UCLK_2 uncoreknm_unc_edc_uclk2Intel KnightLanding EDC_UCLK_3 uncoreknl_unc_edc_uclk3uncore_edc_uclk_3Intel Knights Mill EDC_UCLK_3 uncoreknm_unc_edc_uclk3Intel KnightLanding EDC_UCLK_4 uncoreknl_unc_edc_uclk4uncore_edc_uclk_4Intel Knights Mill EDC_UCLK_4 uncoreknm_unc_edc_uclk4Intel KnightLanding EDC_UCLK_5 uncoreknl_unc_edc_uclk5uncore_edc_uclk_5Intel Knights Mill EDC_UCLK_5 uncoreknm_unc_edc_uclk5Intel KnightLanding EDC_UCLK_6 uncoreknl_unc_edc_uclk6uncore_edc_uclk_6Intel Knights Mill EDC_UCLK_6 uncoreknm_unc_edc_uclk6Intel KnightLanding EDC_UCLK_7 uncoreknl_unc_edc_uclk7uncore_edc_uclk_7Intel Knights Mill EDC_UCLK_7 uncoreknm_unc_edc_uclk7Intel KnightLanding EDC_ECLK_0 uncoreknl_unc_edc_eclk0uncore_edc_eclk_0Intel Knights Mill EDC_ECLK_0 uncoreknm_unc_edc_eclk0Intel KnightLanding EDC_ECLK_1 uncoreknl_unc_edc_eclk1uncore_edc_eclk_1Intel Knights Mill EDC_ECLK_1 uncoreknm_unc_edc_eclk1Intel KnightLanding EDC_ECLK_2 uncoreknl_unc_edc_eclk2uncore_edc_eclk_2Intel Knights Mill EDC_ECLK_2 uncoreknm_unc_edc_eclk2Intel KnightLanding EDC_ECLK_3 uncoreknl_unc_edc_eclk3uncore_edc_eclk_3Intel Knights Mill EDC_ECLK_3 uncoreknm_unc_edc_eclk3Intel KnightLanding EDC_ECLK_4 uncoreknl_unc_edc_eclk4uncore_edc_eclk_4Intel Knights Mill EDC_ECLK_4 uncoreknm_unc_edc_eclk4Intel KnightLanding EDC_ECLK_5 uncoreknl_unc_edc_eclk5uncore_edc_eclk_5Intel Knights Mill EDC_ECLK_5 uncoreknm_unc_edc_eclk5Intel KnightLanding EDC_ECLK_6 uncoreknl_unc_edc_eclk6uncore_edc_eclk_6Intel Knights Mill EDC_ECLK_6 uncoreknm_unc_edc_eclk6Intel KnightLanding EDC_ECLK_7 uncoreknl_unc_edc_eclk7uncore_edc_eclk_7Intel Knights Mill EDC_ECLK_7 uncoreknm_unc_edc_eclk7DATA_READData read requestsWRITEWrite requests. Includes all write transactions (cached, uncached)REMOTE_SNOOPExternal snoop requestANYAny requestM_STATELines in M stateE_STATELines in E stateS_STATELines in S stateF_STATELines in F stateLOCALVictimized Lines matching the NID filter.REMOTEVictimized Lines does not matching the NID.IRQInternal starved with IRQ.IPQInternal starved with IPQ.ISMQInternal starved with ISMQ.PRQInternal starved with PRQ.IRQ_REJIRQ rejectedPRQ_REJPRQ rejectedAD_REQ_VN0AD RequestAD_RSP_VN0AD ResponseBL_RSP_VN0BL ResponseBL_WB_VN0BL WBBL_NCB_VN0BL NCBBL_NCS_VN0BL NCSAK_NON_UPIAK non upiIV_NON_UPIIV non upiANY_REJECTAny reject from request queue0SF_VICTIMSF victimSF_WAYSF wayALLOW_SNPallow snoopPA_MATCHPA match -IRQ.EVICT -SF/LLC Evictions. -PRQ. -IPQ.HIT -Hit (Not a Miss).MISS -Miss.IRQ_HIT -IRQ HIT.IRQ_MISS -IRQ MISS.PRQ_HIT -PRQ HIT.PRQ_MISS -PRQ MISS.IPQ_HIT -IPQ HITIPQ_MISS -IPQ MISSRSPI_WAS_FSESilent Snoop EvictionWC_ALIASINGWrite Combining Aliasing.RFO_HIT_SCounts the number of times that an RFO hits in S state.CV0_PREF_VICCV0 Prefetch Victim.CV0_PREF_MISSCV0 Prefetch Miss.TGR0for Transgress 0TGR1for Transgress 1TGR2for Transgress 2TGR3for Transgress 3TGR4for Transgress 4TGR5for Transgress 5TGR6for Transgress 6TGR7for Transgress 7TGR8for Transgress 8ANY_OF_TGR0_THRU_TGR7for Transgress 0-7AD_AG0AD - Agent 0AK_AG0AK - Agent 0BL_AG0BL - Agent 0IV_AG0IV - Agent 0AD_AG1AD - Agent 1AK_AG1AK - Agent 1BL_AG1BL - Agent 1AD - AD ringAK - AK ringBL - BL ringIV - IV ringVERT - verticalHORZ - horizontalUP_EVENUP_ODDDN_EVENDN_ODDLEFT_EVENLEFT_ODDRIGHT_EVENRIGHT_ODDUPupDNdownLEFTleftRIGHTrightIV_SNP_GO_UPIV_SNP_GO_DNAD_BNCAK_BNCBL_BNCIV_BNCAD_CRDBL_CRDIVFUNC_H_U_CLOCKTICKSUncore clockticksUNC_H_INGRESS_OCCUPANCYIngress Occupancy. Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycleUNC_H_INGRESS_INSERTSIngress Allocations. Counts number of allocations per cycle into the specified Ingress queueUNC_H_INGRESS_INT_STARVEDCycles Internal StarvationUNC_H_INGRESS_RETRY_IRQ0_REJECTIngress Request Queue RejectsUNC_H_INGRESS_RETRY_IRQ01_REJECTUNC_H_INGRESS_RETRY_PRQ0_REJECTUNC_H_INGRESS_RETRY_PRQ1_REJECTUNC_H_INGRESS_RETRY_IPQ0_REJECTUNC_H_INGRESS_RETRY_IPQ1_REJECTUNC_H_INGRESS_RETRY_ISMQ0_REJECTISMQ RejectsUNC_H_INGRESS_RETRY_REQ_Q0_RETRYREQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)UNC_H_INGRESS_RETRY_REQ_Q1_RETRYUNC_H_INGRESS_RETRY_ISMQ0_RETRYISMQ retriesUNC_H_INGRESS_RETRY_OTHER0_RETRYOther Queue RetriesUNC_H_INGRESS_RETRY_OTHER1_RETRYUNC_H_SF_LOOKUPCache Lookups. Counts the number of times the LLC was accessed.UNC_H_CACHE_LINES_VICTIMIZEDUNC_H_TOR_INSERTSCounts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.UNC_H_TOR_OCCUPANCYFor each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subeventUNC_H_MISCMiscellaneous events in the ChaUNC_H_AG0_AD_CRD_ACQUIREDCMS Agent0 AD Credits Acquired.UNC_H_AG0_AD_CRD_ACQUIRED_EXTUNC_H_AG0_AD_CRD_OCCUPANCYCMS Agent0 AD Credits Occupancy.UNC_H_AG0_AD_CRD_OCCUPANCY_EXTCMS Agent0 AD Credits Acquired For Transgress.UNC_H_AG1_AD_CRD_ACQUIREDCMS Agent1 AD Credits Acquired .UNC_H_AG1_AD_CRD_ACQUIRED_EXTUNC_H_AG1_AD_CRD_OCCUPANCYCMS Agent1 AD Credits Occupancy.UNC_H_AG1_AD_CRD_OCCUPANCY_EXTUNC_H_AG0_BL_CRD_ACQUIREDCMS Agent0 BL Credits Acquired.UNC_H_AG0_BL_CRD_ACQUIRED_EXTUNC_H_AG0_BL_CRD_OCCUPANCYCMS Agent0 BL Credits Occupancy.UNC_H_AG0_BL_CRD_OCCUPANCY_EXTUNC_H_AG1_BL_CRD_ACQUIREDCMS Agent1 BL Credits Acquired.UNC_H_AG1_BL_CRD_ACQUIRED_EXTUNC_H_AG1_BL_CRD_OCCUPANCYCMS Agent1 BL Credits Occupancy.UNC_H_AG1_BL_CRD_OCCUPANCY_EXTUNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_ADStall on No AD Transgress Credits.UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXTUNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_ADUNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXTUNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BLUNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXTUNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BLUNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXTUNC_H_EGRESS_VERT_OCCUPANCYCMS Vert Egress Occupancy.UNC_H_EGRESS_VERT_INSERTSCMS Vert Egress Allocations.UNC_H_EGRESS_VERT_CYCLES_FULLCycles CMS Vertical Egress Queue Is Full.UNC_H_EGRESS_VERT_CYCLES_NECycles CMS Vertical Egress Queue Is Not Empty.UNC_H_EGRESS_VERT_NACKCMS Vertical Egress NACKs.UNC_H_EGRESS_VERT_STARVEDCMS Vertical Egress Injection Starvation.UNC_H_EGRESS_VERT_ADS_USEDCMS Vertical ADS Used.UNC_H_EGRESS_VERT_BYPASSCMS Vertical Egress Bypass.UNC_H_EGRESS_HORZ_OCCUPANCYCMS Horizontal Egress Occupancy.UNC_H_EGRESS_HORZ_INSERTSCMS Horizontal Egress Inserts.UNC_H_EGRESS_HORZ_CYCLES_FULLCycles CMS Horizontal Egress Queue is Full.UNC_H_EGRESS_HORZ_CYCLES_NECycles CMS Horizontal Egress Queue is Not Empty.UNC_H_EGRESS_HORZ_NACKCMS Horizontal Egress NACKs.UNC_H_EGRESS_HORZ_STARVEDCMS Horizontal Egress Injection Starvation.UNC_H_EGRESS_HORZ_ADS_USEDCMS Horizontal ADS Used.UNC_H_EGRESS_HORZ_BYPASSCMS Horizontal Egress Bypass.UNC_H_RING_BOUNCES_VERTNumber of incoming messages from the Vertical ring that were bounced, by ring type.UNC_H_RING_BOUNCES_HORZNumber of incoming messages from the Horizontal ring that were bounced, by ring type.UNC_H_RING_SINK_STARVED_VERTVertical ring sink starvation count.UNC_H_RING_SINK_STARVED_HORZHorizontal ring sink starvation count.UNC_H_RING_SRC_THRTCounts cycles in throttle mode.UNC_H_FAST_ASSERTEDCounts cycles source throttling is addertedUNC_H_VERT_RING_AD_IN_USECounts the number of cycles that the Vertical AD ring is being used at this ring stop.UNC_H_HORZ_RING_AD_IN_USECounts the number of cycles that the Horizontal AD ring is being used at this ring stop.UNC_H_VERT_RING_AK_IN_USECounts the number of cycles that the Vertical AK ring is being used at this ring stop.UNC_H_HORZ_RING_AK_IN_USECounts the number of cycles that the Horizontal AK ring is being used at this ring stop.UNC_H_VERT_RING_BL_IN_USECounts the number of cycles that the Vertical BL ring is being used at this ring stop.UNC_H_HORZ_RING_BL_IN_USECounts the number of cycles that the Horizontal BL ring is being used at this ring stop.UNC_H_VERT_RING_IV_IN_USECounts the number of cycles that the Vertical IV ring is being used at this ring stop.UNC_H_HORZ_RING_IV_IN_USECounts the number of cycles that the Horizontal IV ring is being used at this ring stop.UNC_H_EGRESS_ORDERINGCounts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements.UNC_H_TG_INGRESS_OCCUPANCYTransgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh.UNC_H_TG_INGRESS_INSERTSTransgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh.UNC_H_TG_INGRESS_BYPASSTransgress Ingress Bypass. Number of packets bypassing the CMS Ingress.UNC_H_TG_INGRESS_CRD_STARVEDTransgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.UNC_H_TG_INGRESS_BUSY_STARVEDTransgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority.Intel KnightLanding CHA 0 uncoreknl_unc_cha0uncore_cha_0Intel Knights Mill CHA 0 uncoreknm_unc_cha0Intel KnightLanding CHA 1 uncoreknl_unc_cha1uncore_cha_1Intel Knights Mill CHA 1 uncoreknm_unc_cha1Intel KnightLanding CHA 2 uncoreknl_unc_cha2uncore_cha_2Intel Knights Mill CHA 2 uncoreknm_unc_cha2Intel KnightLanding CHA 3 uncoreknl_unc_cha3uncore_cha_3Intel Knights Mill CHA 3 uncoreknm_unc_cha3Intel KnightLanding CHA 4 uncoreknl_unc_cha4uncore_cha_4Intel Knights Mill CHA 4 uncoreknm_unc_cha4Intel KnightLanding CHA 5 uncoreknl_unc_cha5uncore_cha_5Intel Knights Mill CHA 5 uncoreknm_unc_cha5Intel KnightLanding CHA 6 uncoreknl_unc_cha6uncore_cha_6Intel Knights Mill CHA 6 uncoreknm_unc_cha6Intel KnightLanding CHA 7 uncoreknl_unc_cha7uncore_cha_7Intel Knights Mill CHA 7 uncoreknm_unc_cha7Intel KnightLanding CHA 8 uncoreknl_unc_cha8uncore_cha_8Intel Knights Mill CHA 8 uncoreknm_unc_cha8Intel KnightLanding CHA 9 uncoreknl_unc_cha9uncore_cha_9Intel Knights Mill CHA 9 uncoreknm_unc_cha9Intel KnightLanding CHA 10 uncoreknl_unc_cha10uncore_cha_10Intel Knights Mill CHA 10 uncoreknm_unc_cha10Intel KnightLanding CHA 11 uncoreknl_unc_cha11uncore_cha_11Intel Knights Mill CHA 11 uncoreknm_unc_cha11Intel KnightLanding CHA 12 uncoreknl_unc_cha12uncore_cha_12Intel Knights Mill CHA 12 uncoreknm_unc_cha12Intel KnightLanding CHA 13 uncoreknl_unc_cha13uncore_cha_13Intel Knights Mill CHA 13 uncoreknm_unc_cha13Intel KnightLanding CHA 14 uncoreknl_unc_cha14uncore_cha_14Intel Knights Mill CHA 14 uncoreknm_unc_cha14Intel KnightLanding CHA 15 uncoreknl_unc_cha15uncore_cha_15Intel Knights Mill CHA 15 uncoreknm_unc_cha15Intel KnightLanding CHA 16 uncoreknl_unc_cha16uncore_cha_16Intel Knights Mill CHA 16 uncoreknm_unc_cha16Intel KnightLanding CHA 17 uncoreknl_unc_cha17uncore_cha_17Intel Knights Mill CHA 17 uncoreknm_unc_cha17Intel KnightLanding CHA 18 uncoreknl_unc_cha18uncore_cha_18Intel Knights Mill CHA 18 uncoreknm_unc_cha18Intel KnightLanding CHA 19 uncoreknl_unc_cha19uncore_cha_19Intel Knights Mill CHA 19 uncoreknm_unc_cha19Intel KnightLanding CHA 20 uncoreknl_unc_cha20uncore_cha_20Intel Knights Mill CHA 20 uncoreknm_unc_cha20Intel KnightLanding CHA 21 uncoreknl_unc_cha21uncore_cha_21Intel Knights Mill CHA 21 uncoreknm_unc_cha21Intel KnightLanding CHA 22 uncoreknl_unc_cha22uncore_cha_22Intel Knights Mill CHA 22 uncoreknm_unc_cha22Intel KnightLanding CHA 23 uncoreknl_unc_cha23uncore_cha_23Intel Knights Mill CHA 23 uncoreknm_unc_cha23Intel KnightLanding CHA 24 uncoreknl_unc_cha24uncore_cha_24Intel Knights Mill CHA 24 uncoreknm_unc_cha24Intel KnightLanding CHA 25 uncoreknl_unc_cha25uncore_cha_25Intel Knights Mill CHA 25 uncoreknm_unc_cha25Intel KnightLanding CHA 26 uncoreknl_unc_cha26uncore_cha_26Intel Knights Mill CHA 26 uncoreknm_unc_cha26Intel KnightLanding CHA 27 uncoreknl_unc_cha27uncore_cha_27Intel Knights Mill CHA 27 uncoreknm_unc_cha27Intel KnightLanding CHA 28 uncoreknl_unc_cha28uncore_cha_28Intel Knights Mill CHA 28 uncoreknm_unc_cha28Intel KnightLanding CHA 29 uncoreknl_unc_cha29uncore_cha_29Intel Knights Mill CHA 29 uncoreknm_unc_cha29Intel KnightLanding CHA 30 uncoreknl_unc_cha30uncore_cha_30Intel Knights Mill CHA 30 uncoreknm_unc_cha30Intel KnightLanding CHA 31 uncoreknl_unc_cha31uncore_cha_31Intel Knights Mill CHA 31 uncoreknm_unc_cha31Intel KnightLanding CHA 32 uncoreknl_unc_cha32uncore_cha_32Intel Knights Mill CHA 32 uncoreknm_unc_cha32Intel KnightLanding CHA 33 uncoreknl_unc_cha33uncore_cha_33Intel Knights Mill CHA 33 uncoreknm_unc_cha33Intel KnightLanding CHA 34 uncoreknl_unc_cha34uncore_cha_34Intel Knights Mill CHA 34 uncoreknm_unc_cha34Intel KnightLanding CHA 35 uncoreknl_unc_cha35uncore_cha_35Intel Knights Mill CHA 35 uncoreknm_unc_cha35Intel KnightLanding CHA 36 uncoreknl_unc_cha36uncore_cha_36Intel Knights Mill CHA 36 uncoreknm_unc_cha36Intel KnightLanding CHA 37 uncoreknl_unc_cha37uncore_cha_37Intel Knights Mill CHA 37 uncoreknm_unc_cha37CBO_IDICBO_NCBCBO_NCSALLAllAD_0AK_0BL_0AD_1AK_1BL_1AK_CRD_0AK_CRD_1UNC_M2P_INGRESS_CYCLES_NEIngress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not emptyUNC_M2P_EGRESS_CYCLES_NEEgress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not emptyUNC_M2P_EGRESS_INSERTSEgress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queueUNC_M2P_EGRESS_CYCLES_FULLEgress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full[UNC_R2PCIE=0x%lx event=0x%x umask=0x%x en=%d inv=%d edge=%d thres=%d] %s Intel Knights Landing M2PCIe uncoreknl_unc_m2pcieuncore_m2pcieIntel Knights Mill M2PCIe uncoreknm_unc_m2pcieHITReferences per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitectureMISSESReferences per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitectureACCESSESReferences per ICache line. This event counts differently than Intel processors based on Silvermont microarchitectureALLRequests rejected by the XQRECEIVEDHardware interrupts receivedPENDING_AND_MASKEDCycles pending interrupts are maskedALL_BRANCHESRetired mispredicted branch instructions (Precise Event)JCCRetired mispredicted conditional branch instructions (Precise Event)TAKEN_JCCRetired mispredicted conditional branch instructions that were taken (Precise Event)IND_CALLRetired mispredicted near indirect call instructions (Precise Event)RETURNRetired mispredicted near return instructions (Precise Event)NON_RETURN_INDRetired mispredicted instructions of near indirect Jmp or near indirect call (Precise Event)PREDECODE_WRONGDecode restrictions due to predicting wrong instruction lengthLOAD_PAGE_SPLITLoad uops that split a page (Precise Event)STORE_PAGE_SPLITStore uops that split a page (Precise Event)ANY_PCounts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.RESOURCE_FULLUnfilled issue slots per cycle because of a full resource in the backendRECOVERYUnfilled issue slots per cycle to recoverANYUnfilled issue slots per cycleMISSITLB missesREFERENCEL2 cache requestsL2 cache request missesL1_HITLoad uops retired that hit L1 data cache (Precise Event)L1_MISSLoad uops retired that missed L1 data cache (Precise Event)L2_HITLoad uops retired that hit L2 (Precise Event)L2_MISSLoad uops retired that missed L2 (Precise Event)HITMMemory uop retired where cross core or cross module HITM occurred (Precise Event)WCB_HITLoads retired that hit WCB (Precise Event)DRAM_HITLoads retired that came from DRAM (Precise Event)ALL_BLOCKLoads blocked (Precise Event)UTLB_MISSLoads blocked because address in not in the UTLB (Precise Event)STORE_FORWARDLoads blocked due to store forward restriction (Precise Event)DATA_UNKNOWNLoads blocked due to store data not ready (Precise Event)4K_ALIASLoads blocked because address has 4k partial address false dependence (Precise Event)DIRTY_EVICTIONL1 Cache evictions for dirty dataCycles a divider is busyIDIVCycles the integer divide unit is busyFPDIVCycles the FP divide unit is busyMS_ENTRYMS decode startsUops retired (Precise Event)MSMS uops retired (Precise Event)DMND_DATA_RDRequest: number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetchesDMND_RFORequest: number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetchesDMND_CODE_RDRequest: number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetchesWBRequest: number of writebacks (modified to exclusive) transactionsPF_DATA_RDRequest: number of data cacheline reads generated by L2 prefetcherPF_RFORequest: number of RFO requests generated by L2 prefetcherPARTIAL_READSRequest: number of partil readsPARTIAL_WRITESRequest: number of partial writesUC_CODE_READSRequest: number of uncached code readsBUS_LOCKSRequest: number of bus lock and split lock requestsFULL_STRM_STRequest: number of streaming store requests for full cachelineSW_PFRequest: number of cacheline requests due to software prefetchPF_L1_DATA_RDRequest: number of data cacheline reads generated by L1 data prefetcherPARTIAL_STRM_STRequest: number of streaming store requests for partial cachelineSTRM_STRequest: number of streaming store requests for partial or full cachelineFULL_STRM_ST:PARTIAL_STRM_STANY_REQUESTRequest: combination of all request umasksANY_PF_DATA_RDRequest: number of prefetch data readsPF_DATA_RD:SW_PF:PF_L1_DATA_RDANY_RFORequest: number of RFODMND_RFO:PF_RFOANY_RESPONSEResponse: any response typeSupplier: counts L2 hitsL2_MISS_SNP_MISS_OR_NO_SNOOP_NEEDEDSnoop: counts number true misses to this processor module for which a snoop request missed the other processor module or no snoop was neededL2_MISS_HIT_OTHER_CORE_NO_FWDSnoop: counts number of times a snoop request hits the other processor module but no data forwarding is neededL2_MISS_HITM_OTHER_CORESnoop: counts number of times a snoop request hits in the other processor module or other core's L1 where a modified copy (M-state) is foundL2_MISS_SNP_NON_DRAMSnoop: counts number of times target was a non-DRAM system address. This includes MMIO transactionsL2_MISS_SNP_ANYSnoop: any snoop reasonL2_MISS_SNP_MISS_OR_NO_SNOOP_NEEDED:L2_MISS_HIT_OTHER_CORE_NO_FWD:L2_MISS_HITM_OTHER_CORE:L2_MISS_SNP_NON_DRAMOUTSTANDINGOutstanding request: counts weighted cycles of outstanding offcore requests of the request type specified in the bits 15:0 of offcore_response from the time the XQ receives the request and any response received. Bits 37:16 must be set to 0. This is only available for offcore_response_0SMCSelf-Modifying Code detectedMEMORY_ORDERINGMachine cleas due to memory ordering issueFP_ASSISTMachine clears due to FP assistsDISAMBIGUATIONMachine clears due to memory disambiguationAll machine clearsRetired branch instructions (Precise Event)ALL_TAKEN_BRANCHESRetired conditional branch instructions (Precise Event)Retired conditional branch instructions that were taken (Precise Event)CALLRetired near call instructions (Precise Event)REL_CALLRetired near relative call instructions (Precise Event)Retired near indirect call instructions (Precise Event)Retired near return instructions (Precise Event)Retired instructions of near indirect Jmp or call (Precise Event)FAR_BRANCHRetired far branch instructions (Precise Event)ICACHE_FILL_PENDING_CYCLESCycles where code-fetch is stalled and an ICache miss is outstanding. This is not the same as an ICache MissUops requested but not-delivered to the back-end per cycleALL_LOADSLoad uops retired (Precise Event)ALL_STORESStore uops retired (Precise Event)Memory uops retired (Precise Event)DTLB_MISS_LOADSLoad uops retired that missed the DTLB (Precise Event)DTLB_MISS_STORESStore uops retired that missed the DTLB (Precise Event)DTLB_MISSMemory uops retired that missed the DTLB (Precise Event)LOCK_LOADSLocked load uops retired (Precise Event)SPLIT_LOADSLoad uops retired that split a cache-line (Precise Event)SPLIT_STORESStores uops retired that split a cache-line (Precise Event)SPLITMemory uops retired that split a cache-line (Precise Event)Uops issued to the back end per cycleRequests rejected by the L2Q D_SIDE_CYCLESDuration of D-side page-walks in cyclesI_SIDE_CYCLESDuration of I-side pagewalks in cyclesCYCLESDuration of page-walks in cyclesBACLEARs asserted for any branch typeBACLEARs asserted for return branchCONDBACLEARs asserted for conditional branchCORECore cycles when core is not halted (Fixed event)REF_TSCReference cycles when core is not halted (Fixed event)CORE_PCore cycles when core is not haltedREFReference cycles when core is not haltedICACHEL2_REJECT_XQHW_INTERRUPTSBR_MISP_RETIREDDECODE_RESTRICTIONMISALIGN_MEM_REFINST_RETIREDInstructions retired (Precise Event)INSTRUCTION_RETIREDNumber of instructions retiredISSUE_SLOTS_NOT_CONSUMEDITLBLONGEST_LAT_CACHEMEM_LOAD_UOPS_RETIREDLD_BLOCKSDL1CYCLES_DIV_BUSYMS_DECODEDUOPS_RETIREDOFFCORE_RESPONSE_1Offcore response event (must provide at least one request type and either any_response or any combination of supplier + snoop)MACHINE_CLEARSBR_INST_RETIREDFETCH_STALLUOPS_NOT_DELIVEREDMISPREDICTED_BRANCH_RETIREDNumber of mispredicted branch instructions retiredBR_MISP_RETIRED:ALL_BRANCHESINSTRUCTIONS_RETIREDMEM_UOPS_RETIREDUOPS_ISSUEDOFFCORE_RESPONSE_0UNHALTED_REFERENCE_CYCLESUnhalted reference cycles. Ticks at constant reference frequencyBRANCH_INSTRUCTIONS_RETIREDNumber of branch instructions retiredBR_INST_RETIRED:ALL_BRANCHESCORE_REJECT_L2QPAGE_WALKSBACLEARSCPU_CLK_UNHALTEDUNHALTED_CORE_CYCLESCore clock cycles whenever the clock signal on the specific core is running (not halted)\_Intel GoldmontglmTC_deliver_modeThe duration (in clock cycles) of the operating modes of the trace cache and decode engine in the processor packageDDBoth logical CPUs in deliver modeDBLogical CPU 0 in deliver mode and logical CPU 1 in build modeDILogical CPU 0 in deliver mode and logical CPU 1 either halted, under machine clear condition, or transitioning to a long microcode flowBDLogical CPU 0 in build mode and logical CPU 1 is in deliver modeBBBoth logical CPUs in build modeBILogical CPU 0 in build mode and logical CPU 1 either halted, under machine clear condition, or transitioning to a long microcode flowIDLogical CPU 0 either halted, under machine clear condition, or transitioning to a long microcode flow, and logical CPU 1 in deliver modeIBLogical CPU 0 either halted, under machine clear condition, or transitioning to a long microcode flow, and logical CPU 1 in build modeBPU_fetch_requestInstruction fetch requests by the Branch Prediction UnitTCMISSTrace cache lookup missITLB_referenceTranslations using the Instruction Translation Look-Aside BufferHITITLB hitMISSITLB missHIT_UCUncacheable ITLB hitmemory_cancelCanceling of various types of requests in the Data cache Address Control unit (DAC)ST_RB_FULLReplayed because no store request buffer is available64K_CONFConflicts due to 64K aliasingmemory_completeCompletions of a load split, store split, uncacheable (UC) split, or UC loadLSCLoad split completed, excluding UC/WC loadsSSCAny split stores completedload_port_replayReplayed events at the load portSPLIT_LDSplit loadstore_port_replayReplayed events at the store portSPLIT_STSplit storeMOB_load_replayCount of times the memory order buffer (MOB) caused a load operation to be replayedNO_STAReplayed because of unknown store addressNO_STDReplayed because of unknown store dataPARTIAL_DATAReplayed because of partially overlapped data access between the load and store operationsUNALGN_ADDRReplayed because the lower 4 bits of the linear address do not match between the load and store operationspage_walk_typePage walks that the page miss handler (PMH) performsDTMISSPage walk for a data TLB miss (load or store)ITMISSPage walk for an instruction TLB missBSQ_cache_referenceCache references (2nd or 3rd level caches) as seen by the bus unit. Read types include both load and RFO, and write types include writebacks and evictionsRD_2ndL_HITSRead 2nd level cache hit SharedRD_2ndL_HITERead 2nd level cache hit ExclusiveRD_2ndL_HITMRead 2nd level cache hit ModifiedRD_3rdL_HITSRead 3rd level cache hit SharedRD_3rdL_HITERead 3rd level cache hit ExclusiveRD_3rdL_HITMRead 3rd level cache hit ModifiedRD_2ndL_MISSRead 2nd level cache missRD_3rdL_MISSRead 3rd level cache missWR_2ndL_MISSA writeback lookup from DAC misses the 2nd level cache (unlikely to happen)IOQ_allocationCount of various types of transactions on the bus. A count is generated each time a transaction is allocated into the IOQ that matches the specified mask bits. An allocated entry can be a sector (64 bytes) or a chunk of 8 bytes. Requests are counted once per retry. All 'TYPE_BIT*' event-masks together are treated as a single 5-bit valueTYPE_BIT0Bus request type (bit 0)TYPE_BIT1Bus request type (bit 1)TYPE_BIT2Bus request type (bit 2)TYPE_BIT3Bus request type (bit 3)TYPE_BIT4Bus request type (bit 4)ALL_READCount read entriesALL_WRITECount write entriesMEM_UCCount UC memory access entriesMEM_WCCount WC memory access entriesMEM_WTCount write-through (WT) memory access entriesMEM_WPCount write-protected (WP) memory access entriesMEM_WBCount WB memory access entriesOWNCount all store requests driven by processor, as opposed to other processor or DMAOTHERCount all requests driven by other processors or DMAPREFETCHInclude HW and SW prefetch requests in the countIOQ_active_entriesNumber of entries (clipped at 15) in the IOQ that are active. An allocated entry can be a sector (64 bytes) or a chunk of 8 bytes. This event must be programmed in conjunction with IOQ_allocation. All 'TYPE_BIT*' event-masks together are treated as a single 5-bit valueFSB_data_activityCount of DRDY or DBSY events that occur on the front side busDRDY_DRVCount when this processor drives data onto the bus. Includes writes and implicit writebacksDRDY_OWNCount when this processor reads data from the bus. Includes loads and some PIC transactions. Count DRDY events that we drive. Count DRDY events sampled that we ownDRDY_OTHERCount when data is on the bus but not being sampled by the processor. It may or may not be driven by this processorDBSY_DRVCount when this processor reserves the bus for use in the next bus cycle in order to drive dataDBSY_OWNCount when some agent reserves the bus for use in the next bus cycle to drive data that this processor will sampleDBSY_OTHERCount when some agent reserves the bus for use in the next bus cycle to drive data that this processor will NOT sample. It may or may not be being driven by this processorBSQ_allocationAllocations in the Bus Sequence Unit (BSQ). The event mask bits consist of four sub-groups: request type, request length, memory type, and a sub-group consisting mostly of independent bits (5 through 10). Must specify a mask for each sub-groupREQ_TYPE0Along with REQ_TYPE1, request type encodings are: 0 - Read (excludes read invalidate), 1 - Read invalidate, 2 - Write (other than writebacks), 3 - Writeback (evicted from cache)REQ_TYPE1Along with REQ_TYPE0, request type encodings are: 0 - Read (excludes read invalidate), 1 - Read invalidate, 2 - Write (other than writebacks), 3 - Writeback (evicted from cache)REQ_LEN0Along with REQ_LEN1, request length encodings are: 0 - zero chunks, 1 - one chunk, 3 - eight chunksREQ_LEN1Along with REQ_LEN0, request length encodings are: 0 - zero chunks, 1 - one chunk, 3 - eight chunksREQ_IO_TYPERequest type is input or outputREQ_LOCK_TYPERequest type is bus lockREQ_CACHE_TYPERequest type is cacheableREQ_SPLIT_TYPERequest type is a bus 8-byte chunk split across an 8-byte boundaryREQ_DEM_TYPE0: Request type is HW.SW prefetch. 1: Request type is a demandREQ_ORD_TYPERequest is an ordered typeMEM_TYPE0Along with MEM_TYPE1 and MEM_TYPE2, memory type encodings are: 0 - UC, 1 - USWC, 4- WT, 5 - WP, 6 - WBMEM_TYPE1Along with MEM_TYPE0 and MEM_TYPE2, memory type encodings are: 0 - UC, 1 - USWC, 4- WT, 5 - WP, 6 - WBMEM_TYPE2Along with MEM_TYPE0 and MEM_TYPE1, memory type encodings are: 0 - UC, 1 - USWC, 4- WT, 5 - WP, 6 - WBBSQ_active_entriesNumber of BSQ entries (clipped at 15) currently active (valid) which meet the subevent mask criteria during allocation in the BSQ. Active request entries are allocated on the BSQ until de-allocated. De-allocation of an entry does not necessarily imply the request is filled. This event must be programmed in conjunction with BSQ_allocationSSE_input_assistNumber of times an assist is requested to handle problems with input operands for SSE/SSE2/SSE3 operations; most notably denormal source operands when the DAZ bit isn't setALLCount assists for SSE/SSE2/SSE3 uopspacked_SP_uopNumber of packed single-precision uopsCount all uops operating on packed single-precisions operandsTAG0Tag this event with tag bit 0 for retirement counting with execution_eventTAG1Tag this event with tag bit 1 for retirement counting with execution_eventTAG2Tag this event with tag bit 2 for retirement counting with execution_eventTAG3Tag this event with tag bit 3 for retirement counting with execution_eventpacked_DP_uopNumber of packed double-precision uopsCount all uops operating on packed double-precisions operandsscalar_SP_uopNumber of scalar single-precision uopsCount all uops operating on scalar single-precisions operandsscalar_DP_uopNumber of scalar double-precision uopsCount all uops operating on scalar double-precisions operands64bit_MMX_uopNumber of MMX instructions which operate on 64-bit SIMD operandsCount all uops operating on 64-bit SIMD integer operands in memory or MMX registers128bit_MMX_uopNumber of MMX instructions which operate on 128-bit SIMD operandsCount all uops operating on 128-bit SIMD integer operands in memory or MMX registersx87_FP_uopNumber of x87 floating-point uopsCount all x87 FP uopsTC_miscMiscellaneous events detected by the TC. The counter will count twice for each occurrenceFLUSHNumber of flushesglobal_power_eventsCounts the time during which a processor is not stoppedRUNNINGThe processor is active (includes the handling of HLT STPCLK and throttlingtc_ms_xferNumber of times that uop delivery changed from TC to MS ROMCISCA TC to MS transfer occurreduop_queue_writesNumber of valid uops written to the uop queueFROM_TC_BUILDThe uops being written are from TC build modeFROM_TC_DELIVERThe uops being written are from TC deliver modeFROM_ROMThe uops being written are from microcode ROMretired_mispred_branch_typeNumber of retiring mispredicted branches by typeCONDITIONALConditional jumpsCALLIndirect call branchesRETURNReturn branchesINDIRECTReturns, indirect calls, or indirect jumpsretired_branch_typeNumber of retiring branches by typeresource_stallOccurrences of latency or stalls in the AllocatorSBFULLA stall due to lack of store buffersWC_BufferNumber of Write Combining Buffer operationsWCB_EVICTSWC Buffer evictions of all causesWCB_FULL_EVICTWC Buffer eviction; no WC buffer is availableb2b_cyclesNumber of back-to-back bus cyclesBIT1bit 1BIT2bit 2BIT3bit 3BIT4bit 4BIT5bit 5BIT6bit 6bnrNumber of bus-not-ready conditionsBIT0bit 0snoopNumber of snoop hit modified bus trafficBIT7bit 7responseCount of different types of responsesBIT8bit 8BIT9bit 9front_end_eventNumber of retirements of tagged uops which are specified through the front-end tagging mechanismNBOGUSThe marked uops are not bogusBOGUSThe marked uops are bogusexecution_eventNumber of retirements of tagged uops which are specified through the execution tagging mechanism. The event-mask allows from one to four types of uops to be taggedNBOGUS0NBOGUS1NBOGUS2NBOGUS3BOGUS0BOGUS1BOGUS2BOGUS3replay_eventNumber of retirements of tagged uops which are specified through the replay tagging mechanismL1_LD_MISSVirtual mask for L1 cache load miss replaysL2_LD_MISSVirtual mask for L2 cache load miss replaysDTLB_LD_MISSVirtual mask for DTLB load miss replaysDTLB_ST_MISSVirtual mask for DTLB store miss replaysDTLB_ALL_MISSVirtual mask for all DTLB miss replaysBR_MSPVirtual mask for tagged mispredicted branch replaysMOB_LD_REPLAYVirtual mask for MOB load replaysSP_LD_RETVirtual mask for split load replays. Use with load_port_replay eventSP_ST_RETVirtual mask for split store replays. Use with store_port_replay eventinstr_retiredNumber of instructions retired during a clock cycleNBOGUSNTAGNon-bogus instructions that are not taggedNBOGUSTAGNon-bogus instructions that are taggedBOGUSNTAGBogus instructions that are not taggedBOGUSTAGBogus instructions that are taggeduops_retiredNumber of uops retired during a clock cycleuops_typeThis event is used in conjunction with with the front-end mechanism to tag load and store uopsTAGLOADSThe uop is a load operationTAGSTORESThe uop is a store operationbranch_retiredNumber of retirements of a branchMMNPBranch not-taken predictedMMNMBranch not-taken mispredictedMMTPBranch taken predictedMMTMBranch taken mispredictedmispred_branch_retiredNumber of retirements of mispredicted IA-32 branch instructionsThe retired instruction is not bogusx87_assistNumber of retirements of x87 instructions that required special handlingFPSUHandle FP stack underflowFPSOHandle FP stack overflowPOAOHandle x87 output overflowPOAUHandle x87 output underflowPREAHandle x87 input assistmachine_clearNumber of occurrences when the entire pipeline of the machine is clearedCLEARCounts for a portion of the many cycles while the machine is cleared for any cause. Use edge-triggering for this bit only to get a count of occurrences versus a durationMOCLEARIncrements each time the machine is cleared due to memory ordering issuesSMCLEARIncrements each time the machine is cleared due to self-modifying code issuesinstr_completedInstructions that have completed and retired during a clock cycle (models 3, 4, 6 only)Non-bogus instructionsBogus instructionsumonitor at priv level 1, 2, 3kmonitor at priv level 0cmplcomplementeedgethrevent threshold in range [0-15][0x%lx 0x%lx 0x%lx usr=%d os=%d tag_ena=%d tag_val=%d evmask=0x%x evsel=0x%x escr_sel=0x%x comp=%d cmpl=%d thr=%d e=%d] %s %s:%s:%s=%lug"??pmu: %s event%d: :: no name (prev event was %s) pmu: %s event%d: %s :: no description pmu: %s event%d:%s umask%d: %s :: no description pmu: %s event%d:%s umask%d: %s :: invalid bit field pmu: %s event%d:%s :: more than one default umask pmu: %s event%d:%s :: no event mask end-marker Pentium4netburstPentium4 (Prescott)netburst_pL2_INVALIDInvalid line from L2L2_SHAREDShared-state line from L2L2_EXCLUSIVEExclusive-state line from L2L2_OWNEDOwned-state line from L2L2_MODIFIEDModified-state line from L2ALLShared, Exclusive, Owned, Modified State RefillsINVALIDInvalidSHAREDSharedEXCLUSIVEExclusiveOWNEDOwnedMODIFIEDModifiedInvalid, Shared, Exclusive, Owned, ModifiedDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2DATA_CACHE_REFILLS_FROM_SYSTEMData Cache Refills from SystemDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITL1 DTLB Miss and L2 DTLB HitL1_DTLB_AND_L2_DTLB_MISSL1 DTLB and L2 DTLB MissMISALIGNED_ACCESSESMisaligned AccessesCPU_CLK_UNHALTEDCPU Clocks not HaltedINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss and L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissRETIRED_INSTRUCTIONSRetired Instructions (includes exceptions, interrupts, resyncs)RETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch Resyncs (only non-control transfer branches)INTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenAMD64 K7amd64_k7OPS_ADDAdd pipe opsOPS_MULTIPLYMultiply pipe opsOPS_STOREStore pipe opsOPS_ADD_PIPE_LOAD_OPSAdd pipe load opsOPS_MULTIPLY_PIPE_LOAD_OPSMultiply pipe load opsOPS_STORE_PIPE_LOAD_OPSStore pipe load opsALLAll sub-events selectedESCSSSDSFSGSHSAll segmentsEXECUTEDThe number of locked instructions executedCYCLES_SPECULATIVE_PHASEThe number of cycles spent in speculative phaseCYCLES_NON_SPECULATIVE_PHASEThe number of cycles spent in non-speculative phase (including cache miss penalty)NON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to write-combining (WC) memory or WC buffer flushes to WB memorySTREAMING_STOREStreaming store (SS) requestsSYSTEMRefill from SystemL2_SHAREDShared-state line from L2L2_EXCLUSIVEExclusive-state line from L2L2_OWNEDOwned-state line from L2L2_MODIFIEDModified-state line from L2Shared, Exclusive, Owned, Modified State RefillsINVALIDInvalidSHAREDSharedEXCLUSIVEExclusiveOWNEDOwnedMODIFIEDModifiedInvalid, Shared, Exclusive, Owned, ModifiedSCRUBBER_ERRORScrubber errorPIGGYBACK_ERRORPiggyback scrubber errorsLOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA)DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONSData cache misses by locked instructionsCANCELLEDCancelled prefetchesATTEMPTEDPrefetch attemptsExclusive, Modified, SharedQUADWORD_WRITE_TRANSFERQuadword write transferINSTRUCTIONSIC fillDATADC fillTLB_WALKTLB fill (page table walks)SNOOPTag snoop requestCancelled requestAll non-cancelled requestsDC fill (includes possible replays, whereas event 41h does not)TLB page table walkInstructions, Data, TLB walkL2_FILLSL2 fills (victims from L1 caches, TLB page table walks and data prefetches)L2_WRITEBACKSL2 Writebacks to system.X87X87 instructionsMMX_AND_3DNOWMMX and 3DNow! instructionsPACKED_SSE_AND_SSE2Packed SSE and SSE2 instructionsSCALAR_SSE_AND_SSE2Scalar SSE and SSE2 instructionsX87, MMX(TM), 3DNow!(TM), Scalar and Packed SSE and SSE2 instructionsPOSITION_0With low op in position 0POSITION_1With low op in position 1POSITION_2With low op in position 2With low op in position 0, 1, or 2X87_RECLASS_MICROFAULTSX87 reclass microfaultsSSE_RETYPE_MICROFAULTSSSE retype microfaultsSSE_RECLASS_MICROFAULTSSSE reclass microfaultsSSE_AND_X87_MICROTRAPSSSE and x87 microtrapsHITPage hitMISSPage MissCONFLICTPage ConflictPage Hit, Miss, or ConflictCHIP_SELECTDIMM (chip select) turnaroundREAD_TO_WRITERead to write turnaroundWRITE_TO_READWrite to read turnaroundAll Memory Controller TurnaroundsHIGH_PRIORITYMemory controller high priority bypassLOW_PRIORITYMemory controller low priority bypassDRAM_INTERFACEDRAM controller interface bypassDRAM_QUEUEDRAM controller queue bypass32_BYTE_WRITES32-byte Sized Writes64_BYTE_WRITES64-byte Sized Writes32_BYTE_READS32-byte Sized Reads64_BYTE_READS64-byte Sized ReadsCLKS_CPU_ACTIVENumber of clocks CPU is active when HTC is activeCLKS_CPU_INACTIVENumber of clocks CPU clock is inactive when HTC is activeCLKS_DIE_TEMP_TOO_HIGHNumber of clocks when die temperature is higher than the software high temperature thresholdCLKS_TEMP_THRESHOLD_EXCEEDEDNumber of clocks when high temperature threshold was exceededDRAM_ECC_ERRORSNumber of correctable and Uncorrectable DRAM ECC errorsI_O_TO_I_OI/O to I/OI_O_TO_MEMI/O to MemCPU_TO_I_OCPU to I/OCPU_TO_MEMCPU to MemTO_REMOTE_NODETo remote nodeTO_LOCAL_NODETo local nodeFROM_REMOTE_NODEFrom remote nodeFROM_LOCAL_NODEFrom local nodeVICTIM_WRITEBACKVictim Block (Writeback)DCACHE_LOAD_MISSRead Block (Dcache load miss refill)SHARED_ICACHE_REFILLRead Block Shared (Icache refill)READ_BLOCK_MODIFIEDRead Block Modified (Dcache store miss refill)READ_TO_DIRTYChange to Dirty (first store to clean block already in cache)NON_POSTED_WRITE_BYTENonPosted SzWr Byte (1-32 bytes) Legacy or mapped I/O, typically 1-4 bytesNON_POSTED_WRITE_DWORDNonPosted SzWr Dword (1-16 dwords) Legacy or mapped I/O, typically 1 dwordPOSTED_WRITE_BYTEPosted SzWr Byte (1-32 bytes) Sub-cache-line DMA writes, size varies; also flushes of partially-filled Write Combining bufferPOSTED_WRITE_DWORDPosted SzWr Dword (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushesREAD_BYTE_4_BYTESSzRd Byte (4 bytes) Legacy or mapped I/OREAD_DWORD_1_16_DWORDSSzRd Dword (1-16 dwords) Block-oriented DMA reads, typically cache-line sizeREAD_MODIFY_WRITERdModWrProbe missHIT_CLEANProbe hit cleanHIT_DIRTY_NO_MEMORY_CANCELProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)HIT_DIRTY_WITH_MEMORY_CANCELProbe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_DISPLAY_REFRESH_READSUpstream display refresh readsUPSTREAM_NON_DISPLAY_REFRESH_READSUpstream non-display refresh readsUPSTREAM_WRITESUpstream writesAPERTURE_HIT_FROM_CPUGART aperture hit on access from CPUAPERTURE_HIT_FROM_IOGART aperture hit on access from I/OGART missCOMMAND_DWORD_SENTCommand dword sentDATA_DWORD_SENTData dword sentBUFFER_RELEASE_DWORD_SENTBuffer release dword sentNOP_DWORD_SENTNop dword sent (idle)DISPATCHED_FPUDispatched FPU OperationsCYCLES_NO_FPU_OPS_RETIREDCycles with no FPU Ops RetiredDISPATCHED_FPU_OPS_FAST_FLAGDispatched Fast Flag FPU OperationsSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline restart due to self-modifying codePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline restart due to probe hitLS_BUFFER_2_FULL_CYCLESLS Buffer 2 FullLOCKED_OPSLocked OperationsMEMORY_REQUESTSMemory Requests by TypeDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2 or SystemDATA_CACHE_REFILLS_FROM_SYSTEMData Cache Refills from SystemDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITL1 DTLB Miss and L2 DTLB HitL1_DTLB_AND_L2_DTLB_MISSL1 DTLB and L2 DTLB MissMISALIGNED_ACCESSESMisaligned AccessesMICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESSMicroarchitectural Late Cancel of an AccessMICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESSMicroarchitectural Early Cancel of an AccessSCRUBBER_SINGLE_BIT_ECC_ERRORSSingle-bit ECC Errors Recorded by ScrubberPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedDCACHE_MISSES_BY_LOCKED_INSTRUCTIONSDCACHE Misses by Locked InstructionsDATA_PREFETCHESData PrefetcherSYSTEM_READ_RESPONSESSystem Read Responses by Coherency StateQUADWORDS_WRITTEN_TO_SYSTEMQuadwords Written to SystemREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_FILL_WRITEBACKL2 Fill/WritebackINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss and L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissPIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBEPipeline Restart Due to Instruction Stream ProbeINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsCPU_CLK_UNHALTEDCPU Clocks not HaltedRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_MMX_AND_FP_INSTRUCTIONSRetired MMX/FP InstructionsRETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONSRetired Fastpath Double Op InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenDECODER_EMPTYDecoder EmptyDISPATCH_STALLSDispatch StallsDISPATCH_STALL_FOR_BRANCH_ABORTDispatch Stall for Branch Abort to RetireDISPATCH_STALL_FOR_SERIALIZATIONDispatch Stall for SerializationDISPATCH_STALL_FOR_SEGMENT_LOADDispatch Stall for Segment LoadDISPATCH_STALL_FOR_REORDER_BUFFER_FULLDispatch Stall for Reorder Buffer FullDISPATCH_STALL_FOR_RESERVATION_STATION_FULLDispatch Stall for Reservation Station FullDISPATCH_STALL_FOR_FPU_FULLDispatch Stall for FPU FullDISPATCH_STALL_FOR_LS_FULLDispatch Stall for LS FullDISPATCH_STALL_WAITING_FOR_ALL_QUIETDispatch Stall Waiting for All QuietDISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNCDispatch Stall for Far Transfer or Resync to RetireFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINT_MATCHESDR0 Breakpoint MatchesDR1_BREAKPOINT_MATCHESDR1 Breakpoint MatchesDR2_BREAKPOINT_MATCHESDR2 Breakpoint MatchesDR3_BREAKPOINT_MATCHESDR3 Breakpoint MatchesDRAM_ACCESSES_PAGEDRAM AccessesMEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWSMemory Controller Page Table OverflowsMEMORY_CONTROLLER_TURNAROUNDSMemory Controller TurnaroundsMEMORY_CONTROLLER_BYPASSMemory Controller Bypass Counter SaturationSIZED_BLOCKSSized BlocksTHERMAL_STATUS_AND_ECC_ERRORSThermal Status and ECC ErrorsCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCKCache Block CommandsSIZED_COMMANDSSized CommandsPROBEProbe Responses and Upstream RequestsGARTGART EventsHYPERTRANSPORT_LINK0HyperTransport Link 0 Transmit BandwidthHYPERTRANSPORT_LINK1HyperTransport Link 1 Transmit BandwidthHYPERTRANSPORT_LINK2HyperTransport Link 2 Transmit BandwidthAMD64 K8 RevBamd64_k8_revbAMD64 K8 RevCamd64_k8_revcAMD64 K8 RevDamd64_k8_revdAMD64 K8 RevEamd64_k8_reveAMD64 K8 RevFamd64_k8_revfAMD64 K8 RevGamd64_k8_revgOPS_ADDAdd pipe ops excluding load ops and SSE move opsOPS_MULTIPLYMultiply pipe ops excluding load ops and SSE move opsOPS_STOREStore pipe ops excluding load ops and SSE move opsOPS_ADD_PIPE_LOAD_OPSAdd pipe load ops and SSE move opsOPS_MULTIPLY_PIPE_LOAD_OPSMultiply pipe load ops and SSE move opsOPS_STORE_PIPE_LOAD_OPSStore pipe load ops and SSE move opsALLAll sub-events selectedSINGLE_ADD_SUB_OPSSingle precision add/subtract opsSINGLE_MUL_OPSSingle precision multiply opsSINGLE_DIV_OPSSingle precision divide/square root opsDOUBLE_ADD_SUB_OPSDouble precision add/subtract opsDOUBLE_MUL_OPSDouble precision multiply opsDOUBLE_DIV_OPSDouble precision divide/square root opsOP_TYPEOp type: 0=uops. 1=FLOPSLOW_QW_MOVE_UOPSMerging low quadword move uopsHIGH_QW_MOVE_UOPSMerging high quadword move uopsALL_OTHER_MERGING_MOVE_UOPSAll other merging move uopsALL_OTHER_MOVE_UOPSAll other move uopsSSE_BOTTOM_EXECUTING_UOPSSSE bottom-executing uops retiredSSE_BOTTOM_SERIALIZING_UOPSSSE bottom-serializing uops retiredX87_BOTTOM_EXECUTING_UOPSX87 bottom-executing uops retiredX87_BOTTOM_SERIALIZING_UOPSX87 bottom-serializing uops retiredBOTTOM_EXECUTE_CYCLESNumber of cycles a bottom-execute uop is in the FP schedulerBOTTOM_SERIALIZING_CYCLESNumber of cycles a bottom-serializing uop is in the FP schedulerESCSSSDSFSGSHSEXECUTEDThe number of locked instructions executedCYCLES_SPECULATIVE_PHASEThe number of cycles spent in speculative phaseCYCLES_NON_SPECULATIVE_PHASEThe number of cycles spent in non-speculative phase (including cache miss penalty)CYCLES_WAITINGThe number of cycles waiting for a cache hit (cache miss penalty).ADDRESS_MISMATCHESAddress mismatches (starting byte not the same).STORE_IS_SMALLER_THAN_LOADStore is smaller than load.MISALIGNEDMisaligned.SYSTEMRefill from the NorthbridgeL2_SHAREDShared-state line from L2L2_EXCLUSIVEExclusive-state line from L2L2_OWNEDOwned-state line from L2L2_MODIFIEDModified-state line from L2INVALIDInvalidSHAREDSharedEXCLUSIVEExclusiveOWNEDOwnedMODIFIEDModifiedBY_PREFETCHNTACache line evicted was brought into the cache with by a PrefetchNTA instruction.NOT_BY_PREFETCHNTACache line evicted was not brought into the cache with by a PrefetchNTA instruction.L2_4K_TLB_HITL2 4K TLB hitL2_2M_TLB_HITL2 2M TLB hitL2_1G_TLB_HITL2 1G TLB hit4K_TLB_RELOAD4K TLB reload2M_TLB_RELOAD2M TLB reload1G_TLB_RELOAD1G TLB reloadSCRUBBER_ERRORScrubber errorPIGGYBACK_ERRORPiggyback scrubber errorsLOAD_PIPE_ERRORLoad pipe errorSTORE_WRITE_PIPE_ERRORStore write pipe errorLOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA)DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONSData cache misses by locked instructionsL1_4K_TLB_HITL1 4K TLB hitL1_2M_TLB_HITL1 2M TLB hitL1_1G_TLB_HITL1 1G TLB hitSW_PREFETCH_HIT_IN_L1Software prefetch hit in the L1.SW_PREFETCH_HIT_IN_L2Software prefetch hit in L2.NON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to write-combining (WC) memory or WC buffer flushes to WB memorySTREAMING_STOREStreaming store (SS) requestsCANCELLEDCancelled prefetchesATTEMPTEDPrefetch attemptsBUFFER_0Buffer 0BUFFER_1Buffer 1BUFFER_2Buffer 2BUFFER_3Buffer 3BUFFER_4Buffer 4BUFFER_5Buffer 5BUFFER_6Buffer 6BUFFER_7Buffer 7BUFFER_8Buffer 8BUFFER_9Buffer 9DATA_ERRORData ErrorQUADWORD_WRITE_TRANSFEROctword write transferINSTRUCTIONSIC fillDATADC fillTLB_WALKTLB fill (page table walks)SNOOPTag snoop requestCancelled requestHW_PREFETCH_FROM_DCHardware prefetch from DCDC fill (includes possible replays, whereas EventSelect 041h does not)TLB page table walkL2_FILLSL2 fills (victims from L1 caches, TLB page table walks and data prefetches)L2_WRITEBACKSL2 Writebacks to system.4K_PAGE_FETCHESInstruction fetches to a 4K page.2M_PAGE_FETCHESInstruction fetches to a 2M page.INVALIDATING_PROBE_NO_IN_FLIGHTInvalidating probe that did not hit any in-flight instructions.INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHTInvalidating probe that hit one or more in-flight instructions.X87X87 instructionsMMX_AND_3DNOWMMX and 3DNow! instructionsPACKED_SSE_AND_SSE2SSE instructions (SSE, SSE2, SSE3, and SSE4A)POSITION_0With low op in position 0POSITION_1With low op in position 1POSITION_2With low op in position 2X87_RECLASS_MICROFAULTSX87 reclass microfaultsSSE_RETYPE_MICROFAULTSSSE retype microfaultsSSE_RECLASS_MICROFAULTSSSE reclass microfaultsSSE_AND_X87_MICROTRAPSSSE and x87 microtrapsHITDCT0 Page hitMISSDCT0 Page MissCONFLICTDCT0 Page ConflictDCT1_PAGE_HITDCT1 Page hitDCT1_PAGE_MISSDCT1 Page MissDCT1_PAGE_CONFLICTDCT1 Page ConflictDCT0_PAGE_TABLE_OVERFLOWDCT0 Page Table OverflowDCT1_PAGE_TABLE_OVERFLOWDCT1 Page Table OverflowDCT0_COMMAND_SLOTS_MISSEDDCT0 Command Slots MissedDCT1_COMMAND_SLOTS_MISSEDDCT1 Command Slots MissedCHIP_SELECTDCT0 DIMM (chip select) turnaroundREAD_TO_WRITEDCT0 Read to write turnaroundWRITE_TO_READDCT0 Write to read turnaroundDCT1_DIMMDCT1 DIMM (chip select) turnaroundDCT1_READ_TO_WRITE_TURNAROUNDDCT1 Read to write turnaroundDCT1_WRITE_TO_READ_TURNAROUNDDCT1 Write to read turnaroundHIGH_PRIORITYMemory controller high priority bypassLOW_PRIORITYMemory controller medium priority bypassDRAM_INTERFACEDCT0 DCQ bypassDRAM_QUEUEDCT1 DCQ bypassCLKS_DIE_TEMP_TOO_HIGHNumber of times the HTC trip point is crossedCLKS_TEMP_THRESHOLD_EXCEEDEDNumber of clocks when STC trip point activeSTC_TRIP_POINTS_CROSSEDNumber of times the STC trip point is crossedCLOCKS_HTC_P_STATE_INACTIVENumber of clocks HTC P-state is inactive.CLOCKS_HTC_P_STATE_ACTIVENumber of clocks HTC P-state is activeI_O_TO_I_OIO to IOI_O_TO_MEMIO to MemCPU_TO_I_OCPU to IOCPU_TO_MEMCPU to MemTO_REMOTE_NODETo remote nodeTO_LOCAL_NODETo local nodeFROM_REMOTE_NODEFrom remote nodeFROM_LOCAL_NODEFrom local nodeVICTIM_WRITEBACKVictim Block (Writeback)DCACHE_LOAD_MISSRead Block (Dcache load miss refill)SHARED_ICACHE_REFILLRead Block Shared (Icache refill)READ_BLOCK_MODIFIEDRead Block Modified (Dcache store miss refill)READ_TO_DIRTYChange-to-Dirty (first store to clean block already in cache)NON_POSTED_WRITE_BYTENon-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytesNON_POSTED_WRITE_DWORDNon-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORDPOSTED_WRITE_BYTEPosted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining bufferPOSTED_WRITE_DWORDPosted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushesREAD_BYTE_4_BYTESSzRd Byte (4 bytes) Legacy or mapped IOREAD_DWORD_1_16_DWORDSSzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line sizeProbe missHIT_CLEANProbe hit cleanHIT_DIRTY_NO_MEMORY_CANCELProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)HIT_DIRTY_WITH_MEMORY_CANCELProbe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_DISPLAY_REFRESH_READSUpstream display refresh/ISOC readsUPSTREAM_NON_DISPLAY_REFRESH_READSUpstream non-display refresh readsUPSTREAM_WRITESUpstream ISOC writesUPSTREAM_NON_ISOC_WRITESUpstream non-ISOC writesAPERTURE_HIT_FROM_CPUGART aperture hit on access from CPUAPERTURE_HIT_FROM_IOGART aperture hit on access from IOGART missREQUEST_HIT_TABLE_WALKGART/DEV Request hit table walk in progressDEV_HITDEV hitDEV_MISSDEV missDEV_ERRORDEV errorMULTIPLE_TABLE_WALKGART/DEV multiple table walk in progressWRITE_REQUESTSWrite requests sent to the DCTREAD_REQUESTSRead requests (including prefetch requests) sent to the DCTPREFETCH_REQUESTSPrefetch requests sent to the DCT32_BYTES_WRITES32 Bytes Sized Writes64_BYTES_WRITES64 Bytes Sized Writes32_BYTES_READS32 Bytes Sized Reads64_BYTES_READS64 Byte Sized ReadsREAD_REQUESTS_WHILE_WRITES_REQUESTSRead requests sent to the DCT while writes requests are pending in the DCTLOCAL_TO_0From Local node to Node 0LOCAL_TO_1From Local node to Node 1LOCAL_TO_2From Local node to Node 2LOCAL_TO_3From Local node to Node 3LOCAL_TO_4From Local node to Node 4LOCAL_TO_5From Local node to Node 5LOCAL_TO_6From Local node to Node 6LOCAL_TO_7From Local node to Node 7READ_BLOCKRead blockREAD_BLOCK_SHAREDRead block sharedRead block modifiedCHANGE_TO_DIRTYChange-to-DirtyREAD_SIZEDRead SizedWRITE_SIZEDWrite SizedVICTIM_BLOCKVictim BlockNODE_GROUP_SELECTNode Group Select. 0=Nodes 0-3. 1= Nodes 4-7.LOCAL_TO_0_4From Local node to Node 0/4LOCAL_TO_1_5From Local node to Node 1/5LOCAL_TO_2_6From Local node to Node 2/6LOCAL_TO_3_7From Local node to Node 3/7COMMAND_DWORD_SENTCommand DWORD sentDATA_DWORD_SENTData DWORD sentBUFFER_RELEASE_DWORD_SENTBuffer release DWORD sentNOP_DWORD_SENTNop DW sent (idle)ADDRESS_EXT_DWORD_SENTAddress extension DWORD sentPER_PACKET_CRC_SENTPer packet CRC sentSUBLINK_MASKSubLink MaskAddress DWORD sentREAD_BLOCK_EXCLUSIVERead Block Exclusive (Data cache read)Read Block Shared (Instruction cache read)READ_BLOCK_MODIFYRead Block ModifyANY_READAny read modes (exclusive, shared, modify)ALL_CORESAll coresANY_STATEAny line state (shared, owned, exclusive, modified)GUEST_LARGERGuest page size is larger than the host page size.MTRR_MISMATCHMTRR mismatch.HOST_LARGERHost page size is larger than the guest page size.ADD_SUB_OPSAdd/subtract opsMUL_OPSMultiply opsDIV_OPSDivide opsDISPATCHED_FPUDispatched FPU OperationsCYCLES_NO_FPU_OPS_RETIREDCycles in which the FPU is EmptyDISPATCHED_FPU_OPS_FAST_FLAGDispatched Fast Flag FPU OperationsRETIRED_SSE_OPERATIONSRetired SSE OperationsRETIRED_MOVE_OPSRetired Move OpsRETIRED_SERIALIZING_OPSRetired Serializing OpsFP_SCHEDULER_CYCLESNumber of Cycles that a Serializing uop is in the FP SchedulerSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline Restart Due to Self-Modifying CodePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline Restart Due to Probe HitLS_BUFFER_2_FULL_CYCLESLS Buffer 2 FullLOCKED_OPSLocked OperationsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsCANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONSCancelled Store to Load Forward OperationsSMIS_RECEIVEDSMIs ReceivedDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2 or NorthbridgeDATA_CACHE_REFILLS_FROM_SYSTEMData Cache Refills from the NorthbridgeDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITL1 DTLB Miss and L2 DTLB HitL1_DTLB_AND_L2_DTLB_MISSL1 DTLB and L2 DTLB MissMISALIGNED_ACCESSESMisaligned AccessesMICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESSMicroarchitectural Late Cancel of an AccessMICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESSMicroarchitectural Early Cancel of an AccessSCRUBBER_SINGLE_BIT_ECC_ERRORSSingle-bit ECC Errors Recorded by ScrubberPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedDCACHE_MISSES_BY_LOCKED_INSTRUCTIONSDCACHE Misses by Locked InstructionsL1_DTLB_HITL1 DTLB HitINEFFECTIVE_SW_PREFETCHESIneffective Software PrefetchesGLOBAL_TLB_FLUSHESGlobal TLB FlushesMEMORY_REQUESTSMemory Requests by TypeDATA_PREFETCHESData PrefetcherMAB_REQUESTSAverage L1 refill latency for Icache and Dcache misses (request count for cache refills)MAB_WAIT_CYCLESAverage L1 refill latency for Icache and Dcache misses (cycles that requests spent waiting for the refills)SYSTEM_READ_RESPONSESNorthbridge Read Responses by Coherency StateQUADWORDS_WRITTEN_TO_SYSTEMOctwords Written to SystemCPU_CLK_UNHALTEDCPU Clocks not HaltedREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_FILL_WRITEBACKL2 Fill/WritebackINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss and L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissPIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBEPipeline Restart Due to Instruction Stream ProbeINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsINSTRUCTION_CACHE_VICTIMSInstruction Cache VictimsINSTRUCTION_CACHE_LINES_INVALIDATEDInstruction Cache Lines InvalidatedITLB_RELOADSITLB ReloadsITLB_RELOADS_ABORTEDITLB Reloads AbortedRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_MMX_AND_FP_INSTRUCTIONSRetired MMX/FP InstructionsRETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONSRetired Fastpath Double Op InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenDECODER_EMPTYDecoder EmptyDISPATCH_STALLSDispatch StallsDISPATCH_STALL_FOR_BRANCH_ABORTDispatch Stall for Branch Abort to RetireDISPATCH_STALL_FOR_SERIALIZATIONDispatch Stall for SerializationDISPATCH_STALL_FOR_SEGMENT_LOADDispatch Stall for Segment LoadDISPATCH_STALL_FOR_REORDER_BUFFER_FULLDispatch Stall for Reorder Buffer FullDISPATCH_STALL_FOR_RESERVATION_STATION_FULLDispatch Stall for Reservation Station FullDISPATCH_STALL_FOR_FPU_FULLDispatch Stall for FPU FullDISPATCH_STALL_FOR_LS_FULLDispatch Stall for LS FullDISPATCH_STALL_WAITING_FOR_ALL_QUIETDispatch Stall Waiting for All QuietDISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNCDispatch Stall for Far Transfer or Resync to RetireFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINT_MATCHESDR0 Breakpoint MatchesDR1_BREAKPOINT_MATCHESDR1 Breakpoint MatchesDR2_BREAKPOINT_MATCHESDR2 Breakpoint MatchesDR3_BREAKPOINT_MATCHESDR3 Breakpoint MatchesDRAM_ACCESSES_PAGEDRAM AccessesMEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWSDRAM Controller Page Table OverflowsMEMORY_CONTROLLER_SLOT_MISSESMemory Controller DRAM Command Slots MissedMEMORY_CONTROLLER_TURNAROUNDSMemory Controller TurnaroundsMEMORY_CONTROLLER_BYPASSMemory Controller Bypass Counter SaturationTHERMAL_STATUS_AND_ECC_ERRORSThermal StatusCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCKCache Block CommandsSIZED_COMMANDSSized CommandsPROBEProbe Responses and Upstream RequestsGARTGART EventsMEMORY_CONTROLLER_REQUESTSMemory Controller RequestsCPU_TO_DRAM_REQUESTS_TO_TARGET_NODECPU to DRAM Requests to Target NodeIO_TO_DRAM_REQUESTS_TO_TARGET_NODEIO to DRAM Requests to Target NodeCPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3CPU Read Command Latency to Target Node 0-3CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3CPU Read Command Requests to Target Node 0-3CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7CPU Read Command Latency to Target Node 4-7CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7CPU Read Command Requests to Target Node 4-7CPU_COMMAND_LATENCY_TO_TARGET_NODE_0_3_4_7CPU Command Latency to Target Node 0-3/4-7CPU_REQUESTS_TO_TARGET_NODE_0_3_4_7CPU Requests to Target Node 0-3/4-7HYPERTRANSPORT_LINK0HyperTransport Link 0 Transmit BandwidthHYPERTRANSPORT_LINK1HyperTransport Link 1 Transmit BandwidthHYPERTRANSPORT_LINK2HyperTransport Link 2 Transmit BandwidthHYPERTRANSPORT_LINK3HyperTransport Link 3 Transmit BandwidthREAD_REQUEST_TO_L3_CACHERead Request to L3 CacheL3_CACHE_MISSESL3 Cache MissesL3_FILLS_CAUSED_BY_L2_EVICTIONSL3 Fills caused by L2 EvictionsL3_EVICTIONSL3 EvictionsPAGE_SIZE_MISMATCHESPage Size MismatchesRETIRED_X87_OPSRetired x87 Floating Point OperationsIBS_OPS_TAGGEDIBS Ops TaggedLFENCE_INST_RETIREDLFENCE Instructions RetiredSFENCE_INST_RETIREDSFENCE Instructions RetiredMFENCE_INST_RETIREDMFENCE Instructions RetiredNON_CANCELLED_L3_READ_REQUESTSNon-cancelled L3 Read RequestsAMD64 Fam10h Barcelonaamd64_fam10h_barcelonaAMD64 Fam10h Shanghaiamd64_fam10h_shanghaiAMD64 Fam10h Istanbulamd64_fam10h_istanbulOPS_ADDAdd pipe ops excluding load ops and SSE move opsOPS_MULTIPLYMultiply pipe ops excluding load ops and SSE move opsOPS_STOREStore pipe ops excluding load ops and SSE move opsOPS_ADD_PIPE_LOAD_OPSAdd pipe load ops and SSE move opsOPS_MULTIPLY_PIPE_LOAD_OPSMultiply pipe load ops and SSE move opsOPS_STORE_PIPE_LOAD_OPSStore pipe load ops and SSE move opsALLAll sub-events selectedESCSSSDSFSGSHSEXECUTEDThe number of locked instructions executedCYCLES_SPECULATIVE_PHASEThe number of cycles spent in speculative phaseCYCLES_NON_SPECULATIVE_PHASEThe number of cycles spent in non-speculative phase (including cache miss penalty)SYSTEMRefill from the NorthbridgeL2_SHAREDShared-state line from L2L2_EXCLUSIVEExclusive-state line from L2L2_OWNEDOwned-state line from L2L2_MODIFIEDModified-state line from L2INVALIDInvalidSHAREDSharedEXCLUSIVEExclusiveOWNEDOwnedMODIFIEDModifiedSCRUBBER_ERRORScrubber errorPIGGYBACK_ERRORPiggyback scrubber errorsLOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA)DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONSData cache misses by locked instructionsNON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to write-combining (WC) memory or WC buffer flushes to WB memorySTREAMING_STOREStreaming store (SS) requestsCANCELLEDCancelled prefetchesATTEMPTEDPrefetch attemptsDATA_ERRORData ErrorQUADWORD_WRITE_TRANSFERQuadword write transferINSTRUCTIONSIC fillDATADC fillTLB_WALKTLB fill (page table walks)SNOOPTag snoop requestCancelled requestDC fill (includes possible replays, whereas EventSelect 041h does not)TLB page table walkL2_FILLSL2 fills (victims from L1 caches, TLB page table walks and data prefetches)L2_WRITEBACKSL2 Writebacks to system.X87X87 instructionsMMX_AND_3DNOWMMX and 3DNow! instructionsPACKED_SSE_AND_SSE2Packed SSE and SSE2 instructionsSCALAR_SSE_AND_SSE2Scalar SSE and SSE2 instructionsPOSITION_0With low op in position 0POSITION_1With low op in position 1POSITION_2With low op in position 2FIXED_AND_LPAFixed and LPALPASMINMIINITSTARTUPINTEOIHALTSTOPGRANTSHUTDOWNWBINVDINVDX87_RECLASS_MICROFAULTSX87 reclass microfaultsSSE_RETYPE_MICROFAULTSSSE retype microfaultsSSE_RECLASS_MICROFAULTSSSE reclass microfaultsSSE_AND_X87_MICROTRAPSSSE and x87 microtrapsDCT0_PAGE_HITDCT0 Page hitDCT0_PAGE_MISSDCT0 Page MissDCT0_PAGE_CONFLICTDCT0 Page ConflictDCT1_PAGE_HITDCT1 Page hitDCT1_PAGE_MISSDCT1 Page MissDCT1_PAGE_CONFLICTDCT1 Page ConflictWRITE_REQUESTWrite request.READ_REQUESTRead request.DCT_PAGE_TABLE_OVERFLOWDCT Page Table OverflowSTALE_TABLE_ENTRY_HITSNumber of stale table entry hits. (hit on a page closed too soon).PAGE_TABLE_IDLE_CYCLE_LIMIT_INCREMENTEDPage table idle cycle limit incremented.PAGE_TABLE_IDLE_CYCLE_LIMIT_DECREMENTEDPage table idle cycle limit decremented.DCT0_READ_TO_WRITEDCT0 read-to-write turnaround.DCT0_WRITE_TO_READDCT0 write-to-read turnaroundDCT0_DIMMDCT0 DIMM (chip select) turnaroundDCT1_READ_TO_WRITEDCT1 read-to-write turnaround.DCT1_WRITE_TO_READDCT1 write-to-read turnaroundDCT1_DIMMDCT1 DIMM (chip select) turnaroundCOUNTER_REACHEDF2x[1,0]94[DcqBypassMax] counter reached.MEMHOT_L_ASSERTIONSNumber of clocks MEMHOT_L is asserted.HTC_TRANSITIONSNumber of times the HTC transitions from inactive to active.CLOCKS_HTC_P_STATE_INACTIVENumber of clocks HTC P-state is inactive.CLOCKS_HTC_P_STATE_ACTIVENumber of clocks HTC P-state is activePROCHOT_L_ASSERTIONSPROCHOT_L asserted by an external source and the assertion causes a P-state change.I_O_TO_I_OIO to IOI_O_TO_MEMIO to MemCPU_TO_I_OCPU to IOCPU_TO_MEMCPU to MemVICTIM_WRITEBACKVictim Block (Writeback)DCACHE_LOAD_MISSRead Block (Dcache load miss refill)SHARED_ICACHE_REFILLRead Block Shared (Icache refill)READ_BLOCK_MODIFIEDRead Block Modified (Dcache store miss refill)READ_TO_DIRTYChange-to-Dirty (first store to clean block already in cache)NON_POSTED_WRITE_BYTENon-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytesNON_POSTED_WRITE_DWORDNon-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORDPOSTED_WRITE_BYTEPosted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining bufferPOSTED_WRITE_DWORDPosted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushesREAD_BYTE_4_BYTESSzRd Byte (4 bytes) Legacy or mapped IOREAD_DWORD_1_16_DWORDSSzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line sizeMISSProbe missHIT_CLEANProbe hit cleanHIT_DIRTY_NO_MEMORY_CANCELProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)HIT_DIRTY_WITH_MEMORY_CANCELProbe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_DISPLAY_REFRESH_READSUpstream display refresh/ISOC reads.UPSTREAM_NON_DISPLAY_REFRESH_READSUpstream non-display refresh reads.UPSTREAM_ISOC_WRITESUpstream ISOC writes.UPSTREAM_NON_ISOC_WRITESUpstream non-ISOC writes.DEV_HITDEV hitDEV_MISSDEV missDEV_ERRORDEV error32_BYTES_WRITES32 Bytes Sized Writes64_BYTES_WRITES64 Bytes Sized Writes32_BYTES_READS32 Bytes Sized Reads64_BYTES_READS64 Byte Sized ReadsCOMMAND_DWORD_SENTCommand DWORD sentADDRESS_DWORD_SENTAddress DWORD sentDATA_DWORD_SENTData DWORD sentBUFFER_RELEASE_DWORD_SENTBuffer release DWORD sentNOP_DWORD_SENTNop DW sent (idle)PER_PACKET_CRC_SENTPer packet CRC sentDISPATCHED_FPUDispatched FPU OperationsCYCLES_NO_FPU_OPS_RETIREDCycles in which the FPU is EmptyDISPATCHED_FPU_OPS_FAST_FLAGDispatched Fast Flag FPU OperationsSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline Restart Due to Self-Modifying CodePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline Restart Due to Probe HitLS_BUFFER_2_FULL_CYCLESLS Buffer 2 FullLOCKED_OPSLocked OperationsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2 or SystemDATA_CACHE_REFILLS_FROM_SYSTEMData Cache Refills from the SystemDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITNumber of data cache accesses that miss in L1 DTLB and hit in L2 DTLBL1_DTLB_AND_L2_DTLB_MISSNumber of data cache accesses that miss both the L1 and L2 DTLBsMISALIGNED_ACCESSESMisaligned AccessesMICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESSMicroarchitectural Late Cancel of an AccessMICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESSMicroarchitectural Early Cancel of an AccessSCRUBBER_SINGLE_BIT_ECC_ERRORSSingle-bit ECC Errors Recorded by ScrubberPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedDCACHE_MISSES_BY_LOCKED_INSTRUCTIONSDCACHE Misses by Locked InstructionsMEMORY_REQUESTSMemory Requests by TypeDATA_PREFETCHESData PrefetcherSYSTEM_READ_RESPONSESSystem Read Responses by Coherency StateQUADWORDS_WRITTEN_TO_SYSTEMQuadwords Written to SystemCPU_CLK_UNHALTEDCPU Clocks not HaltedREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_FILL_WRITEBACKL2 Fill/WritebackINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss and L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissPIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBEPipeline Restart Due to Instruction Stream ProbeINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_MMX_AND_FP_INSTRUCTIONSRetired MMX/FP InstructionsRETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONSRetired Fastpath Double Op InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenDECODER_EMPTYDecoder EmptyDISPATCH_STALLSDispatch StallsDISPATCH_STALL_FOR_BRANCH_ABORTDispatch Stall for Branch Abort to RetireDISPATCH_STALL_FOR_SERIALIZATIONDispatch Stall for SerializationDISPATCH_STALL_FOR_SEGMENT_LOADDispatch Stall for Segment LoadDISPATCH_STALL_FOR_REORDER_BUFFER_FULLDispatch Stall for Reorder Buffer FullDISPATCH_STALL_FOR_RESERVATION_STATION_FULLDispatch Stall for Reservation Station FullDISPATCH_STALL_FOR_FPU_FULLDispatch Stall for FPU FullDISPATCH_STALL_FOR_LS_FULLDispatch Stall for LS FullDISPATCH_STALL_WAITING_FOR_ALL_QUIETDispatch Stall Waiting for All QuietDISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNCDispatch Stall for Far Transfer or Resync to RetireFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINT_MATCHESDR0 Breakpoint MatchesDR1_BREAKPOINT_MATCHESDR1 Breakpoint MatchesDR2_BREAKPOINT_MATCHESDR2 Breakpoint MatchesDR3_BREAKPOINT_MATCHESDR3 Breakpoint MatchesDRAM_ACCESSESDRAM AccessesDRAM_CONTROLLER_PAGE_TABLE_EVENTSDRAM Controller Page Table EventsMEMORY_CONTROLLER_TURNAROUNDSMemory Controller TurnaroundsMEMORY_CONTROLLER_RBD_QUEUEMemory Controller RBD Queue EventsTHERMAL_STATUSThermal StatusCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCKCache Block CommandsSIZED_COMMANDSSized CommandsPROBEProbe Responses and Upstream RequestsDEVDEV EventsHYPERTRANSPORT_LINK0HyperTransport Link 0 Transmit BandwidthMEMORY_CONTROLLER_REQUESTSMemory Controller RequestsSIDEBAND_SIGNALSSideband Signals and Special CyclesINTERRUPT_EVENTSInterrupt EventsAMD64 Fam11h Turionamd64_fam11h_turionOPS_ADDAdd pipe ops excluding load ops and SSE move opsOPS_MULTIPLYMultiply pipe ops excluding load ops and SSE move opsOPS_STOREStore pipe ops excluding load ops and SSE move opsOPS_ADD_PIPE_LOAD_OPSAdd pipe load ops and SSE move opsOPS_MULTIPLY_PIPE_LOAD_OPSMultiply pipe load ops and SSE move opsOPS_STORE_PIPE_LOAD_OPSStore pipe load ops and SSE move opsALLAll sub-events selectedSINGLE_ADD_SUB_OPSSingle precision add/subtract opsSINGLE_MUL_OPSSingle precision multiply opsSINGLE_DIV_OPSSingle precision divide/square root opsDOUBLE_ADD_SUB_OPSDouble precision add/subtract opsDOUBLE_MUL_OPSDouble precision multiply opsDOUBLE_DIV_OPSDouble precision divide/square root opsOP_TYPEOp type: 0=uops. 1=FLOPSLOW_QW_MOVE_UOPSMerging low quadword move uopsHIGH_QW_MOVE_UOPSMerging high quadword move uopsALL_OTHER_MERGING_MOVE_UOPSAll other merging move uopsALL_OTHER_MOVE_UOPSAll other move uopsSSE_BOTTOM_EXECUTING_UOPSSSE bottom-executing uops retiredSSE_BOTTOM_SERIALIZING_UOPSSSE bottom-serializing uops retiredX87_BOTTOM_EXECUTING_UOPSX87 bottom-executing uops retiredX87_BOTTOM_SERIALIZING_UOPSX87 bottom-serializing uops retiredBOTTOM_EXECUTE_CYCLESNumber of cycles a bottom-execute uop is in the FP schedulerBOTTOM_SERIALIZING_CYCLESNumber of cycles a bottom-serializing uop is in the FP schedulerESCSSSDSFSGSHSEXECUTEDThe number of locked instructions executedCYCLES_SPECULATIVE_PHASEThe number of cycles spent in speculative phaseCYCLES_NON_SPECULATIVE_PHASEThe number of cycles spent in non-speculative phase (including cache miss penalty)CYCLES_WAITINGThe number of cycles waiting for a cache hit (cache miss penalty).ADDRESS_MISMATCHESAddress mismatches (starting byte not the same).STORE_IS_SMALLER_THAN_LOADStore is smaller than load.MISALIGNEDMisaligned.SYSTEMRefill from the NorthbridgeL2_SHAREDShared-state line from L2L2_EXCLUSIVEExclusive-state line from L2L2_OWNEDOwned-state line from L2L2_MODIFIEDModified-state line from L2INVALIDInvalidSHAREDSharedEXCLUSIVEExclusiveOWNEDOwnedMODIFIEDModifiedBY_PREFETCHNTACache line evicted was brought into the cache with by a PrefetchNTA instruction.NOT_BY_PREFETCHNTACache line evicted was not brought into the cache with by a PrefetchNTA instruction.L2_4K_TLB_HITL2 4K TLB hitL2_2M_TLB_HITL2 2M TLB hitL2_1G_TLB_HITL2 1G TLB hit4K_TLB_RELOAD4K TLB reload2M_TLB_RELOAD2M TLB reload1G_TLB_RELOAD1G TLB reloadLOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA)DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONSData cache misses by locked instructionsL1_4K_TLB_HITL1 4K TLB hitL1_2M_TLB_HITL1 2M TLB hitL1_1G_TLB_HITL1 1G TLB hitSW_PREFETCH_HIT_IN_L1Software prefetch hit in the L1.SW_PREFETCH_HIT_IN_L2Software prefetch hit in L2.NON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to write-combining (WC) memory or WC buffer flushes to WB memoryCACHE_DISABLEDRequests to cache-disabled (CD) memorySTREAMING_STOREStreaming store (SS) requestsCANCELLEDCancelled prefetchesATTEMPTEDPrefetch attemptsDATA_ERRORData ErrorOCTWORD_WRITE_TRANSFEROctword write transferINSTRUCTIONSIC fillDATADC fillTLB_WALKTLB fill (page table walks)SNOOPTag snoop requestCancelled requestHW_PREFETCH_FROM_DCHardware prefetch from DCDC fill (includes possible replays, whereas EventSelect 041h does not)TLB page table walkL2_FILLSL2 fills (victims from L1 caches, TLB page table walks and data prefetches)L2_WRITEBACKSL2 Writebacks to system.4K_PAGE_FETCHESInstruction fetches to a 4K page.2M_PAGE_FETCHESInstruction fetches to a 2M page.INVALIDATING_PROBE_NO_IN_FLIGHTInvalidating probe that did not hit any in-flight instructions.INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHTInvalidating probe that hit one or more in-flight instructions.SMC_NO_INFLIGHTSMC that did not hit any in-flight instructions.SMC_INFLIGHTSMC that hit one or more in-flight instructions.X87X87 instructionsMMX_AND_3DNOWMMX and 3DNow! instructionsSSE_AND_SSE2SSE and SSE2 instructionsFIXED_AND_LPAFixed and LPALPASMINMIINITSTARTUPINTEOISTOPGRANTSHUTDOWNWBINVDINVDX87_RECLASS_MICROFAULTSX87 reclass microfaultsSSE_RETYPE_MICROFAULTSSSE retype microfaultsSSE_RECLASS_MICROFAULTSSSE reclass microfaultsSSE_AND_X87_MICROTRAPSSSE and x87 microtrapsDCT0_HITDCT0 Page hitDCT0_MISSDCT0 Page MissDCT0_CONFLICTDCT0 Page ConflictDCT1_PAGE_HITDCT1 Page hitDCT1_PAGE_MISSDCT1 Page MissDCT1_PAGE_CONFLICTDCT1 Page ConflictWRITE_REQUESTWrite request.READ_REQUESTRead request.PAGE_TABLE_OVERFLOWPage Table OverflowSTALE_TABLE_ENTRY_HITSNumber of stale table entry hits. (hit on a page closed too soon).PAGE_TABLE_IDLE_CYCLE_LIMIT_INCREMENTEDPage table idle cycle limit incremented.PAGE_TABLE_IDLE_CYCLE_LIMIT_DECREMENTEDPage table idle cycle limit decremented.PAGE_TABLE_CLOSED_INACTIVITYPage table is closed due to row inactivity.DCT0_RBDDCT0 RBD.DCT1_RBDDCT1 RBD.DCT0_PREFETCHDCT0 Prefetch.DCT1_PREFETCHDCT1 Prefetch.DCT0_READ_TO_WRITEDCT0 read-to-write turnaround.DCT0_WRITE_TO_READDCT0 write-to-read turnaroundDCT1_READ_TO_WRITEDCT1 read-to-write turnaround.DCT1_WRITE_TO_READDCT1 write-to-read turnaroundCOUNTER_REACHEDD18F2x[1,0]94[DcqBypassMax] counter reached.BANK_CLOSEDBank is closed due to bank conflict with an outstanding request in the RBD queue.MEMHOT_L_ASSERTIONSMEMHOT_L assertions.HTC_TRANSITIONSNumber of times the HTC transitions from inactive to active.CLOCKS_HTC_P_STATE_INACTIVENumber of clocks HTC P-state is inactive.CLOCKS_HTC_P_STATE_ACTIVENumber of clocks HTC P-state is activePROCHOT_L_ASSERTIONSPROCHOT_L asserted by an external source and the assertion causes a P-state change.I_O_TO_I_OIO to IOI_O_TO_MEMIO to MemCPU_TO_I_OCPU to IOCPU_TO_MEMCPU to MemVICTIM_WRITEBACKVictim Block (Writeback)DCACHE_LOAD_MISSRead Block (Dcache load miss refill)SHARED_ICACHE_REFILLRead Block Shared (Icache refill)READ_BLOCK_MODIFIEDRead Block Modified (Dcache store miss refill)READ_TO_DIRTYChange-to-Dirty (first store to clean block already in cache)NON_POSTED_WRITE_BYTENon-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytesNON_POSTED_WRITE_DWORDNon-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORDPOSTED_WRITE_BYTEPosted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining bufferPOSTED_WRITE_DWORDPosted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushesREAD_BYTE_4_BYTESSzRd Byte (4 bytes) Legacy or mapped IOREAD_DWORD_1_16_DWORDSSzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line sizeMISSProbe missHIT_CLEANProbe hit cleanHIT_DIRTY_NO_MEMORY_CANCELProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)HIT_DIRTY_WITH_MEMORY_CANCELProbe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_HIGH_PRIORITY_READSUpstream high priority reads.UPSTREAM_LOW_PRIORITY_READSUpstream low priority reads.UPSTREAM_LOW_PRIORITY_WRITESUpstream low priority writes.DEV_HITDEV hitDEV_MISSDEV missDEV_ERRORDEV error32_BYTES_WRITES32 Bytes Sized Writes64_BYTES_WRITES64 Bytes Sized Writes32_BYTES_READS32 Bytes Sized Reads64_BYTES_READS64 Byte Sized ReadsGUEST_LARGERGuest page size is larger than the host page size.MTRR_MISMATCHMTRR mismatch.HOST_LARGERHost page size is larger than the guest page size.ADD_SUB_OPSAdd/subtract opsMUL_OPSMultiply opsDIV_OPSDivide opsDISPATCHED_FPUDispatched FPU OperationsCYCLES_NO_FPU_OPS_RETIREDCycles in which the FPU is EmptyDISPATCHED_FPU_OPS_FAST_FLAGDispatched Fast Flag FPU OperationsRETIRED_SSE_OPERATIONSRetired SSE OperationsRETIRED_MOVE_OPSRetired Move OpsRETIRED_SERIALIZING_OPSRetired Serializing OpsFP_SCHEDULER_CYCLESNumber of Cycles that a Serializing uop is in the FP SchedulerSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline Restart Due to Self-Modifying CodePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline Restart Due to Probe HitLS_BUFFER_2_FULL_CYCLESLS Buffer 2 FullLOCKED_OPSLocked OperationsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsCANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONSCancelled Store to Load Forward OperationsSMIS_RECEIVEDSMIs ReceivedDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2 or NorthbridgeDATA_CACHE_REFILLS_FROM_SYSTEMData Cache Refills from the NorthbridgeDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITL1 DTLB Miss and L2 DTLB HitL1_DTLB_AND_L2_DTLB_MISSL1 DTLB and L2 DTLB MissMISALIGNED_ACCESSESMisaligned AccessesMICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESSMicroarchitectural Late Cancel of an AccessMICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESSMicroarchitectural Early Cancel of an AccessPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedDCACHE_MISSES_BY_LOCKED_INSTRUCTIONSDCACHE Misses by Locked InstructionsL1_DTLB_HITL1 DTLB HitINEFFECTIVE_SW_PREFETCHESIneffective Software PrefetchesGLOBAL_TLB_FLUSHESGlobal TLB FlushesMEMORY_REQUESTSMemory Requests by TypeDATA_PREFETCHESData PrefetcherNORTHBRIDGE_READ_RESPONSESNorthbridge Read Responses by Coherency StateOCTWORDS_WRITTEN_TO_SYSTEMOctwords Written to SystemCPU_CLK_UNHALTEDCPU Clocks not HaltedREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_FILL_WRITEBACKL2 Fill/WritebackPAGE_SIZE_MISMATCHESPage Size MismatchesINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss and L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissPIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBEPipeline Restart Due to Instruction Stream ProbeINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsINSTRUCTION_CACHE_VICTIMSInstruction Cache VictimsINSTRUCTION_CACHE_LINES_INVALIDATEDInstruction Cache Lines InvalidatedITLB_RELOADSITLB ReloadsITLB_RELOADS_ABORTEDITLB Reloads AbortedRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_MMX_AND_FP_INSTRUCTIONSRetired MMX/FP InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenDECODER_EMPTYDecoder EmptyDISPATCH_STALLSDispatch StallsDISPATCH_STALL_FOR_BRANCH_ABORTDispatch Stall for Branch Abort to RetireDISPATCH_STALL_FOR_SERIALIZATIONDispatch Stall for SerializationDISPATCH_STALL_FOR_SEGMENT_LOADDispatch Stall for Segment LoadDISPATCH_STALL_FOR_REORDER_BUFFER_FULLDispatch Stall for Reorder Buffer FullDISPATCH_STALL_FOR_RESERVATION_STATION_FULLDispatch Stall for Reservation Station FullDISPATCH_STALL_FOR_FPU_FULLDispatch Stall for FPU FullDISPATCH_STALL_FOR_LS_FULLDispatch Stall for LS FullDISPATCH_STALL_WAITING_FOR_ALL_QUIETDispatch Stall Waiting for All QuietDISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNCDispatch Stall for Far Transfer or Resync to RetireFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINT_MATCHESDR0 Breakpoint MatchesDR1_BREAKPOINT_MATCHESDR1 Breakpoint MatchesDR2_BREAKPOINT_MATCHESDR2 Breakpoint MatchesDR3_BREAKPOINT_MATCHESDR3 Breakpoint MatchesRETIRED_X87_OPSRetired x87 Floating Point OperationsLFENCE_INST_RETIREDLFENCE Instructions RetiredSFENCE_INST_RETIREDSFENCE Instructions RetiredMFENCE_INST_RETIREDMFENCE Instructions RetiredDRAM_ACCESSES_PAGEDRAM AccessesMEMORY_CONTROLLER_0_PAGEDRAM Controller 0 Page Table EventsMEMORY_CONTROLLER_SLOT_MISSESMemory Controller DRAM Command Slots MissedMEMORY_CONTROLLER_TURNAROUNDSMemory Controller TurnaroundsMEMORY_CONTROLLER_RBD_QUEUEMemory Controller RBD Queue EventsMEMORY_CONTROLLER_1_PAGEDRAM Controller 1 Page Table EventsTHERMAL_STATUSThermal StatusCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCKCache Block CommandsSIZED_COMMANDSSized CommandsPROBEProbe Responses and Upstream RequestsDEVDEV EventsMEMORY_CONTROLLER_REQUESTSMemory Controller RequestsSIDEBAND_SIGNALSSideband Signals and Special CyclesINTERRUPT_EVENTSInterrupt EventsAMD64 Fam12h Llanoamd64_fam12h_llanoPIPE0Pipe 0 (fadd, imul, mmx) opsPIPE1Pipe 1 (fmul, store, mmx) opsANYPipe 1 and Pipe 0 opsSINGLE_ADD_SUB_OPSSingle precision add/subtract opsSINGLE_MUL_OPSSingle precision multiply opsSINGLE_DIV_OPSSingle precision divide/square root opsDOUBLE_ADD_SUB_OPSDouble precision add/subtract opsDOUBLE_MUL_OPSDouble precision multiply opsDOUBLE_DIV_OPSDouble precision divide/square root opsOP_TYPEOp type: 0=uops. 1=FLOPSALLAll sub-events selectedALL_OTHER_MERGING_MOVE_UOPSAll other merging move uopsALL_OTHER_MOVE_UOPSAll other move uopsSSE_BOTTOM_EXECUTING_UOPSSSE bottom-executing uops retiredSSE_BOTTOM_SERIALIZING_UOPSSSE bottom-serializing uops retiredX87_BOTTOM_EXECUTING_UOPSX87 bottom-executing uops retiredX87_BOTTOM_SERIALIZING_UOPSX87 bottom-serializing uops retiredADD_SUB_OPSAdd/subtract opsMULT_OPSMultiply opsDIV_FSQRT_OPSDivide and fqsrt opsESCSSSDSFSGSHSEXECUTEDNumber of locked instructions executedBUS_LOCKNumber of cycles to acquire bus lockUNLOCK_LINENumber of cycles to unlock line (not including cache miss)ADDRESS_MISMATCHESAddress mismatches (starting byte not the same).STORE_IS_SMALLER_THAN_LOADStore is smaller than load.MISALIGNEDMisaligned.UNCACHEABLEFrom non-cacheable dataSHAREDFrom shared linesEXCLUSIVEFrom exclusive linesOWNEDFrom owned linesMODIFIEDFrom modified linesUncacheable dataSharedExclusiveOwnedModifiedPROBEEviction from probeShared evictionExclusive evictionOwned evictionModified evictionSTORES_L1TLB_MISSStores that miss L1TLBLOADS_L1TLB_MISSLoads that miss L1TLBSTORES_L2TLB_MISSStores that miss L2TLBLOADS_L2TLB_MISSLoads that miss L2TLBLOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA)L1_4K_TLB_HITL1 4K TLB hitL1_2M_TLB_HITL1 2M TLB hitHITSW prefetch hit in the data cachePENDING_FILLSW prefetch hit a pending fillNO_MABSW prefetch does not get a MABL2_HITSW prefetch hits L2NON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to write-combining (WC) memory or WC buffer flushes to WB memorySTREAMING_STOREStreaming store (SS) requestsDC_BUFFER_0Data cache buffer 0DC_BUFFER_1Data cache buffer 1DC_BUFFER_2Data cache buffer 2DC_BUFFER_3Data cache buffer 3DC_BUFFER_4Data cache buffer 4DC_BUFFER_5Data cache buffer 5DC_BUFFER_6Data cache buffer 6DC_BUFFER_7Data cache buffer 7IC_BUFFER_0Instruction cache Buffer 1IC_BUFFER_1Instructions cache buffer 1ANY_IC_BUFFERAny instruction cache bufferANY_DC_BUFFERAny data cache bufferDATA_ERRORData ErrorDIRTY_SUCCESSChange-to-dirty successUncacheableINSTRUCTIONSIC fillDATADC fillSNOOPTag snoop requestDC fill (includes possible replays, whereas EventSelect 041h does not)L2_FILLSL2 fills (victims from L1 caches, TLB page table walks and data prefetches)L2_WRITEBACKSL2 Writebacks to system.IC_ATTR_WRITES_L2_ACCESSIc attribute writes which access the L2IC_ATTR_WRITES_L2_WRITESIc attribute writes which store into the L24K_PAGE_FETCHESInstruction fetches to a 4K page.2M_PAGE_FETCHESInstruction fetches to a 2M page.INVALIDATING_LS_PROBEIC invalidate due to an LS probeINVALIDATING_BU_PROBEIC invalidate due to a BU probeX87X87 or MMX instructionsSSESSE (SSE, SSE2, SSE3, MNI) instructionsX87_RECLASS_MICROFAULTSX87 reclass microfaultsSSE_RETYPE_MICROFAULTSSSE retype microfaultsSSE_RECLASS_MICROFAULTSSSE reclass microfaultsSSE_AND_X87_MICROTRAPSSSE and x87 microtrapsDCT0 Page hitMISSDCT0 Page MissCONFLICTDCT0 Page ConflictWRITE_REQUESTWrite requestDCT0_PAGE_TABLE_OVERFLOWDCT0 Page Table OverflowDCT0_PAGE_TABLE_STALE_HITDCT0 number of stale table entry hits (hit on a page closed too soon)DCT0_PAGE_TABLE_IDLE_INCDCT0 page table idle cycle limit incrementedDCT0_PAGE_TABLE_IDLE_DECDCT0 page table idle cycle limit decrementedDCT0_PAGE_TABLE_CLOSEDDCT0 page table is closed due to row inactivityDCT0_RBDDCT0 RBDDCT0_PREFETCHDCT0 prefetchDCQ_BYPASS_MAXDCQ_BYPASS_MAX counter reachedBANK_CLOSEDBank is closed due to bank conflict with an outstanding request in the RBD queueMEMHOT_LMEMHOT_L assertionsHTC_TRANSITIONNumber of times HTC transitions from inactive to activeCLOCKS_HTC_P_STATE_INACTIVENumber of clocks HTC P-state is inactive.CLOCKS_HTC_P_STATE_ACTIVENumber of clocks HTC P-state is activePROCHOT_LPROCHOT_L asserted by an external source and the assertion causes a P-state changeI_O_TO_I_OIO to IOI_O_TO_MEMIO to MemCPU_TO_I_OCPU to IOCPU_TO_MEMCPU to MemVICTIM_WRITEBACKVictim Block (Writeback)DCACHE_LOAD_MISSRead Block (Dcache load miss refill)SHARED_ICACHE_REFILLRead Block Shared (Icache refill)READ_BLOCK_MODIFIEDRead Block Modified (Dcache store miss refill)CHANGE_TO_DIRTYChange-to-Dirty (first store to clean block already in cache)NON_POSTED_WRITE_BYTENon-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytesNON_POSTED_WRITE_DWORDNon-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORDPOSTED_WRITE_BYTEPosted SzWr Byte (1-32 bytes) Subcache-line DMA writes, size varies; also flushes of partially-filled Write Combining bufferPOSTED_WRITE_DWORDPosted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushesREAD_BYTE_4_BYTESSzRd Byte (4 bytes) Legacy or mapped IOREAD_DWORD_1_16_DWORDSSzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line sizeProbe missHIT_CLEANProbe hit cleanHIT_DIRTY_NO_MEMORY_CANCELProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)HIT_DIRTY_WITH_MEMORY_CANCELProbe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_HIGH_PRIO_READSUpstream high priority readsUPSTREAM_LOW_PRIO_READSUpstream low priority readsUPSTREAM_LOW_PRIO_WRITESUpstream non-ISOC writesDEV hitDEV missERRORDEV error32_BYTES_WRITES32 Bytes Sized Writes64_BYTES_WRITES64 Bytes Sized Writes32_BYTES_READS32 Bytes Sized Reads64_BYTES_READS64 Byte Sized ReadsSTOPGRANTStopgrantSHUTDOWNShutdownWBINVDWbinvdINVDInvdFIXED_AND_LPAFixed and LPALPASMINMIINITSTARTUPINTEOIHOST_PDE_LEVELHost PDE levelHOST_PDPE_LEVELHost PDPE levelHOST_PML4E_LEVELHost PML4E levelGUEST_PDE_LEVELGuest PDE levelGUEST_PDPE_LEVELGuest PDPE levelGUEST_PML4E_LEVELGuest PML4E levelDISPATCHED_FPUNumber of uops dispatched to FPU execution pipelinesCYCLES_NO_FPU_OPS_RETIREDCycles in which the FPU is EmptyDISPATCHED_FPU_OPS_FAST_FLAGDispatched Fast Flag FPU OperationsRETIRED_SSE_OPERATIONSRetired SSE OperationsRETIRED_MOVE_OPSRetired Move OpsRETIRED_SERIALIZING_OPSRetired Serializing OpsRETIRED_X87_FPU_OPSNumber of x87 floating points ops that have retiredSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline Restart Due to Self-Modifying CodePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline Restart Due to Probe HitRSQ_FULLNumber of cycles that the RSQ holds retired stores. This buffer holds the stores waiting to retired as well as requests that missed the data cache and waiting on a refillLOCKED_OPSLocked OperationsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsCANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONSCancelled Store to Load Forward OperationsDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2 or NorthbridgeDATA_CACHE_REFILLS_FROM_NBData Cache Refills from the NorthbridgeDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITNumber of data cache accesses that miss in the L1 DTLB and hit the L2 DTLB. This is a speculative eventDTLB_MISSL1 DTLB and L2 DTLB MissMISALIGNED_ACCESSESMisaligned AccessesPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedDCACHE_MISSES_BY_LOCKED_INSTRUCTIONSDCACHE Misses by Locked InstructionsL1_DTLB_HITL1 DTLB HitDCACHE_SW_PREFETCHESNumber of software prefetches that do not cause an actual data cache refillGLOBAL_TLB_FLUSHESGlobal TLB FlushesMEMORY_REQUESTSMemory Requests by TypeMAB_REQUESTSNumber of L1 I-cache and D-cache misses per buffer. Average latency by combining with MAB_WAIT_CYCLES.MAB_WAIT_CYCLESLatency of L1 I-cache and D-cache misses per buffer. Average latency by combining with MAB_REQUESTS.SYSTEM_READ_RESPONSESNorthbridge Read Responses by Coherency StateCPU_CLK_UNHALTEDCPU Clocks not HaltedREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_FILL_WRITEBACKL2 Fill/WritebackINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss and L2 ITLB MissINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsINSTRUCTION_CACHE_VICTIMSInstruction Cache VictimsINSTRUCTION_CACHE_LINES_INVALIDATEDInstruction Cache Lines InvalidatedITLB_RELOADSITLB ReloadsITLB_RELOADS_ABORTEDITLB Reloads AbortedRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_FLOATING_POINT_INSTRUCTIONSRetired SSE/MMX/FP InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINT_MATCHESDR0 Breakpoint MatchesDR1_BREAKPOINT_MATCHESDR1 Breakpoint MatchesDR2_BREAKPOINT_MATCHESDR2 Breakpoint MatchesDR3_BREAKPOINT_MATCHESDR3 Breakpoint MatchesDRAM_ACCESSES_PAGEDRAM AccessesMEMORY_CONTROLLER_PAGE_TABLENumber of page table events in the local DRAM controllerMEMORY_CONTROLLER_SLOT_MISSESMemory Controller DRAM Command Slots MissedMEMORY_CONTROLLER_RBD_QUEUE_EVENTSMemory Controller Bypass Counter SaturationTHERMAL_STATUSThermal StatusCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCKCache Block CommandsSIZED_COMMANDSSized CommandsProbe Responses and Upstream RequestsDEV_EVENTSDEV EventsMEMORY_CONTROLLER_REQUESTSMemory Controller RequestsSIDEBAND_SIGNALS_SPECIAL_SIGNALSSideband signals and special cyclesINTERRUPT_EVENTSInterrupt eventsPDC_MISSPDC missAMD64 Fam14h Bobcatamd64_fam14h_bobcatOPS_PIPE0Total number uops assigned to Pipe 0OPS_PIPE1Total number uops assigned to Pipe 1OPS_PIPE2Total number uops assigned to Pipe 2OPS_PIPE3Total number uops assigned to Pipe 3OPS_DUAL_PIPE0Total number dual-pipe uops assigned to Pipe 0OPS_DUAL_PIPE1Total number dual-pipe uops assigned to Pipe 1OPS_DUAL_PIPE2Total number dual-pipe uops assigned to Pipe 2OPS_DUAL_PIPE3Total number dual-pipe uops assigned to Pipe 3ALLAll sub-events selectedSINGLE_ADD_SUB_OPSSingle-precision add/subtract FLOPSSINGLE_MUL_OPSSingle-precision multiply FLOPSSINGLE_DIV_OPSSingle-precision divide/square root FLOPSSINGLE_MUL_ADD_OPSSingle precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSDOUBLE_ADD_SUB_OPSDouble precision add/subtract FLOPSDOUBLE_MUL_OPSDouble precision multiply FLOPSDOUBLE_DIV_OPSDouble precision divide/square root FLOPSDOUBLE_MUL_ADD_OPSDouble precision multiply-add FLOPS. Multiply-add counts as 2 FLOPSSSE_MOVE_OPSNumber of SSE Move OpsSSE_MOVE_OPS_ELIMNumber of SSE Move Ops eliminatedOPT_CANDNumber of Ops that are candidates for optimization (Z-bit set or pass)SCALAR_OPS_OPTIMIZEDNumber of Scalar ops optimizedSSE_RETIREDSSE bottom-executing uops retiredSSE_MISPREDICTEDSSE control word mispredict traps due to mispredictionsX87_RETIREDX87 bottom-executing uops retiredX87_MISPREDICTEDX87 control word mispredict traps due to mispredictionsESCSSSDSFSGSHSLOAD_QUEUEThe number of cycles that the load buffer is fullSTORE_QUEUEThe number of cycles that the store buffer is fullEXECUTEDNumber of locked instructions executedCYCLES_NON_SPECULATIVE_PHASENumber of cycles spent in non-speculative phase, excluding cache miss penaltyCYCLES_WAITINGNumber of cycles spent in non-speculative phase, including the cache miss penaltySIZE_ADDRESS_MISMATCHESStore is smaller than load or different starting byte but partial overlapDC_MISS_STREAMING_STOREFirst data cache miss or streaming store to a 64B cache lineSTREAMING_STOREFirst streaming store to a 64B cache lineGOODFill with good data. (Final valid status is valid)INVALIDEarly valid status turned out to be invalidPOISONFill with poison dataREAD_ERRORFill with read data error4K_DATA4 KB unified TLB hit for data2M_DATA2 MB unified TLB hit for data1G_DATA1 GB unified TLB hit for data4K_INST4 KB unified TLB hit for instruction2M_INST2 MB unified TLB hit for instruction1G_INST1 GB unified TLB hit for instruction4 KB unified TLB miss for data2 MB unified TLB miss for data1GB_DATA1 GB unified TLB miss for data4 KB unified TLB miss for instruction2 MB unified TLB miss for instruction1 GB unified TLB miss for instructionLOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA)SW_PREFETCH_HIT_IN_L1Software prefetch hit in the L1SW_PREFETCH_HIT_IN_L2Software prefetch hit in the L2NON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to non-cacheable (WC, but not WC+/SS) memoryRequests to non-cacheable (WC+/SS, but not WC) memoryATTEMPTEDPrefetch attemptsBUFFER_BIT_0Buffer entry index bit 0BUFFER_BIT_1Buffer entry index bit 1BUFFER_BIT_2Buffer entry index bit 2BUFFER_BIT_3Buffer entry index bit 3BUFFER_BIT_4Buffer entry index bit 4BUFFER_BIT_5Buffer entry index bit 5BUFFER_BIT_6Buffer entry index bit 6BUFFER_BIT_7Buffer entry index bit 7EXCLUSIVEExclusiveMODIFIEDModified (D18F0x68[ATMModeEn]==0), Modified written (D18F0x68[ATMModeEn]==1)SHAREDSharedOWNEDOwnedDATA_ERRORData ErrorMODIFIED_UNWRITTENModified unwrittenOCTWORD_WRITE_TRANSFEROW write transferINSTRUCTIONSIC fillDATADC fillTLB_WALKTLB fill (page table walks)SNOOPNB probe requestCANCELLEDCanceled requestPREFETCHERL2 cache prefetcher requestDC fill (includes possible replays, whereas PMCx041 does not)TLB page table walkL2 Cache Prefetcher requestL2_FILLSL2 fills from systemL2_WRITEBACKSL2 Writebacks to system (Clean and Dirty)L2_WRITEBACKS_CLEANL2 Clean Writebacks to systemGUEST_LARGERGuest page size is larger than host page size when nested paging is enabledMTRR_MISMATCHSplintering due to MTRRs, IORRs, APIC, TOMs or other special address regionHOST_LARGERHost page size is larger than the guest page size4K_PAGE_FETCHESInstruction fetches to a 4 KB page2M_PAGE_FETCHESInstruction fetches to a 2 MB page1G_PAGE_FETCHESInstruction fetches to a 1 GB pageNON_SMC_PROBE_MISSNon-SMC invalidating probe that missed on in-flight instructionsNON_SMC_PROBE_HITNon-SMC invalidating probe that hit on in-flight instructionsSMC_PROBE_MISSSMC invalidating probe that missed on in-flight instructionsSMC_PROBE_HITSMC invalidating probe that hit on in-flight instructionsX87X87 instructionsMMXMMX(tm) instructionsSSESSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4)TOTAL_FAULTSTotal microfaultsTOTAL_TRAPSTotal microtrapsINT2EXT_FAULTSInt2Ext faultsEXT2INT_FAULTSExt2Int faultsBYPASS_FAULTSBypass faultsTAGGEDNumber of ops tagged by IBSRETIREDNumber of ops tagged by IBS that retiredIGNOREDNumber of times an op could not be tagged by IBS because of a previous tagged op that has not retiredLOADSLoadsSTORESStoresLOAD_OP_STORESLoad-op-StoresLOAD_L1_MISS_SEEN_BY_PREFETCHERLoad L1 miss seen by prefetcherSTORE_L1_MISS_SEEN_BY_PREFETCHERStore L1 miss seen by prefetcherDISPATCHED_FPU_OPSFPU Pipe AssignmentCYCLES_FPU_EMPTYFP Scheduler EmptyRETIRED_SSE_OPSRetired SSE/BNI OpsMOVE_SCALAR_OPTIMIZATIONNumber of Move Elimination and Scalar Op OptimizationRETIRED_SERIALIZING_OPSRetired Serializing OpsBOTTOM_EXECUTE_OPNumber of Cycles that a Bottom-Execute uop is in the FP SchedulerSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline Restart Due to Self-Modifying CodePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline Restart Due to Probe HitLOAD_Q_STORE_Q_FULLLoad Queue/Store Queue FullLOCKED_OPSLocked OperationsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsCANCELLED_STORE_TO_LOADCanceled Store to Load Forward OperationsSMIS_RECEIVEDSMIs ReceivedDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGEData Cache Refills from L2 or SystemDATA_CACHE_REFILLS_FROM_NORTHBRIDGEData Cache Refills from SystemUNIFIED_TLB_HITUnified TLB HitUNIFIED_TLB_MISSUnified TLB MissMISALIGNED_ACCESSESMisaligned AccessesPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedINEFFECTIVE_SW_PREFETCHESIneffective Software PrefetchesMEMORY_REQUESTSMemory Requests by TypeDATA_PREFETCHERData PrefetcherMAB_REQSMAB RequestsMAB_WAITMAB Wait CyclesSYSTEM_READ_RESPONSESResponse From System on Cache RefillsOCTWORD_WRITE_TRANSFERSOctwords Written to SystemCPU_CLK_UNHALTEDCPU Clocks not HaltedREQUESTS_TO_L2Requests to L2 CacheL2_CACHE_MISSL2 Cache MissesL2_CACHE_FILL_WRITEBACKL2 Fill/WritebackPAGE_SPLINTERINGPage SplinteringINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss, L2 ITLB HitL1_ITLB_MISS_AND_L2_ITLB_MISSL1 ITLB Miss, L2 ITLB MissPIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBEPipeline Restart Due to Instruction Stream ProbeINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsINSTRUCTION_CACHE_VICTIMSInstruction Cache VictimsINSTRUCTION_CACHE_INVALIDATEDInstruction Cache Lines InvalidatedITLB_RELOADSITLB ReloadsITLB_RELOADS_ABORTEDITLB Reloads AbortedRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_INDIRECT_BRANCHES_MISPREDICTEDRetired Indirect Branches MispredictedRETIRED_MMX_FP_INSTRUCTIONSRetired MMX/FP InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenDECODER_EMPTYDecoder EmptyDISPATCH_STALLSDispatch StallsDISPATCH_STALL_FOR_SERIALIZATIONMicrosequencer Stall due to SerializationDISPATCH_STALL_FOR_RETIRE_QUEUE_FULLDispatch Stall for Instruction Retire Q FullDISPATCH_STALL_FOR_INT_SCHED_QUEUE_FULLDispatch Stall for Integer Scheduler Queue FullDISPATCH_STALL_FOR_FPU_FULLDispatch Stall for FP Scheduler Queue FullDISPATCH_STALL_FOR_LDQ_FULLDispatch Stall for LDQ FullMICROSEQ_STALL_WAITING_FOR_ALL_QUIETMicrosequencer Stall Waiting for All QuietFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINTSDR0 Breakpoint MatchDR1_BREAKPOINTSDR1 Breakpoint MatchDR2_BREAKPOINTSDR2 Breakpoint MatchDR3_BREAKPOINTSDR3 Breakpoint MatchIBS_OPS_TAGGEDTagged IBS OpsLS_DISPATCHLS DispatchEXECUTED_CLFLUSH_INSTRUCTIONSExecuted CLFLUSH InstructionsL2_PREFETCHER_TRIGGER_EVENTSL2 Prefetcher Trigger EventsDISPATCH_STALL_FOR_STQ_FULLDispatch Stall for STQ FullDCT0_PAGE_HITDCT0 Page hitDCT0_PAGE_MISSDCT0 Page MissDCT0_PAGE_CONFLICTDCT0 Page ConflictDCT1_PAGE_HITDCT1 Page hitDCT1_PAGE_MISSDCT1 Page MissDCT1_PAGE_CONFLICTDCT1 Page ConflictDCT0_PAGE_TABLE_OVERFLOWDCT0 Page Table OverflowDCT1_PAGE_TABLE_OVERFLOWDCT1 Page Table OverflowDCT0_COMMAND_SLOTS_MISSEDDCT0 Command Slots Missed (in MemClks)DCT1_COMMAND_SLOTS_MISSEDDCT1 Command Slots Missed (in MemClks)DCT0_DIMM_TURNAROUNDDCT0 DIMM (chip select) turnaroundDCT0_READ_WRITE_TURNAROUNDDCT0 Read to write turnaroundDCT0_WRITE_READ_TURNAROUNDDCT0 Write to read turnaroundDCT1_DIMM_TURNAROUNDDCT1 DIMM (chip select) turnaroundDCT1_READ_WRITE_TURNAROUNDDCT1 Read to write turnaroundDCT1_WRITE_READ_TURNAROUNDDCT1 Write to read turnaroundMEMORY_CONTROLLER_HIGH_PRIORITY_BYPASSMemory controller high priority bypassMEMORY_CONTROLLER_MEDIUM_PRIORITY_BYPASSMemory controller medium priority bypassDCT0_DCQ_BYPASSDCT0 DCQ bypassDCT1_DCQ_BYPASSDCT1 DCQ bypassNUM_HTC_TRIP_POINT_CROSSEDNumber of times the HTC trip point is crossedNUM_CLOCKS_HTC_PSTATE_INACTIVENumber of clocks HTC P-state is inactiveNUM_CLOCKS_HTC_PSTATE_ACTIVENumber of clocks HTC P-state is activeREMOTE_IO_TO_LOCAL_IORemote IO to Local IOREMOTE_CPU_TO_LOCAL_IORemote CPU to Local IOLOCAL_IO_TO_REMOTE_IOLocal IO to Remote IOLOCAL_IO_TO_REMOTE_MEMLocal IO to Remote MemLOCAL_CPU_TO_REMOTE_IOLocal CPU to Remote IOLOCAL_CPU_TO_REMOTE_MEMLocal CPU to Remote MemLOCAL_IO_TO_LOCAL_IOLocal IO to Local IOLOCAL_IO_TO_LOCAL_MEMLocal IO to Local MemLOCAL_CPU_TO_LOCAL_IOLocal CPU to Local IOLOCAL_CPU_TO_LOCAL_MEMLocal CPU to Local MemVICTIM_BLOCKVictim Block (Writeback)READ_BLOCKRead Block (Dcache load miss refill)READ_BLOCK_SHAREDRead Block Shared (Icache refill)READ_BLOCK_MODIFIEDRead Block Modified (Dcache store miss refill)CHANGE_TO_DIRTYChange-to-Dirty (first store to clean block already in cache)NON-POSTED_SZWR_BYTENon-Posted SzWr Byte (1-32 bytes). Typical Usage: Legacy or mapped IO, typically 1-4 bytes.NON-POSTED_SZWR_DWNon-Posted SzWr DW (1-16 dwords). Typical Usage: Legacy or mapped IO, typically 1POSTED_SZWR_BYTEPosted SzWr Byte (1-32 bytes). Typical Usage: Subcache-line DMA writes, size varies; alsoPOSTED_SZWR_DWPosted SzWr DW (1-16 dwords). Typical Usage: Block-oriented DMA writes, often cache-lineSZRD_BYTESzRd Byte (4 bytes). Typical Usage: Legacy or mapped IO.SZRD_DWSzRd DW (1-16 dwords). Typical Usage: Block-oriented DMA reads, typically cache-line size.PROBE_MISSProbe missPROBE_HIT_CLEANProbe hit cleanPROBE_HIT_DIRTY_WITHOUT_MEMORY_CANCELProbe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)PROBE_HIT_DIRTY_WITH_MEMORY_CANCELProbe hit dirty with memory cancel (probed by DMA read or cache refill request)UPSTREAM_DISPLAY_REFRESH_ISOC_READSUpstream display refresh/ISOC readsUPSTREAM_NON-DISPLAY_REFRESH_READSUpstream non-display refresh readsUPSTREAM_ISOC_WRITESUpstream ISOC writesUPSTREAM_NON-ISOC_WRITESUpstream non-ISOC writesGART_APERTURE_HIT_ON_ACCESS_FROM_CPUGART aperture hit on access from CPUGART_APERTURE_HIT_ON_ACCESS_FROM_IOGART aperture hit on access from IOGART_MISSGART missGART_REQUEST_HIT_TABLE_WALK_IN_PROGRESSGART Request hit table walk in progressGART_MULTIPLE_TABLE_WALK_IN_PROGRESSGART multiple table walk in progressCOMMAND_DW_SENTCommand DW sentDATA_DW_SENTData DW sentBUFFER_RELEASE_DW_SENTBuffer release DW sentNOP_DW_SENTNOP DW sent (idle)ADDRESS_DW_SENTAddress (including extensions) DW sentPER_PACKET_CRC_SENTPer packet CRC sentSUBLINK_1When links are unganged, enable this umask to select sublink 1SUBLINK_0When links are unganged, enable this umask to select sublink 0 (default when links ganged)LOCAL_TO_NODE_0From Local node to Node 0LOCAL_TO_NODE_1From Local node to Node 1LOCAL_TO_NODE_2From Local node to Node 2LOCAL_TO_NODE_3From Local node to Node 3LOCAL_TO_NODE_4From Local node to Node 4LOCAL_TO_NODE_5From Local node to Node 5LOCAL_TO_NODE_6From Local node to Node 6LOCAL_TO_NODE_7From Local node to Node 7READ_BLOCK_LOCAL_TO_NODE_0Read block From Local node to Node 0READ_BLOCK_SHARED_LOCAL_TO_NODE_0Read block shared From Local node to Node 0READ_BLOCK_MODIFIED_LOCAL_TO_NODE_0Read block modified From Local node to Node 0CHANGE_TO_DIRTY_LOCAL_TO_NODE_0Change-to-Dirty From Local node to Node 0READ_BLOCK_LOCAL_TO_NODE_1Read block From Local node to Node 1READ_BLOCK_SHARED_LOCAL_TO_NODE_1Read block shared From Local node to Node 1READ_BLOCK_MODIFIED_LOCAL_TO_NODE_1Read block modified From Local node to Node 1CHANGE_TO_DIRTY_LOCAL_TO_NODE_1Change-to-Dirty From Local node to Node 1READ_BLOCK_LOCAL_TO_NODE_2Read block From Local node to Node 2READ_BLOCK_SHARED_LOCAL_TO_NODE_2Read block shared From Local node to Node 2READ_BLOCK_MODIFIED_LOCAL_TO_NODE_2Read block modified From Local node to Node 2CHANGE_TO_DIRTY_LOCAL_TO_NODE_2Change-to-Dirty From Local node to Node 2READ_BLOCK_LOCAL_TO_NODE_3Read block From Local node to Node 3READ_BLOCK_SHARED_LOCAL_TO_NODE_3Read block shared From Local node to Node 3READ_BLOCK_MODIFIED_LOCAL_TO_NODE_3Read block modified From Local node to Node 3CHANGE_TO_DIRTY_LOCAL_TO_NODE_3Change-to-Dirty From Local node to Node 3READ_BLOCK_LOCAL_TO_NODE_4Read block From Local node to Node 4READ_BLOCK_SHARED_LOCAL_TO_NODE_4Read block shared From Local node to Node 4READ_BLOCK_MODIFIED_LOCAL_TO_NODE_4Read block modified From Local node to Node 4CHANGE_TO_DIRTY_LOCAL_TO_NODE_4Change-to-Dirty From Local node to Node 4READ_BLOCK_LOCAL_TO_NODE_5Read block From Local node to Node 5READ_BLOCK_SHARED_LOCAL_TO_NODE_5Read block shared From Local node to Node 5READ_BLOCK_MODIFIED_LOCAL_TO_NODE_5Read block modified From Local node to Node 5CHANGE_TO_DIRTY_LOCAL_TO_NODE_5Change-to-Dirty From Local node to Node 5READ_BLOCK_LOCAL_TO_NODE_6Read block From Local node to Node 6READ_BLOCK_SHARED_LOCAL_TO_NODE_6Read block shared From Local node to Node 6READ_BLOCK_MODIFIED_LOCAL_TO_NODE_6Read block modified From Local node to Node 6CHANGE_TO_DIRTY_LOCAL_TO_NODE_6Change-to-Dirty From Local node to Node 6READ_BLOCK_LOCAL_TO_NODE_7Read block From Local node to Node 7READ_BLOCK_SHARED_LOCAL_TO_NODE_7Read block shared From Local node to Node 7READ_BLOCK_MODIFIED_LOCAL_TO_NODE_7Read block modified From Local node to Node 7CHANGE_TO_DIRTY_LOCAL_TO_NODE_7Change-to-Dirty From Local node to Node 7READ_SIZED_LOCAL_TO_NODE_0Read Sized From Local node to Node 0WRITE_SIZED_LOCAL_TO_NODE_0Write Sized From Local node to Node 0VICTIM_BLOCK_LOCAL_TO_NODE_0Victim Block From Local node to Node 0READ_SIZED_LOCAL_TO_NODE_1Read Sized From Local node to Node 1WRITE_SIZED_LOCAL_TO_NODE_1Write Sized From Local node to Node 1VICTIM_BLOCK_LOCAL_TO_NODE_1Victim Block From Local node to Node 1READ_SIZED_LOCAL_TO_NODE_2Read Sized From Local node to Node 2WRITE_SIZED_LOCAL_TO_NODE_2Write Sized From Local node to Node 2VICTIM_BLOCK_LOCAL_TO_NODE_2Victim Block From Local node to Node 2READ_SIZED_LOCAL_TO_NODE_3Read Sized From Local node to Node 3WRITE_SIZED_LOCAL_TO_NODE_3Write Sized From Local node to Node 3VICTIM_BLOCK_LOCAL_TO_NODE_3Victim Block From Local node to Node 3READ_SIZED_LOCAL_TO_NODE_4Read Sized From Local node to Node 4WRITE_SIZED_LOCAL_TO_NODE_4Write Sized From Local node to Node 4VICTIM_BLOCK_LOCAL_TO_NODE_4Victim Block From Local node to Node 4READ_SIZED_LOCAL_TO_NODE_5Read Sized From Local node to Node 5WRITE_SIZED_LOCAL_TO_NODE_5Write Sized From Local node to Node 5VICTIM_BLOCK_LOCAL_TO_NODE_5Victim Block From Local node to Node 5READ_SIZED_LOCAL_TO_NODE_6Read Sized From Local node to Node 6WRITE_SIZED_LOCAL_TO_NODE_6Write Sized From Local node to Node 6VICTIM_BLOCK_LOCAL_TO_NODE_6Victim Block From Local node to Node 6READ_SIZED_LOCAL_TO_NODE_7Read Sized From Local node to Node 7WRITE_SIZED_LOCAL_TO_NODE_7Write Sized From Local node to Node 7VICTIM_BLOCK_LOCAL_TO_NODE_7Victim Block From Local node to Node 7ALL_LOCAL_TO_NODE_0_3All From Local node to Node 0-3ALL_LOCAL_TO_NODE_4_7All From Local node to Node 4-7PROBE_HIT_SProbe Hit SPROBE_HIT_EProbe Hit EPROBE_HIT_MUW_OR_OProbe Hit MuW or OPROBE_HIT_MProbe Hit MProbe MissDIRECTED_PROBEDirected ProbeTRACK_CACHE_STAT_FOR_RDBLKTrack Cache Stat for RdBlkTRACK_CACHE_STAT_FOR_RDBLKSTrack Cache Stat for RdBlkSTRACK_CACHE_STAT_FOR_CHGTODIRTYTrack Cache Stat for ChgToDirtyTRACK_CACHE_STAT_FOR_RDBLKMTrack Cache Stat for RdBlkMWRITE_REQUESTS_TO_DCTWrite requests sent to the DCTREAD_REQUESTS_TO_DCTRead requests (including prefetch requests) sent to the DCTPREFETCH_REQUESTS_TO_DCTPrefetch requests sent to the DCT32_BYTES_SIZED_WRITES32 Bytes Sized Writes64_BYTES_SIZED_WRITES64 Bytes Sized Writes32_BYTES_SIZED_READS32 Bytes Sized Reads64_BYTE_SIZED_READS64 Byte Sized ReadsREAD_REQUESTS_TO_DCT_WHILE_WRITES_PENDINGRead requests sent to the DCT while writes requests are pending in the DCTREAD_BLOCK_EXCLUSIVERead Block Exclusive (Data cache read)Read Block Shared (Instruction cache read)READ_BLOCK_MODIFYRead Block ModifyPREFETCHCount prefetches onlyREAD_BLOCK_ANYCount any read requestCORE_0Measure on Core0CORE_1Measure on Core1CORE_2Measure on Core2CORE_3Measure on Core3CORE_4Measure on Core4CORE_5Measure on Core5CORE_6Measure on Core6CORE_7Measure on Core7ANY_COREMeasure on any coreModifiedL3_REQUEST_CYCLEL3 Request cycle count.L3_REQUESTL3 request count.DRAM_ACCESSESDRAM AccessesDRAM_CONTROLLER_PAGE_TABLE_OVERFLOWSDRAM Controller Page Table OverflowsMEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSEDMemory Controller DRAM Command Slots MissedMEMORY_CONTROLLER_TURNAROUNDSMemory Controller TurnaroundsMEMORY_CONTROLLER_BYPASS_COUNTER_SATURATIONMemory Controller Bypass Counter SaturationTHERMAL_STATUSThermal StatusCPU_IO_REQUESTS_TO_MEMORY_IOCPU/IO Requests to Memory/IOCACHE_BLOCK_COMMANDSCache Block CommandsSIZED_COMMANDSSized CommandsPROBE_RESPONSES_AND_UPSTREAM_REQUESTSProbe Responses and Upstream RequestsGART_EVENTSGART EventsLINK_TRANSMIT_BANDWIDTH_LINK_0Link Transmit Bandwidth Link 0LINK_TRANSMIT_BANDWIDTH_LINK_1Link Transmit Bandwidth Link 1LINK_TRANSMIT_BANDWIDTH_LINK_2Link Transmit Bandwidth Link 2LINK_TRANSMIT_BANDWIDTH_LINK_3Link Transmit Bandwidth Link 3CPU_TO_DRAM_REQUESTS_TO_TARGET_NODECPU to DRAM Requests to Target NodeIO_TO_DRAM_REQUESTS_TO_TARGET_NODEIO to DRAM Requests to Target NodeCPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3CPU Read Command Latency to Target Node 0-3CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3CPU Read Command Requests to Target Node 0-3CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7CPU Read Command Latency to Target Node 4-7CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7CPU Read Command Requests to Target Node 4-7CPU_COMMAND_LATENCY_TO_TARGET_NODECPU Command Latency to Target NodeCPU_REQUESTS_TO_TARGET_NODECPU Requests to Target NodeREQUEST_CACHE_STATUS_0Request Cache Status 0REQUEST_CACHE_STATUS_1Request Cache Status 1MEMORY_CONTROLLER_REQUESTSMemory Controller RequestsREAD_REQUEST_TO_L3_CACHERead Request to L3 CacheL3_CACHE_MISSESL3 Cache MissesL3_FILLS_CAUSED_BY_L2_EVICTIONSL3 Fills caused by L2 EvictionsL3_EVICTIONSL3 EvictionsNON_CANCELED_L3_READ_REQUESTSNon-canceled L3 Read RequestsL3_LATENCYL3 LatencyAMD64 Fam15h Interlagosamd64_fam15h_interlagosAMD64 Fam15h NorthBridgeamd64_fam15h_nbamd_nbIF1GTBDIF2MIF4KSSE_INSTRMMX_INSTRX87_INSTRIBS_COUNT_ROLLOVERNumber of times a uop could not be tagged by IBS because of a previous tagged uop that has not retired.IBS_TAGGED_OPS_RETNumber of uops tagged by IBS that retired.IBS_TAGGED_OPSNumber of uops tagged by IBS.OPTIMIZEDNumber of scalar ops optimized.OPT_POTENTIALNumber of ops that are candidates for optimization (have z-bit either set or pass.SSE_MOV_OPS_ELIMNumber of SSE move ops eliminated.SSE_MOV_OPSNumber of SSE move ops.DP_MULT_ADD_FLOPSDouble precision multiply-add flops.DP_DIV_FLOPSDouble precision divide/square root flops.DP_MULT_FLOPSDouble precision multiply flops.DP_ADD_SUB_FLOPSDouble precision add/subtract flops.SP_MULT_ADD_FLOPSSingle precision multiply-add flops.SP_DIV_FLOPSSingle precision divide/square root flops.SP_MULT_FLOPSSingle precision multiply flops.SP_ADD_SUB_FLOPSSingle precision add/subtract flops.X87_CTRL_RETX87 control word mispredict traps due to mispredction in RC or PC, or changes in mask bits.X87_BOT_RETX87 bottom-executing uops retired.SSE_CTRL_RETSSE control word mispreduct traps due to mispredctions in RC, FTZ or DAZ or changes in mask bits.SSE_BOT_RETSSE bottom-executing uops retired.DIV_SQR_R_OPSDivide and square root opsMUL_OPSMultiple opsADD_SUB_OPSAdd/subtract opsDUAL3Total number of multi-pipe uops assigned to pipe3DUAL2Total number of multi-pipe uops assigned to pipe2DUAL1Total number of multi-pipe uops assigned to pipe1DUAL0Total number of multi-pipe uops assigned to pipe0TOTAL3Total number of uops assigned to pipe3TOTAL2Total number of uops assigned to pipe2TOTAL1Total number of uops assigned to pipe1TOTAL0Total number of uops assigned to pipe0L2_INVALIDATING_PROBEIC line invalidated due to L2 invalidating probe (external or LS).FILL_INVALIDATEDIC line invalidated due to overwriting fill response.IC_STALL_ANYIC pipe was stalled during this clock cycle for any reason (nothing valud in pipe ICM1).IC_STALL_DQ_EMPTYIC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty.IC_STALL_BACK_PRESSUREIC pipe was stalled during this clock cycle (ncluding IC to OC fetches) due to back pressure.LS_RD_BLK_C_SLoad/Store ReadBlock C/S hitLS_RD_BLK_L_HIT_XLoad/Store Readblock L hit eXclusive.LS_RD_BLK_L_HIT_SLoad/Store ReadBlock L hit Shared.LS_RD_BLK_XLoad/Store ReadblockX/ChangeToX hit eXclusive.LS_RD_BLK_CLoad/Store ReadBlock C S L X Change To X Miss.IC_FILL_HIT_XIcache fill hit eXclusive.IC_FILL_HIT_SIcache fill hit Shared.IC_FILL_MISSIcache fill miss.L2_FILL_BUSYL2_CYCLES_WAITING_ON_FILLSRD_BLK_LRD_BLK_XCACHEABLE_IC_READCHANGE_TO_XPREFETCH_L2L2_HW_PFOTHER_REQUESTSGROUP1LS_RD_SIZEDLS_RD_SIZED_N_CIC_RD_SIZEDIC_RD_SIZED_N_CSMC_INVALBUS_LOCKS_ORIGINATORBUS_LOCKS_RESPONSESWCB_WRITEWCB_CLOSECACHE_LINE_FLUSHI_LINE_FLUSHZERO_BYTE_STORELOCAL_IC_CLRC_L_ZEROLD_ST_DISPATCHLoad/Store uops dispatched.STORE_DISPATCHStore uops dispatched.LD_DISPATCHLoad uops dispatched.MAB_MCH_CNTDATA_PIPE_SW_PF_DC_HITTLB_RELOAD_1G_L2_MISSTLB_RELOAD_2M_L2_MISSTLB_RELOAD_32K_L2_MISSTLB_RELOAD_4K_L2_MISSTLB_RELOAD_1G_L2_HITTLB_RELOAD_2M_L2_HITTLB_RELOAD_32K_L2_HITTLB_RELOAD_4K_L2_HITSPEC_LOCK_MAP_COMMITSPEC_LOCKNON_SPEC_LOCKBUS_LOCKTLB_PIPE_EARLYHW_PFhw_pfTLB_PIPE_LATEST_PIPEDATA_PIPEPREFETCH_NTANon-temporal prefetches.STORE_PREFETCH_WLOAD_PREFETCH_WALLOC_ISIDE1ALLOC_ISIDE0ALLOC_DSIDE1ALLOC_DSIDE0OC_IC_MODE_SWITCHIC_OC_MODE_SWITCHRETIRE_TOKEN_STALLRetire tokens unavailableAGSQ_TOKEN_STALLAGSQ tokens unavailableALU_TOKEN_STALLALU tokens unavailableALSQ3_0_TOKEN_STALLALSQ3_TOKEN_STALLALSQ3 tokens unavailableALSQ2_TOKEN_STALLALSQ2 tokens unavailableALSQ1_TOKEN_STALLALSQ1 tokens unavailableL1_ITLB_MISS_L2_ITLB_HITThe number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB.L1_ITLB_MISS_L2_ITLB_MISSThe number of instruction fetches that miss in both the L1 and L2 TLBs.PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBEThe number of pipeline restarts caused by invalidating probes that hit on the instruction stream currently being executed. This would happen if the active instruction stream was being modified by another processor in an MP system - typically a highly unlikely event.ITLB_RELOADSThe number of ITLB reload requests.DIV_CYCLES_BUSY_COUNTDIV_OP_COUNTRETIRED_BRANCH_INSTRUCTIONSThe number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts.RETIRED_FAR_CONTROL_TRANSFERSThe number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction.RETIRED_INDIRECT_BRANCH_INSTRUCTIONS_MISPREDICTEDRETIRED_BRANCH_INSTRUCTIONS_MISPREDICTEDThe number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts).RETIRED_BRANCH_RESYNCSThe number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare.RETIRED_TAKEN_BRANCH_INSTRUCTIONSThe number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts.RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDThe number of retired taken branch instructions that were mispredicted.RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONSRETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS_MISPREDICTEDRETIRED_UOPSThe number of uops retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4.RETIRED_FUSED_BRANCH_INSTRUCTIONSThe number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3.RETIRED_INSTRUCTIONSInstructions Retired.RETIRED_MMX_FP_INSTRUCTIONSThe number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS.RETIRED_NEAR_RETURNSThe number of near return instructions (RET or RETI) retired.RETIRED_NEAR_RETURNS_MISPREDICTEDThe number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction.TAGGED_IBS_OPSNUMBER_OF_MOVE_ELIMINATION_AND_SCALAR_OP_OPTIMIZATIONThis is a dispatch based speculative event. It is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.RETIRED_SSE_AVX_OPERATIONSThis is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15.RETIRED_SERIALIZING_OPSThe number of serializing Ops retired.RETIRED_X87_FLOATING_POINT_OPERATIONSThe number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8.FP_SCHEDULER_EMPTYThis is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the scheduler. Invert this to count cycles in which at least one FPU operation is present in the FPU.FPU_PIPE_ASSIGNMENTThe number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. (See Core::X86::Pmc::Core::ExRetMmxFpInstr). Since this event includes non-numeric operations it is not suitable for measuring MFLOPS.INSTRUCTION_CACHE_REFILLS_FROM_L2The number of 64-byte instruction cachelines that was fulfilled by the L2 cache.INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMThe number of 64-byte instruction cachelines fulfilled from system memory or another cache.INSTRUCTION_CACHE_LINES_INVALIDATEDThe number of instruction cachelines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.INSTRUCTION_PIPE_STALL32_BYTE_INSTRUCTION_CACHE_FETCHThe number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses).32_BYTE_INSTRUCTION_CACHE_MISSESThe number of 32B fetch windows tried to read the L1 IC and missed in the full tag.CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUSThis event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher.CYCLES_WITH_FILL_PENDING_FROM_L2Total cycles spent with one or more fill requests in flight from L2.L2_LATENCYTotal cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. This may be used to calculate average latency by multiplying this count by four and then dividing by the total number of L2 fills (umask L2RequestG1). Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used.REQUESTS_TO_L2_GROUP1REQUESTS_TO_L2_GROUP2Multi-events in that LS and IF requests can be received simultaneous.LS_TO_L2_WBC_REQUESTSDATA_CACHE_ACCESSESThe number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event.LS_DISPATCHCounts the number of operations dispatched to the LS unit. Unit Masks ADDed.INEFFECTIVE_SOFTWARE_PREFETCHThe number of software prefetches that did not fetch data outside of the processor core.L1_DTLB_MISSL1 Data TLB misses.LOCKSLock operations. Unit masks ORedMAB_ALLOCATION_BY_PIPEMISALIGNED_LOADSCYCLES_NOT_IN_HALTPREFETCH_INSTRUCTIONS_DISPATCHEDSoftware Prefetch Instructions Dispatched.STORE_TO_LOAD_FORWARDNumber of STore Lad Forward hits.TABLEWALKER_ALLOCATIONMERGESee .L1_BTB_CORRECTIONL2_BTB_CORRECTIONOC_MODE_SWITCHDYNAMIC_TOKENS_DISPATCH_STALLS_CYCLES_0Cycles where a dispatch group is valid but does not get dispatched due to a token stall.AMD64 Fam17h Zenamd64_fam17hPIPE0Pipe0 dispatchesPIPE1Pipe1 dispatchesALLAll sub-events selectedSINGLE_ADD_SUB_OPSSingle precision add/subtract opsSINGLE_MUL_OPSSingle precision multiply opsSINGLE_DIV_OPSSingle precision divide/square root opsDOUBLE_ADD_SUB_OPSDouble precision add/subtract opsDOUBLE_MUL_OPSDouble precision multiply opsDOUBLE_DIV_OPSDouble precision divide/square root opsSSE_BOTTOM_EXECUTING_UOPSSSE bottom-executing uops retiredSSE_CONTROL_RENAMING_UOPSSSE control-renaming uops retiredX87_BOTTOM_EXECUTING_UOPSX87 bottom-executing uops retiredX87_CONTROL_RENAMING_UOPSX87 control-renaming uops retiredADD_AND_SUBAdd and subtractMULTIPLYMultiplyDIVIDE_AND_FSQRTDivide and fsqrtESCSSSDSFSGSHSINVALIDATING_PROBESEvictions caused by invalidating probesFILLSEvictions caused by fillsEXECUTEDThe number of locked instructions executedCYCLES_TO_ACQUIREThe number of cycles to acquire bus lockCYCLES_TO_UNLOCKThe number of cycles to unlock cache lineLOADSThe number of loadsSTORESThe number of storesLOAD_OP_STORESThe number of load-op-storesADDRESS_MISMATCHESAddress mismatches (starting byte not the same).STORE_IS_SMALLER_THAN_LOADStore is smaller than load.MISALIGNEDMisaligned.NON_CACHABLENon-cachableSHAREDSharedEXCLUSIVEExclusiveOWNEDOwnedMODIFIEDModifiednon-cachableEVICTEDEvicted from probeShared evictionExclusive evictionOwned evictionModified evictionSTORES_L1TLBStores that miss L1TLBLOADS_L1TLBLoads that miss L1TLBSTORES_L2TLBStores that miss L2TLBLOADS_L2TLBLoads that miss L2TLBMISALIGN_16BMisaligns that cross 16 Byte boundaryMISALIGN_4KBMisaligns that cross a 4kB boundaryLOADLoad (Prefetch, PrefetchT0/T1/T2)STOREStore (PrefetchW)NTANTA (PrefetchNTA)L1_4K_TLB_HITL1 4K TLB hitL1_2M_TLB_HITL1 2M TLB hitSW_PREFETCH_DATA_CACHESoftware prefetch hit in data cacheSW_PREFETCH_PENDING_FILLSoftware prefetch hit a pending fillSW_PREFETCH_MABSoftware prefetches that don't get a MABSW_PREFETCH_HIT_L2Software prefetches that hit in L2READ_BYTERead byteREAD_DOUBLEWORDRead doublewordWRITE_BYTEWrite byteWRITE_DOUBLEWORDWrite doublewordREAD_BLOCKRead blockRDBLKMODRdBlkModREAD_BLOCK_SHAREDRead block sharedREAD_BLOCK_SPECRead block speculativeREAD_BLOCK_SPEC_MODRead block speculative modifiedREAD_BLOCK_SPEC_SHAREDRead block speculative sharedCHANGE_DIRTYChange to dirtyNON_CACHEABLERequests to non-cacheable (UC) memoryWRITE_COMBININGRequests to write-combining (WC) memory or WC buffer flushes to WB memorySTREAMING_STOREStreaming store (SS) requestsATTEMPTEDPrefetch attemptsMABHits on MABDC_MISS0Data cache miss buffer 0DC_MISS1Data cache miss buffer 1DC_MISS2Data cache miss buffer 2DC_MISS3Data cache miss buffer 3DC_MISS4Data cache miss buffer 4DC_MISS5Data cache miss buffer 5DC_MISS6Data cache miss buffer 6DC_MISS7Data cache miss buffer 7IC_MISS0Instruction cache miss buffer 0IC_MISS1Instruction cache miss buffer 1DC_ANYAny data cache miss bufferIC_ANYAny instruction cache miss bufferDATA_ERRORData ErrorChange to dirty successUNCACHEABLEUncacheableDATA_LINE_EVICTIONSData line evictionsINSTRUCTION_ATTRIBUTE_EVICTIONSInstruction attribute evictionsBYTE_ENABLE_MASK_UNCACHEABLEByte enable mask for uncacheabe or I/O storeDATA_FOR_UNCACHEABLEData for uncacheabe or I/O storeBYTE_ENABLE_MASK_WRITE_COMBINEByte enable mask for write combine context flushDATA_FOR_WRITE_COMBINEData for write combine contet flushDC_INVALIDATES_ICModification of instructions of data too close to codeDC_INVALIDATES_DCCD or WBINVDIC_INVALIDATES_ICaliasingIC_INVALIDATES_DC_DIRTYExection of modified instruction or data too close to codeIC_HITS_DC_CLEAN_LINEReading codeDC_PROBE_REJECTED_EARLYDC probe rejected earlyDC_PROBE_REJECTED_LATEDC probe rejected lateHOST_PDE_LEVELHost: PDE levelHOST_PDPE_LEVELHost: PDPE levelHOST_PML4E_LEVELHost: PML4E levelGUEST_PDE_LEVELGuest: PDE levelGUEST_PDPE_LEVELGuest: PDPE levelGUEST_PML4E_LEVELGuest: PML4E level4K_PAGE_FETCHESInstruction fetches to a 4K page.2M_PAGE_FETCHESInstruction fetches to a 2M page.IC_INVALIDATE_LS_PROBEInstruction cache invalidate due to LS probeIC_INVALIDATE_BU_PROBEInstruction cache invalidate due to BU probeRETIREDRetired indirect branch instruction.MISPREDICTEDRetired mispredicted near unconditional jump.X87X87 instructionsSSESSE, SSE2, SSE3, MNI instructionsX87_RECLASS_MICROFAULTSX87 reclass microfaultsSSE_RETYPE_MICROFAULTSSSE retype microfaultsSSE_RECLASS_MICROFAULTSSSE reclass microfaultsSSE_AND_X87_MICROTRAPSSSE and x87 microtrapsDISPATCHED_FPUDispatched FPU OperationsFP_SCHEDULER_EMPTYCycles in which the FPU is EmptyDISPATCHED_FPU_OPS_FAST_FLAGDispatched Fast Flag FPU OperationsRETIRED_SSE_AVX_OPERATIONSRetired SSE/AVX OperationsRETIRED_SERIALIZING_OPSRetired Serializing OpsRETIRED_X87_OPERATIONSRetired x87 operationsSEGMENT_REGISTER_LOADSSegment Register LoadsPIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODEPipeline Restart Due to Self-Modifying CodePIPELINE_RESTART_DUE_TO_PROBE_HITPipeline Restart Due to Probe HitLOCKED_OPSLocked OperationsRETIRED_CLFLUSH_INSTRUCTIONSRetired CLFLUSH InstructionsRETIRED_CPUID_INSTRUCTIONSRetired CPUID InstructionsLS_DISPATCHTransactions dispatched to load-store unitCANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONSCancelled Store to Load Forward OperationsDATA_CACHE_ACCESSESData Cache AccessesDATA_CACHE_MISSESData Cache MissesDATA_CACHE_REFILLSData Cache Refills from L2 or NorthbridgeDATA_CACHE_REFILLS_FROM_NORTHBRIDGEData Cache Refills from the NorthbridgeDATA_CACHE_LINES_EVICTEDData Cache Lines EvictedL1_DTLB_MISS_AND_L2_DTLB_HITL1 DTLB Miss and L2 DTLB HitDTLB_MISSL1 DTLB and L2 DTLB MissMISALIGNED_ACCESSESMisaligned AccessesPREFETCH_INSTRUCTIONS_DISPATCHEDPrefetch Instructions DispatchedDCACHE_MISSES_BY_LOCKED_INSTRUCTIONSDCACHE Misses by Locked InstructionsL1_DTLB_HITL1 DTLB HitINEFFECTIVE_SW_PREFETCHESIneffective Software PrefetchesGLOBAL_TLB_FLUSHESGlobal TLB FlushesCOMMAND_RELATED_UNCACHABLECommands realted to uncachable memory and I/OCOMMAND_RELATED_READ_BLOCKCommands realted to read block operationsCOMMAND_RELATED_DIRTYCommands realted to change dirty operationsMEMORY_REQUESTSMemory Requests by TypeDATA_PREFETCHESData PrefetchesMAB_REQUESTSMiss address buffer requestsMAB_WAIT_CYCLESMiss address buffer wait cyclesSYSTEM_RESPONSESL2I Responses by Coherency StateDATA_WRITTEN_TO_SYSTEM16-byte transfers written to systemCACHE_CROSS_INVALIDATESInternal probes causing cache lines to be invalidatedCPU_CLK_UNHALTEDCPU Clocks not HaltedPDC_MISSNumber of PDC missesINSTRUCTION_CACHE_FETCHESInstruction Cache FetchesINSTRUCTION_CACHE_MISSESInstruction Cache MissesINSTRUCTION_CACHE_REFILLS_FROM_L2Instruction Cache Refills from L2INSTRUCTION_CACHE_REFILLS_FROM_SYSTEMInstruction Cache Refills from SystemL1_ITLB_MISS_AND_L2_ITLB_HITL1 ITLB Miss and L2 ITLB HitITLB_MISSInstruction fetches that miss in 4k and 2M ITLBINSTRUCTION_FETCH_STALLInstruction Fetch StallRETURN_STACK_HITSReturn Stack HitsRETURN_STACK_OVERFLOWSReturn Stack OverflowsINSTRUCTION_CACHE_VICTIMSInstruction Cache VictimsINSTRUCTION_CACHE_LINES_INVALIDATEDInstruction Cache Lines InvalidatedITLB_RELOADSITLB ReloadsITLB_RELOADS_ABORTEDITLB reloads abortedRETIRED_INDIRECT_BRANCH_INFORetired indirect branch infoRETIRED_INSTRUCTIONSRetired InstructionsRETIRED_UOPSRetired uopsRETIRED_BRANCH_INSTRUCTIONSRetired Branch InstructionsRETIRED_MISPREDICTED_BRANCH_INSTRUCTIONSRetired Mispredicted Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONSRetired Taken Branch InstructionsRETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTEDRetired Taken Branch Instructions MispredictedRETIRED_FAR_CONTROL_TRANSFERSRetired Far Control TransfersRETIRED_BRANCH_RESYNCSRetired Branch ResyncsRETIRED_NEAR_RETURNSRetired Near ReturnsRETIRED_NEAR_RETURNS_MISPREDICTEDRetired Near Returns MispredictedRETIRED_MISPREDICTED_TAKENRetired mispredicted taken branches due to target mismatchRETIRED_MMX_AND_FP_INSTRUCTIONSRetired MMX/FP InstructionsINTERRUPTS_MASKED_CYCLESInterrupts-Masked CyclesINTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDINGInterrupts-Masked Cycles with Interrupt PendingINTERRUPTS_TAKENInterrupts TakenFPU_EXCEPTIONSFPU ExceptionsDR0_BREAKPOINT_MATCHESDR0 Breakpoint MatchesDR1_BREAKPOINT_MATCHESDR1 Breakpoint MatchesDR2_BREAKPOINT_MATCHESDR2 Breakpoint MatchesDR3_BREAKPOINT_MATCHESDR3 Breakpoint MatchesTAGGED_IBS_OPSOps tagged by IBSTAGGED_IBS_OPS_RETIREDOps tagged by IBS that retiredAMD64 Fam16h Jaguaramd64_fam16h;h2U3 0 P p  & ; W s  8 X c x  M @ C`  l j  L 5 @ h : g G" ' M'( X'H 'h ( ) + , 32608P4>> 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