NVRrj Linux3#86~20.04.2-Ubuntu SMP Mon Jul 17 23:27:17 UTC 2023"AMD Ryzen 7 3700X 8-Core Processor"x86_640"(2 127.0.0.1 w"(2k 127.0.0.1Y/usr/local/nsight-compute-2023.3.1/extras/samples/sharedBankConflicts/sharedBankConflictsU"XELF3u'VV@@.shstrtab.strtab.symtab.symtab_shndx.nv.info.text._Z24transposeNoBankConflictsPfS_ii.nv.info._Z24transposeNoBankConflictsPfS_ii.nv.shared._Z24transposeNoBankConflictsPfS_ii.nv.constant0._Z24transposeNoBankConflictsPfS_ii.text._Z18transposeCoalescedPfS_ii.nv.info._Z18transposeCoalescedPfS_ii.nv.shared._Z18transposeCoalescedPfS_ii.nv.constant0._Z18transposeCoalescedPfS_ii.debug_frame.debug_line.rel.debug_line.nv_debug_line_sass.rel.nv_debug_line_sass.nv_debug_ptx_txt.rel.debug_frame.rela.debug_frame.nv.rel.action.shstrtab.strtab.symtab.symtab_shndx.nv.info_Z24transposeNoBankConflictsPfS_ii.text._Z24transposeNoBankConflictsPfS_ii.nv.info._Z24transposeNoBankConflictsPfS_ii.nv.shared._Z24transposeNoBankConflictsPfS_ii$___ZZ24transposeNoBankConflictsPfS_iiE4tile__113.nv.constant0._Z24transposeNoBankConflictsPfS_ii_param_Z18transposeCoalescedPfS_ii.text._Z18transposeCoalescedPfS_ii.nv.info._Z18transposeCoalescedPfS_ii.nv.shared._Z18transposeCoalescedPfS_ii$___ZZ18transposeCoalescedPfS_iiE4tile__29.nv.constant0._Z18transposeCoalescedPfS_ii.debug_frame.debug_line.rel.debug_line.nv_debug_line_sass.rel.nv_debug_line_sass.nv_debug_ptx_txt.rel.debug_frame.rela.debug_frame.nv.rel.actionU _&3O{ 2B(| (((0p (?(| (((0pp (?u /usr/local/nsight-compute-2023.3.1/extras/samples/sharedBankConflictssharedBankConflicts.cuҸާR  w0 w  ty0  w0 w  ty0#   f!qs x uw cvv  f"pr w uv bvv.version 7.7.target sm_86.address_size 64.visible .entry _Z18transposeCoalescedPfS_ii(.param .u64 _Z18transposeCoalescedPfS_ii_param_0,.param .u64 _Z18transposeCoalescedPfS_ii_param_1,.param .u32 _Z18transposeCoalescedPfS_ii_param_2,.param .u32 _Z18transposeCoalescedPfS_ii_param_3){.reg .f32 %f<9>;.reg .b32 %r<26>;.reg .b64 %rd<17>;.shared .align 4 .b8 _ZZ18transposeCoalescedPfS_iiE4tile[4096];ld.param.u64 %rd1, [_Z18transposeCoalescedPfS_ii_param_0];ld.param.u64 %rd2, [_Z18transposeCoalescedPfS_ii_param_1];ld.param.u32 %r1, [_Z18transposeCoalescedPfS_ii_param_2];ld.param.u32 %r2, [_Z18transposeCoalescedPfS_ii_param_3];cvta.to.global.u64 %rd3, %rd2;mov.u32 %r3, %ctaid.x;shl.b32 %r4, %r3, 5;mov.u32 %r5, %tid.x;mov.u32 %r6, %ctaid.y;shl.b32 %r7, %r6, 5;mov.u32 %r8, %tid.y;add.s32 %r9, %r7, %r8;add.s32 %r10, %r4, %r5;mad.lo.s32 %r11, %r9, %r1, %r10;mul.wide.s32 %rd4, %r11, 4;add.s64 %rd5, %rd3, %rd4;ld.global.f32 %f1, [%rd5];shl.b32 %r12, %r8, 7;mov.u32 %r13, _ZZ18transposeCoalescedPfS_iiE4tile;add.s32 %r14, %r13, %r12;shl.b32 %r15, %r5, 2;add.s32 %r16, %r14, %r15;st.shared.f32 [%r16], %f1;shl.b32 %r17, %r1, 3;mul.wide.s32 %rd6, %r17, 4;add.s64 %rd7, %rd5, %rd6;ld.global.f32 %f2, [%rd7];st.shared.f32 [%r16+1024], %f2;add.s64 %rd8, %rd7, %rd6;ld.global.f32 %f3, [%rd8];st.shared.f32 [%r16+2048], %f3;add.s64 %rd9, %rd8, %rd6;ld.global.f32 %f4, [%rd9];st.shared.f32 [%r16+3072], %f4;add.s32 %r18, %r4, %r8;cvta.to.global.u64 %rd10, %rd1;bar.sync 0;add.s32 %r19, %r7, %r5;shl.b32 %r20, %r5, 7;add.s32 %r21, %r13, %r20;shl.b32 %r22, %r8, 2;add.s32 %r23, %r21, %r22;ld.shared.f32 %f5, [%r23];mad.lo.s32 %r24, %r18, %r2, %r19;mul.wide.s32 %rd11, %r24, 4;add.s64 %rd12, %rd10, %rd11;st.global.f32 [%rd12], %f5;ld.shared.f32 %f6, [%r23+32];shl.b32 %r25, %r2, 3;mul.wide.s32 %rd13, %r25, 4;add.s64 %rd14, %rd12, %rd13;st.global.f32 [%rd14], %f6;ld.shared.f32 %f7, [%r23+64];add.s64 %rd15, %rd14, %rd13;st.global.f32 [%rd15], %f7;ld.shared.f32 %f8, [%r23+96];add.s64 %rd16, %rd15, %rd13;st.global.f32 [%rd16], %f8;ret;}.visible .entry _Z24transposeNoBankConflictsPfS_ii(.param .u64 _Z24transposeNoBankConflictsPfS_ii_param_0,.param .u64 _Z24transposeNoBankConflictsPfS_ii_param_1,.param .u32 _Z24transposeNoBankConflictsPfS_ii_param_2,.param .u32 _Z24transposeNoBankConflictsPfS_ii_param_3){.reg .f32 %f<9>;.reg .b32 %r<24>;.reg .b64 %rd<17>;.shared .align 4 .b8 _ZZ24transposeNoBankConflictsPfS_iiE4tile[4224];ld.param.u64 %rd1, [_Z24transposeNoBankConflictsPfS_ii_param_0];ld.param.u64 %rd2, [_Z24transposeNoBankConflictsPfS_ii_param_1];ld.param.u32 %r1, [_Z24transposeNoBankConflictsPfS_ii_param_2];ld.param.u32 %r2, [_Z24transposeNoBankConflictsPfS_ii_param_3];cvta.to.global.u64 %rd3, %rd2;mov.u32 %r3, %ctaid.x;shl.b32 %r4, %r3, 5;mov.u32 %r5, %tid.x;mov.u32 %r6, %ctaid.y;shl.b32 %r7, %r6, 5;mov.u32 %r8, %tid.y;add.s32 %r9, %r7, %r8;add.s32 %r10, %r4, %r5;mad.lo.s32 %r11, %r9, %r1, %r10;mul.wide.s32 %rd4, %r11, 4;add.s64 %rd5, %rd3, %rd4;ld.global.f32 %f1, [%rd5];mov.u32 %r12, _ZZ24transposeNoBankConflictsPfS_iiE4tile;mad.lo.s32 %r13, %r8, 132, %r12;shl.b32 %r14, %r5, 2;add.s32 %r15, %r13, %r14;st.shared.f32 [%r15], %f1;shl.b32 %r16, %r1, 3;mul.wide.s32 %rd6, %r16, 4;add.s64 %rd7, %rd5, %rd6;ld.global.f32 %f2, [%rd7];st.shared.f32 [%r15+1056], %f2;add.s64 %rd8, %rd7, %rd6;ld.global.f32 %f3, [%rd8];st.shared.f32 [%r15+2112], %f3;add.s64 %rd9, %rd8, %rd6;ld.global.f32 %f4, [%rd9];st.shared.f32 [%r15+3168], %f4;add.s32 %r17, %r4, %r8;cvta.to.global.u64 %rd10, %rd1;bar.sync 0;add.s32 %r18, %r7, %r5;mad.lo.s32 %r19, %r5, 132, %r12;shl.b32 %r20, %r8, 2;add.s32 %r21, %r19, %r20;ld.shared.f32 %f5, [%r21];mad.lo.s32 %r22, %r17, %r2, %r18;mul.wide.s32 %rd11, %r22, 4;add.s64 %rd12, %rd10, %rd11;st.global.f32 [%rd12], %f5;ld.shared.f32 %f6, [%r21+32];shl.b32 %r23, %r2, 3;mul.wide.s32 %rd13, %r23, 4;add.s64 %rd14, %rd12, %rd13;st.global.f32 [%rd14], %f6;ld.shared.f32 %f7, [%r21+64];add.s64 %rd15, %rd14, %rd13;st.global.f32 [%rd15], %f7;ld.shared.f32 %f8, [%r21+96];add.s64 %rd16, %rd15, %rd13;st.global.f32 [%rd16], %f8;ret;}/ #   / #   7u5 `   ! !7u5 `   ! !K /" (08 (08 (08,      H z y %"xzF z \y &fx y"hy!"r (/r ($z\%vZ%x y %x y %x y (y b$x!$x!r (r (z ]/$z]x sHOs Hs@Hs` H{y H(y  Hhy@Hy`H%vX%x %x %x y  y  /y Oy MyGyyyyyyyyyyyz y %"xzF z \y &fx y"hy!"r (/r ($z\%vZ%x y %x y %x y (y br(r(r (r (z ]/$z]x sHOsHsHs H{y H(y  Hhy@Hy`H%vX%x %x %x y  y  /y Oy MyGyyyyyyyyyyy@ [ P pP#s' )p`[ph p`h  p      xWx2  # '/'(0 8BR R \/usr/local/nsight-compute-2023.3.1/extras/samples/sharedBankConflicts/sharedBankConflicts.cuR/* * Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of NVIDIA CORPORATION nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* Sample CUDA application for shared memory bank conflicts. * Transposes a N x N square matrix of float elements in * global memory and generates an output matrix in global memory. * */ #include #include #define DEFAULT_KERNEL_OPTION 1 #define DEFAULT_MATRIX_SIZE 512 #define RUNTIME_API_CALL(apiFuncCall) \ do \ { \ cudaError_t _status = apiFuncCall; \ if (_status != cudaSuccess) \ { \ fprintf(stderr, "%s:%d: error: function %s failed with error %s.\n", __FILE__, \ __LINE__, #apiFuncCall, cudaGetErrorString(_status)); \ exit(EXIT_FAILURE); \ } \ } while (0) #define PRINT_PROGRAM_USAGE() \ fprintf(stderr, "Usage: %s [] [] []\n" \ " Default kernel option: %d\n" \ " Use 1 for '%s' and 2 for '%s'\n" \ " Default matrix size: %d\n" \ " Matrix size should be greater than or equal to tile size: %d and" \ " must be an integral multiple of tile size.\n" \ " Default cache config option: none\n" \ " Options: none|shared|l1|equal\n", \ argv[0], DEFAULT_KERNEL_OPTION, \ "transposeCoalesced", "transposeNoBankConflicts", \ DEFAULT_MATRIX_SIZE, TILE_DIM) // Each block transposes a tile of (TILE_DIM x TILE_DIM) elements // using TILE_DIM x BLOCK_ROWS threads, // so that each thread transposes (TILE_DIM / BLOCK_ROWS) elements. // TILE_DIM must be an integral multiple of BLOCK_ROWS #define TILE_DIM 32 #define BLOCK_ROWS 8 // Coalesced global memory transpose with shared memory bank conflicts __global__ void transposeCoalesced(float* odata, float* idata, int width, int height) { __shared__ float tile[TILE_DIM][TILE_DIM]; int xIndex = blockIdx.x * TILE_DIM + threadIdx.x; int yIndex = blockIdx.y * TILE_DIM + threadIdx.y; int indexIn = xIndex + yIndex*width; xIndex = blockIdx.y * TILE_DIM + threadIdx.x; yIndex = blockIdx.x * TILE_DIM + threadIdx.y; int indexOut = xIndex + yIndex*height; for (int i = 0; i < TILE_DIM; i += BLOCK_ROWS) { tile[threadIdx.y + i][threadIdx.x] = idata[indexIn + i * width]; } __syncthreads(); for (int i = 0; i < TILE_DIM; i += BLOCK_ROWS) { odata[indexOut + i * height] = tile[threadIdx.x][threadIdx.y + i]; } } // Coalesced global memory transpose with no shared memory bank conflicts __global__ void transposeNoBankConflicts(float* odata, float* idata, int width, int height) { __shared__ float tile[TILE_DIM][TILE_DIM + 1]; int xIndex = blockIdx.x * TILE_DIM + threadIdx.x; int yIndex = blockIdx.y * TILE_DIM + threadIdx.y; int indexIn = xIndex + yIndex*width; xIndex = blockIdx.y * TILE_DIM + threadIdx.x; yIndex = blockIdx.x * TILE_DIM + threadIdx.y; int indexOut = xIndex + yIndex*height; for (int i = 0; i < TILE_DIM; i += BLOCK_ROWS) { tile[threadIdx.y + i][threadIdx.x] = idata[indexIn + i * width]; } __syncthreads(); for (int i = 0; i < TILE_DIM; i += BLOCK_ROWS) { odata[indexOut + i * height] = tile[threadIdx.x][threadIdx.y + i]; } } void computeTransposeGold(float* gold, float* idata, const int size_x, const int size_y) { for (int y = 0; y < size_y; ++y) { for (int x = 0; x < size_x; ++x) { gold[(x * size_y) + y] = idata[(y * size_x) + x]; } } } bool compareData(const float* reference, const float* data, const unsigned int len) { const float epsilon = 0.01f; for (unsigned int i = 0; i < len; ++i) { float diff = reference[i] - data[i]; if ((diff > epsilon) || (diff < -epsilon)) return false; } return true; } int setCacheConfig(const char *cacheConfigStr, const void *kernel) { const int NumCacheConfigs = 4; const char *cacheConfigOptionsStr[NumCacheConfigs] = { "none", "shared", "l1", "equal"}; cudaFuncCache cacheConfigOptions[NumCacheConfigs] = {cudaFuncCachePreferNone, cudaFuncCachePreferShared, cudaFuncCachePreferL1, cudaFuncCachePreferEqual}; cudaFuncCache cacheConfigOption; int i; for(i = 0; i < NumCacheConfigs; i++) { if (strcmp(cacheConfigStr, cacheConfigOptionsStr[i]) == 0) { cacheConfigOption = cacheConfigOptions[i]; break; } } if (i >= NumCacheConfigs) { fprintf(stderr, "Invalid cache config option : '%s'\n", cacheConfigStr); return -1; } fprintf(stderr, "Set cache config option : '%s'\n", cacheConfigStr); RUNTIME_API_CALL(cudaFuncSetCacheConfig(kernel, cacheConfigOption)); return 0; } int main(int argc, char* argv[]) { int kernelOption = DEFAULT_KERNEL_OPTION; if (argc > 1) { kernelOption = atoi(argv[1]); } void (*kernel)(float*, float*, int, int); const char* kernelName; if (kernelOption == 1) { kernel = &transposeCoalesced; kernelName = "transposeCoalesced"; } else if (kernelOption == 2) { kernel = &transposeNoBankConflicts; kernelName = "transposeNoBankConflicts"; } else { fprintf(stderr, "** Invalid kernel option: %s\n", argv[1]); PRINT_PROGRAM_USAGE(); exit(EXIT_FAILURE); } int matrixSize = DEFAULT_MATRIX_SIZE; if (argc > 2) { matrixSize = atoi(argv[2]); } if ((matrixSize < TILE_DIM) || (matrixSize % TILE_DIM != 0)) { fprintf(stderr, "** Invalid matrix size: %s\n", argv[2]); PRINT_PROGRAM_USAGE(); exit(EXIT_FAILURE); } // size of memory required to store the matrix size_t memSize = sizeof(float) * matrixSize * matrixSize; // allocate host memory float* h_idata = (float*)malloc(memSize); float* h_odata = (float*)malloc(memSize); float* transposeGold = (float*)malloc(memSize); // allocate device memory float *d_idata, *d_odata; RUNTIME_API_CALL(cudaMalloc((void**)&d_idata, memSize)); RUNTIME_API_CALL(cudaMalloc((void**)&d_odata, memSize)); // initialize host data for (int i = 0; i < (matrixSize * matrixSize); ++i) { h_idata[i] = (float)i; } // copy host data to device RUNTIME_API_CALL(cudaMemcpy(d_idata, h_idata, memSize, cudaMemcpyHostToDevice)); printf("\nmatrix size: %dx%d (%dx%d tiles), kernel name: '%s', " "tile size: %dx%d, block size: %dx%d\n", matrixSize, matrixSize, matrixSize/TILE_DIM, matrixSize/TILE_DIM, kernelName, TILE_DIM, TILE_DIM, TILE_DIM, BLOCK_ROWS); if ((argc > 3) && setCacheConfig(argv[3], (const void *)kernel)) { PRINT_PROGRAM_USAGE(); exit(EXIT_FAILURE); } // execution configuration parameters dim3 grid(matrixSize / TILE_DIM, matrixSize / TILE_DIM); dim3 threads(TILE_DIM, BLOCK_ROWS); kernel<<>>(d_odata, d_idata, matrixSize, matrixSize); cudaError_t err = cudaGetLastError(); if (err != cudaSuccess) { fprintf(stderr, "Failed to launch '%s' kernel (error code %s)!\n", kernelName, cudaGetErrorString(err)); exit(EXIT_FAILURE); } RUNTIME_API_CALL(cudaMemcpy(h_odata, d_odata, memSize, cudaMemcpyDeviceToHost)); // Compute reference transpose solution computeTransposeGold(transposeGold, h_idata, matrixSize, matrixSize); bool res = compareData(transposeGold, h_odata, matrixSize * matrixSize); if (res == false) { fprintf(stderr, "** '%s' kernel FAILED\n", kernelName); exit(EXIT_FAILURE); } printf("Done\n"); return 0; } J0 . "_Z24transposeNoBankConflictsPfS_ii " launch__grid_size launch__grid_dim_x launch__grid_dim_y launch__grid_dim_z launch__block_size launch__block_dim_x launch__block_dim_y launch__block_dim_z launch__thread_count #launch__shared_mem_per_block_static $launch__shared_mem_per_block_dynamic #launch__shared_mem_per_block_driver launch__shared_mem_per_block launch__shared_mem_config_size launch__registers_per_thread launch__function_pcs launch__uses_cdp launch__device_id launch__context_id launch__func_cache_config launch__stream_id &sm__maximum_warps_per_active_cycle_pct &sm__maximum_warps_avg_per_active_cycle launch__waves_per_multiprocessor &launch__registers_per_thread_allocated &launch__shared_mem_per_block_allocated !launch__occupancy_limit_registers "launch__occupancy_limit_shared_mem launch__occupancy_limit_warps launch__occupancy_limit_blocks $launch__occupancy_per_register_count launch__occupancy_per_block_size %launch__occupancy_per_shared_mem_size device__attribute_architecture device__attribute_chip device__attribute_device_index 'device__attribute_limits_max_cta_per_sm 'device__attribute_max_gpu_frequency_khz 'device__attribute_max_mem_frequency_khz device__attribute_fb_bus_width device__attribute_fbp_count 3device__attribute_num_schedulers_per_multiprocessor ,device__attribute_num_tex_per_multiprocessor !device__attribute_num_l2s_per_fbp *device__attribute_max_registers_per_thread )device__attribute_max_warps_per_scheduler .device__attribute_max_warps_per_multiprocessor 'device__attribute_max_ipc_per_scheduler ,device__attribute_max_ipc_per_multiprocessor device__attribute_l2s_count device__attribute_implementation device__attribute_sass_level -device__attribute_confidential_computing_mode 'device__attribute_max_threads_per_block !device__attribute_max_block_dim_x !device__attribute_max_block_dim_y !device__attribute_max_block_dim_z device__attribute_max_grid_dim_x device__attribute_max_grid_dim_y device__attribute_max_grid_dim_z -device__attribute_max_shared_memory_per_block 'device__attribute_total_constant_memory device__attribute_warp_size device__attribute_max_pitch )device__attribute_max_registers_per_block device__attribute_clock_rate #device__attribute_texture_alignment device__attribute_gpu_overlap &device__attribute_multiprocessor_count %device__attribute_kernel_exec_timeout device__attribute_integrated %device__attribute_can_map_host_memory device__attribute_compute_mode )device__attribute_maximum_texture1d_width )device__attribute_maximum_texture2d_width *device__attribute_maximum_texture2d_height )device__attribute_maximum_texture3d_width *device__attribute_maximum_texture3d_height )device__attribute_maximum_texture3d_depth 1device__attribute_maximum_texture2d_layered_width 2device__attribute_maximum_texture2d_layered_height 2device__attribute_maximum_texture2d_layered_layers #device__attribute_surface_alignment $device__attribute_concurrent_kernels device__attribute_ecc_enabled device__attribute_pci_bus_id device__attribute_pci_device_id device__attribute_tcc_driver #device__attribute_memory_clock_rate )device__attribute_global_memory_bus_width device__attribute_l2_cache_size 0device__attribute_max_threads_per_multiprocessor $device__attribute_async_engine_count $device__attribute_unified_addressing 1device__attribute_maximum_texture1d_layered_width 2device__attribute_maximum_texture1d_layered_layers "device__attribute_can_tex2d_gather 0device__attribute_maximum_texture2d_gather_width 1device__attribute_maximum_texture2d_gather_height 3device__attribute_maximum_texture3d_width_alternate 4device__attribute_maximum_texture3d_height_alternate 3device__attribute_maximum_texture3d_depth_alternate device__attribute_pci_domain_id )device__attribute_texture_pitch_alignment .device__attribute_maximum_texturecubemap_width 6device__attribute_maximum_texturecubemap_layered_width 7device__attribute_maximum_texturecubemap_layered_layers )device__attribute_maximum_surface1d_width )device__attribute_maximum_surface2d_width *device__attribute_maximum_surface2d_height )device__attribute_maximum_surface3d_width *device__attribute_maximum_surface3d_height )device__attribute_maximum_surface3d_depth 1device__attribute_maximum_surface1d_layered_width 2device__attribute_maximum_surface1d_layered_layers 1device__attribute_maximum_surface2d_layered_width 2device__attribute_maximum_surface2d_layered_height 2device__attribute_maximum_surface2d_layered_layers .device__attribute_maximum_surfacecubemap_width 6device__attribute_maximum_surfacecubemap_layered_width 7device__attribute_maximum_surfacecubemap_layered_layers 0device__attribute_maximum_texture1d_linear_width 0device__attribute_maximum_texture2d_linear_width 1device__attribute_maximum_texture2d_linear_height 0device__attribute_maximum_texture2d_linear_pitch 3device__attribute_maximum_texture2d_mipmapped_width 4device__attribute_maximum_texture2d_mipmapped_height 3device__attribute_maximum_texture1d_mipmapped_width -device__attribute_stream_priorities_supported +device__attribute_global_l1_cache_supported *device__attribute_local_l1_cache_supported 6device__attribute_max_shared_memory_per_multiprocessor 2device__attribute_max_registers_per_multiprocessor device__attribute_managed_memory !device__attribute_multi_gpu_board *device__attribute_multi_gpu_board_group_id .device__attribute_host_native_atomic_supported 7device__attribute_single_to_double_precision_perf_ratio (device__attribute_pageable_memory_access +device__attribute_concurrent_managed_access .device__attribute_compute_preemption_supported 9device__attribute_can_use_host_pointer_for_registered_mem $device__attribute_cooperative_launch 1device__attribute_cooperative_multi_device_launch 3device__attribute_max_shared_memory_per_block_optin )device__attribute_can_flush_remote_writes )device__attribute_host_register_supported >device__attribute_pageable_memory_access_uses_host_page_tables 5device__attribute_direct_managed_mem_access_from_host 6device__attribute_virtual_address_management_supported =device__attribute_handle_type_posix_file_descriptor_supported 4device__attribute_handle_type_win32_handle_supported 8device__attribute_handle_type_win32_kmt_handle_supported /device__attribute_max_blocks_per_multiprocessor /device__attribute_generic_compression_supported .device__attribute_max_persisting_l2_cache_size /device__attribute_max_access_policy_window_size 9device__attribute_gpu_direct_rdma_with_cuda_vmm_supported 2device__attribute_reserved_shared_memory_per_block -device__attribute_sparse_cuda_array_supported (device__attribute_memory_pools_supported +device__attribute_gpu_direct_rdma_supported 6device__attribute_gpu_direct_rdma_flush_writes_options 1device__attribute_gpu_direct_rdma_writes_ordering 0device__attribute_mempool_supported_handle_types device__attribute_cluster_launch 7device__attribute_deferred_mapping_cuda_array_supported %device__attribute_ipc_event_supported +device__attribute_can_use_stream_mem_ops_v1 2device__attribute_can_use_64_bit_stream_mem_ops_v1 2device__attribute_can_use_stream_wait_value_nor_v1 /device__attribute_can_use_64_bit_stream_mem_ops /device__attribute_can_use_stream_wait_value_nor #device__attribute_dma_buf_supported 'device__attribute_mem_sync_domain_count -device__attribute_tensor_map_access_supported +device__attribute_unified_function_pointers device__attribute_numa_config %device__attribute_multicast_supported device__attribute_mps_enabled device__attribute_host_numa_id device__attribute_display_name *device__attribute_compute_capability_major *device__attribute_compute_capability_minor device__attribute_total_memory device__attribute_ram_type device__attribute_ram_location #device__attribute_gpu_pci_device_id 'device__attribute_gpu_pci_sub_system_id %device__attribute_gpu_pci_revision_id 'device__attribute_gpu_pci_ext_device_id !device__attribute_gpu_pci_ext_gen %device__attribute_gpu_pci_ext_gpu_gen +device__attribute_gpu_pci_ext_gpu_link_rate ,device__attribute_gpu_pci_ext_gpu_link_width 2device__attribute_gpu_pci_ext_downstream_link_rate 3device__attribute_gpu_pci_ext_downstream_link_width (smsp__maximum_warps_avg_per_active_cycle sass__inst_executed_per_opcode 6sass__inst_executed_per_opcode_with_modifier_selective 0sass__inst_executed_per_opcode_with_modifier_all *sass__thread_inst_executed_true_per_opcode Bsass__thread_inst_executed_true_per_opcode_with_modifier_selective smsp__pcsamp_warps_issue_stalled_math_pipe_throttle_not_issued 'smsp__pcsamp_warps_issue_stalled_membar 2smsp__pcsamp_warps_issue_stalled_membar_not_issued -smsp__pcsamp_warps_issue_stalled_mio_throttle 8smsp__pcsamp_warps_issue_stalled_mio_throttle_not_issued %smsp__pcsamp_warps_issue_stalled_misc 0smsp__pcsamp_warps_issue_stalled_misc_not_issued 0smsp__pcsamp_warps_issue_stalled_no_instructions ;smsp__pcsamp_warps_issue_stalled_no_instructions_not_issued -smsp__pcsamp_warps_issue_stalled_not_selected 8smsp__pcsamp_warps_issue_stalled_not_selected_not_issued )smsp__pcsamp_warps_issue_stalled_selected 4smsp__pcsamp_warps_issue_stalled_selected_not_issued 1smsp__pcsamp_warps_issue_stalled_short_scoreboard smsp__sass_inst_executed_memdesc_explicit_hitprop_evict_normal Esmsp__sass_inst_executed_memdesc_explicit_hitprop_evict_normal_demote >smsp__sass_inst_executed_memdesc_explicit_missprop_evict_first ?smsp__sass_inst_executed_memdesc_explicit_missprop_evict_normal Jbreakdown:gpu__compute_memory_throughput.avg.pct_of_peak_sustained_elapsed :breakdown:sm__throughput.avg.pct_of_peak_sustained_elapsed group:memory__chart group:memory__dram_table %group:memory__first_level_cache_table )group:memory__l2_cache_evict_policy_table group:memory__l2_cache_table group:memory__shared_table %group:smsp__pcsamp_warp_stall_reasons 0group:smsp__pcsamp_warp_stall_reasons_not_issued !profiler__perfworks_session_reuse smsp__pcsamp_dropped_bytes smsp__pcsamp_buffer_size_bytes smsp__pcsamp_interval smsp__pcsamp_interval_cycles smsp__pcsamp_aggregated_passes #profiler__pmsampler_dropped_samples "profiler__pmsampler_merged_samples %profiler__pmsampler_buffer_size_bytes !profiler__pmsampler_interval_time profiler__pmsampler_pass_groups profiler__pmsampler_ctxsw_0 profiler__pmsampler_ctxsw_1 profiler__pmsampler_ctxsw_2 profiler__pmsampler_ctxsw_3 profiler__pmsampler_ctxsw_4 profiler__pmsampler_ctxsw_5 profiler__pmsampler_ctxsw_6 profiler__replayer_passes %profiler__replayer_passes_type_warmup +profiler__replayer_bytes_mem_accessible.min +profiler__replayer_bytes_mem_accessible.max +profiler__replayer_bytes_mem_accessible.sum +profiler__replayer_bytes_mem_accessible.avg *profiler__replayer_bytes_mem_backed_up.min *profiler__replayer_bytes_mem_backed_up.max *profiler__replayer_bytes_mem_backed_up.sum *profiler__replayer_bytes_mem_backed_up.avg dram__bytes.sum.peak_sustained dram__bytes.sum.per_second dram__bytes_read.sum 2dram__bytes_read.sum.pct_of_peak_sustained_elapsed dram__bytes_read.sum.per_second dram__bytes_write.sum 3dram__bytes_write.sum.pct_of_peak_sustained_elapsed dram__bytes_write.sum.per_second 5dram__cycles_active.avg.pct_of_peak_sustained_elapsed #dram__cycles_elapsed.avg.per_second dram__sectors_read.sum dram__sectors_write.sum 4fbpa__dram_sectors.avg.pct_of_peak_sustained_elapsed "gpc__cycles_elapsed.avg.per_second gpc__cycles_elapsed.max Ggpu__compute_memory_access_throughput.avg.pct_of_peak_sustained_elapsed Hgpu__compute_memory_request_throughput.avg.pct_of_peak_sustained_elapsed @gpu__compute_memory_throughput.avg.pct_of_peak_sustained_elapsed 6gpu__dram_throughput.avg.pct_of_peak_sustained_elapsed gpu__time_duration.sum lts__t_sectors_srcunit_tex_evict_normal_demote_lookup_miss.sum 6lts__t_sectors_srcunit_tex_evict_normal_lookup_hit.sum 7lts__t_sectors_srcunit_tex_evict_normal_lookup_miss.sum )lts__t_sectors_srcunit_tex_lookup_hit.sum *lts__t_sectors_srcunit_tex_lookup_miss.sum Llts__t_sectors_srcunit_tex_op_atom_dot_alu.avg.pct_of_peak_sustained_elapsed =lts__t_sectors_srcunit_tex_op_atom_dot_alu.avg.peak_sustained @lts__t_sectors_srcunit_tex_op_atom_dot_alu.avg.per_cycle_elapsed .lts__t_sectors_srcunit_tex_op_atom_dot_alu.sum 9lts__t_sectors_srcunit_tex_op_atom_dot_alu.sum.per_second 9lts__t_sectors_srcunit_tex_op_atom_dot_alu_lookup_hit.sum :lts__t_sectors_srcunit_tex_op_atom_dot_alu_lookup_miss.sum Llts__t_sectors_srcunit_tex_op_atom_dot_cas.avg.pct_of_peak_sustained_elapsed =lts__t_sectors_srcunit_tex_op_atom_dot_cas.avg.peak_sustained @lts__t_sectors_srcunit_tex_op_atom_dot_cas.avg.per_cycle_elapsed .lts__t_sectors_srcunit_tex_op_atom_dot_cas.sum 9lts__t_sectors_srcunit_tex_op_atom_dot_cas.sum.per_second 9lts__t_sectors_srcunit_tex_op_atom_dot_cas_lookup_hit.sum :lts__t_sectors_srcunit_tex_op_atom_dot_cas_lookup_miss.sum =lts__t_sectors_srcunit_tex_op_atom_evict_first_lookup_hit.sum >lts__t_sectors_srcunit_tex_op_atom_evict_first_lookup_miss.sum lts__t_sectors_srcunit_tex_op_atom_evict_normal_lookup_hit.sum ?lts__t_sectors_srcunit_tex_op_atom_evict_normal_lookup_miss.sum Dlts__t_sectors_srcunit_tex_op_read.avg.pct_of_peak_sustained_elapsed 5lts__t_sectors_srcunit_tex_op_read.avg.peak_sustained 8lts__t_sectors_srcunit_tex_op_read.avg.per_cycle_elapsed <s__t_sectors_srcunit_tex_op_read.sum 1lts__t_sectors_srcunit_tex_op_read.sum.per_second =lts__t_sectors_srcunit_tex_op_read_evict_first_lookup_hit.sum >lts__t_sectors_srcunit_tex_op_read_evict_first_lookup_miss.sum lts__t_sectors_srcunit_tex_op_read_evict_normal_lookup_hit.sum ?lts__t_sectors_srcunit_tex_op_read_evict_normal_lookup_miss.sum 1lts__t_sectors_srcunit_tex_op_read_lookup_hit.sum 2lts__t_sectors_srcunit_tex_op_read_lookup_miss.sum Clts__t_sectors_srcunit_tex_op_red.avg.pct_of_peak_sustained_elapsed 4lts__t_sectors_srcunit_tex_op_red.avg.peak_sustained 7lts__t_sectors_srcunit_tex_op_red.avg.per_cycle_elapsed %lts__t_sectors_srcunit_tex_op_red.sum 0lts__t_sectors_srcunit_tex_op_red.sum.per_second 0lts__t_sectors_srcunit_tex_op_red_lookup_hit.sum 1lts__t_sectors_srcunit_tex_op_red_lookup_miss.sum Elts__t_sectors_srcunit_tex_op_write.avg.pct_of_peak_sustained_elapsed 6lts__t_sectors_srcunit_tex_op_write.avg.peak_sustained 9lts__t_sectors_srcunit_tex_op_write.avg.per_cycle_elapsed 'lts__t_sectors_srcunit_tex_op_write.sum 2lts__t_sectors_srcunit_tex_op_write.sum.per_second >lts__t_sectors_srcunit_tex_op_write_evict_first_lookup_hit.sum ?lts__t_sectors_srcunit_tex_op_write_evict_first_lookup_miss.sum =lts__t_sectors_srcunit_tex_op_write_evict_last_lookup_hit.sum >lts__t_sectors_srcunit_tex_op_write_evict_last_lookup_miss.sum Flts__t_sectors_srcunit_tex_op_write_evict_normal_demote_lookup_hit.sum Glts__t_sectors_srcunit_tex_op_write_evict_normal_demote_lookup_miss.sum ?lts__t_sectors_srcunit_tex_op_write_evict_normal_lookup_hit.sum @lts__t_sectors_srcunit_tex_op_write_evict_normal_lookup_miss.sum 2lts__t_sectors_srcunit_tex_op_write_lookup_hit.sum 3lts__t_sectors_srcunit_tex_op_write_lookup_miss.sum 5lts__t_tag_requests.avg.pct_of_peak_sustained_elapsed 1lts__throughput.avg.pct_of_peak_sustained_elapsed =lts__xbar2lts_cycles_active.avg.pct_of_peak_sustained_elapsed pcie__read_bytes.sum.per_second pcie__write_bytes.sum.per_second sm__cycles_active.avg !sm__cycles_elapsed.avg.per_second 3sm__inst_executed.avg.pct_of_peak_sustained_elapsed &sm__inst_executed.avg.per_cycle_active 'sm__inst_executed.avg.per_cycle_elapsed ;sm__inst_executed_pipe_adu.avg.pct_of_peak_sustained_active sm__pipe_tensor_cycles_active.avg.pct_of_peak_sustained_active ?sm__pipe_tensor_cycles_active.avg.pct_of_peak_sustained_elapsed Fsm__pipe_tensor_op_hmma_cycles_active.avg.pct_of_peak_sustained_active Fsm__pipe_tensor_op_imma_cycles_active.avg.pct_of_peak_sustained_active 1sm__sass_inst_executed_op_ldgsts_cache_access.sum 1sm__sass_inst_executed_op_ldgsts_cache_bypass.sum Nsm__sass_l1tex_data_bytes_write_pipe_lsu_mem_shared_op_ldgsts_cache_access.sum lsm__sass_l1tex_data_bytes_write_pipe_lsu_mem_shared_op_ldgsts_cache_access.sum.pct_of_peak_sustained_elapsed Ysm__sass_l1tex_data_bytes_write_pipe_lsu_mem_shared_op_ldgsts_cache_access.sum.per_second Lsm__sass_l1tex_m_xbar2l1tex_read_bytes_mem_global_op_ldgsts_cache_bypass.sum jsm__sass_l1tex_m_xbar2l1tex_read_bytes_mem_global_op_ldgsts_cache_bypass.sum.pct_of_peak_sustained_elapsed Wsm__sass_l1tex_m_xbar2l1tex_read_bytes_mem_global_op_ldgsts_cache_bypass.sum.per_second ;sm__sass_l1tex_t_requests_pipe_lsu_mem_global_op_ldgsts.sum Ysm__sass_l1tex_t_requests_pipe_lsu_mem_global_op_ldgsts.sum.pct_of_peak_sustained_elapsed Hsm__sass_l1tex_t_requests_pipe_lsu_mem_global_op_ldgsts_cache_access.sum Hsm__sass_l1tex_t_requests_pipe_lsu_mem_global_op_ldgsts_cache_bypass.sum Gsm__sass_l1tex_t_sectors_pipe_lsu_mem_global_op_ldgsts_cache_access.sum esm__sass_l1tex_t_sectors_pipe_lsu_mem_global_op_ldgsts_cache_access.sum.pct_of_peak_sustained_elapsed Gsm__sass_l1tex_t_sectors_pipe_lsu_mem_global_op_ldgsts_cache_bypass.sum esm__sass_l1tex_t_sectors_pipe_lsu_mem_global_op_ldgsts_cache_bypass.sum.pct_of_peak_sustained_elapsed @sm__sass_thread_inst_executed_op_dfma_pred_on.sum.peak_sustained @sm__sass_thread_inst_executed_op_ffma_pred_on.sum.peak_sustained 0sm__throughput.avg.pct_of_peak_sustained_elapsed 1sm__warps_active.avg.pct_of_peak_sustained_active %sm__warps_active.avg.per_cycle_active 0smsp__average_warp_latency_per_inst_issued.ratio 2smsp__average_warps_active_per_inst_executed.ratio @smsp__average_warps_issue_stalled_barrier_per_issue_active.ratio Ismsp__average_warps_issue_stalled_branch_resolving_per_issue_active.ratio Gsmsp__average_warps_issue_stalled_dispatch_stall_per_issue_active.ratio >smsp__average_warps_issue_stalled_drain_per_issue_active.ratio Asmsp__average_warps_issue_stalled_imc_miss_per_issue_active.ratio Dsmsp__average_warps_issue_stalled_lg_throttle_per_issue_active.ratio Hsmsp__average_warps_issue_stalled_long_scoreboard_per_issue_active.ratio Ksmsp__average_warps_issue_stalled_math_pipe_throttle_per_issue_active.ratio ?smsp__average_warps_issue_stalled_membar_per_issue_active.ratio Esmsp__average_warps_issue_stalled_mio_throttle_per_issue_active.ratio =smsp__average_warps_issue_stalled_misc_per_issue_active.ratio Gsmsp__average_warps_issue_stalled_no_instruction_per_issue_active.ratio Esmsp__average_warps_issue_stalled_not_selected_per_issue_active.ratio Asmsp__average_warps_issue_stalled_selected_per_issue_active.ratio Ismsp__average_warps_issue_stalled_short_scoreboard_per_issue_active.ratio Asmsp__average_warps_issue_stalled_sleeping_per_issue_active.ratio Esmsp__average_warps_issue_stalled_tex_throttle_per_issue_active.ratio =smsp__average_warps_issue_stalled_wait_per_issue_active.ratio #smsp__cycles_elapsed.avg.per_second smsp__cycles_elapsed.sum smsp__inst_executed.avg smsp__inst_executed.sum !smsp__inst_executed_op_branch.sum /smsp__inst_executed_op_generic_atom_dot_alu.sum Msmsp__inst_executed_op_generic_atom_dot_alu.sum.pct_of_peak_sustained_elapsed /smsp__inst_executed_op_generic_atom_dot_cas.sum Msmsp__inst_executed_op_generic_atom_dot_cas.sum.pct_of_peak_sustained_elapsed %smsp__inst_executed_op_global_red.sum Csmsp__inst_executed_op_global_red.sum.pct_of_peak_sustained_elapsed !smsp__inst_executed_op_ldgsts.sum ?smsp__inst_executed_op_ldgsts.sum.pct_of_peak_sustained_elapsed smsp__inst_executed_op_ldsm.sum =smsp__inst_executed_op_ldsm.sum.pct_of_peak_sustained_elapsed &smsp__inst_executed_op_shared_atom.sum Dsmsp__inst_executed_op_shared_atom.sum.pct_of_peak_sustained_elapsed /smsp__inst_executed_op_surface_atom_dot_alu.sum Msmsp__inst_executed_op_surface_atom_dot_alu.sum.pct_of_peak_sustained_elapsed /smsp__inst_executed_op_surface_atom_dot_cas.sum Msmsp__inst_executed_op_surface_atom_dot_cas.sum.pct_of_peak_sustained_elapsed %smsp__inst_executed_op_surface_ld.sum Csmsp__inst_executed_op_surface_ld.sum.pct_of_peak_sustained_elapsed &smsp__inst_executed_op_surface_red.sum Dsmsp__inst_executed_op_surface_red.sum.pct_of_peak_sustained_elapsed %smsp__inst_executed_op_surface_st.sum Csmsp__inst_executed_op_surface_st.sum.pct_of_peak_sustained_elapsed "smsp__inst_executed_op_texture.sum @smsp__inst_executed_op_texture.sum.pct_of_peak_sustained_elapsed smsp__inst_issued.avg smsp__inst_issued.sum 3smsp__issue_active.avg.pct_of_peak_sustained_active 'smsp__issue_active.avg.per_cycle_active 2smsp__issue_inst0.avg.pct_of_peak_sustained_active 5smsp__sass_average_branch_targets_threads_uniform.pct /smsp__sass_branch_targets_threads_divergent.avg )smsp__sass_inst_executed_op_global_ld.sum )smsp__sass_inst_executed_op_global_st.sum (smsp__sass_inst_executed_op_local_ld.sum (smsp__sass_inst_executed_op_local_st.sum +smsp__sass_inst_executed_op_memory_128b.sum *smsp__sass_inst_executed_op_memory_16b.sum *smsp__sass_inst_executed_op_memory_32b.sum *smsp__sass_inst_executed_op_memory_64b.sum )smsp__sass_inst_executed_op_memory_8b.sum )smsp__sass_inst_executed_op_shared_ld.sum )smsp__sass_inst_executed_op_shared_st.sum Fsmsp__sass_l1tex_data_bank_conflicts_pipe_lsu_mem_shared_op_ldgsts.sum Bsmsp__sass_l1tex_data_bank_conflicts_pipe_lsu_mem_shared_op_st.sum Bsmsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_ldgsts.sum `smsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_ldgsts.sum.pct_of_peak_sustained_elapsed Osmsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_ldgsts_cache_access.sum msmsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_ldgsts_cache_access.sum.pct_of_peak_sustained_elapsed >smsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_st.sum \smsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_st.sum.pct_of_peak_sustained_elapsed Psmsp__sass_l1tex_m_xbar2l1tex_read_sectors_mem_global_op_ldgsts_cache_bypass.sum nsmsp__sass_l1tex_m_xbar2l1tex_read_sectors_mem_global_op_ldgsts_cache_bypass.sum.pct_of_peak_sustained_elapsed Esmsp__sass_thread_inst_executed_op_dadd_pred_on.sum.per_cycle_elapsed Esmsp__sass_thread_inst_executed_op_dfma_pred_on.sum.per_cycle_elapsed Esmsp__sass_thread_inst_executed_op_dmul_pred_on.sum.per_cycle_elapsed Esmsp__sass_thread_inst_executed_op_fadd_pred_on.sum.per_cycle_elapsed Esmsp__sass_thread_inst_executed_op_ffma_pred_on.sum.per_cycle_elapsed Esmsp__sass_thread_inst_executed_op_fmul_pred_on.sum.per_cycle_elapsed 2smsp__thread_inst_executed_per_inst_executed.ratio :smsp__thread_inst_executed_pred_on_per_inst_executed.ratio %smsp__warps_active.avg.peak_sustained 'smsp__warps_active.avg.per_cycle_active )smsp__warps_eligible.avg.per_cycle_active sass__inst_executed_global_loads !sass__inst_executed_global_stores sass__inst_executed_local_loads sass__inst_executed_local_stores sass__inst_executed_shared_loads !sass__inst_executed_shared_stores GFBSP.TriageSCG.dramc__read_throughput.avg.pct_of_peak_sustained_elapsed BFBSP.TriageSCG.dramc__throughput.avg.pct_of_peak_sustained_elapsed HFBSP.TriageSCG.dramc__write_throughput.avg.pct_of_peak_sustained_elapsed .FE_B.TriageAC.gr__ctas_launched_queue_sync.sum 8TriageAC.tpc__warps_active_realtime.avg.per_cycle_active 8TriageAC.tpc__warps_active_realtime.sum.per_cycle_active 9LTS.TriageSCG.lts__average_t_sector_hit_rate_realtime.pct ?LTS.TriageSCG.lts__throughput.avg.pct_of_peak_sustained_elapsed 1SM_A.TriageAC.l1tex__data_pipe_lsu_wavefronts.avg -SM_A.TriageAC.l1tex__lsu_writeback_active.avg BSM_A.TriageSCG.l1tex__throughput.avg.pct_of_peak_sustained_elapsed #SM_A.TriageAC.sm__cycles_active.avg =SM_A.TriageAC.sm__inst_executed_realtime.avg.per_cycle_active TSM_A.TriageSCG.sm__inst_executed_pipe_alu_realtime.avg.pct_of_peak_sustained_elapsed RSM_C.TriageSCG.smsp__inst_executed_pipe_fmaheavy.avg.pct_of_peak_sustained_elapsed QSM_C.TriageSCG.smsp__inst_executed_pipe_fmalite.avg.pct_of_peak_sustained_elapsed :TriageSCG.sm__throughput.avg.pct_of_peak_sustained_elapsed Spmsampling:sm__pipe_tensor_cycles_active_realtime.avg.pct_of_peak_sustained_elapsed *SM_B.TriageAC.l1tex__t_sector_hit_rate.pct derived__avg_thread_executed !derived__avg_thread_executed_true (derived__memory_l1_conflicts_shared_nway .derived__memory_l1_wavefronts_shared_excessive 7derived__memory_l2_theoretical_sectors_global_excessive 9derived__sm__sass_thread_inst_executed_op_dfma_pred_on_x2 9derived__sm__sass_thread_inst_executed_op_ffma_pred_on_x2 *derived__smsp__inst_executed_op_branch_pct ;derived__smsp__sass_thread_inst_executed_op_dfma_pred_on_x2 ;derived__smsp__sass_thread_inst_executed_op_ffma_pred_on_x2(2k 127.0.0.1Y/usr/local/nsight-compute-2023.3.1/extras/samples/sharedBankConflicts/sharedBankConflicts?• Õ*"_Z24transposeNoBankConflictsPfS_ii2transposeNoBankConflicts:4transposeNoBankConflicts(float *, float *, int, int)@JRZ j @ j p@ j p@ j ? j p@ j @@ j  @ j ? j pA j  @ j   j  @ j  @ j  @ j 8@ j t(B (( j  j  j ? j CachePreferNone j @ j Y@ j H@ j aah@ j @ j @ j $@ j (@ j @ j 0@ j p@ ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ( (0 ( (0 ( (0 ( (0 ( (0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ((0 ( (0 (!(0 ("(0 (#(0 ($(0 (%(0 (&(0 ('(0 (((0 ()(( (*(( (+(( (,(( (-(( (.(( (/(( (0(( (1(  (2(  (3(  (4(  (5(  (6(  (7(  (8(  (9(  (:(  (;(  (<(  (=(  (>(  (?(  (@(  (A( (B( (C( (D( (E( (F( (G( (H( (I( (J( (K( (L( (M( (N( (O( (P( (Q( (R( (S( (T( (U( (V( (W( (X( (Y( (Z( ([( (\( (]( (^( (_( (`( (a( (b( (c( (d( (e( (f( (g( (h( (i( (j( (k( (l( (m( (n( (o( (p( (q( (r( (s( (t( (u( (v( (w( (x( (y( (z( ({( (|( (}( (~( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( (( 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dram__cycles_active.avg.pct_of_peak_sustained_elapsed,fbpa__dram_sectors.avg.pct_of_peak_sustained_elapsed,l1tex__data_bank_reads.avg.pct_of_peak_sustained_elapsed,l1tex__data_bank_writes.avg.pct_of_peak_sustained_elapsed,l1tex__data_pipe_lsu_wavefronts.avg.pct_of_peak_sustained_elapsed,l1tex__data_pipe_tex_wavefronts.avg.pct_of_peak_sustained_elapsed,l1tex__f_wavefronts.avg.pct_of_peak_sustained_elapsed,l1tex__lsu_writeback_active.avg.pct_of_peak_sustained_elapsed,l1tex__lsuin_requests.avg.pct_of_peak_sustained_elapsed,l1tex__m_l1tex2xbar_req_cycles_active.avg.pct_of_peak_sustained_elapsed,l1tex__m_xbar2l1tex_read_sectors.avg.pct_of_peak_sustained_elapsed,l1tex__tex_writeback_active.avg.pct_of_peak_sustained_elapsed,l1tex__texin_sm2tex_req_cycles_active.avg.pct_of_peak_sustained_elapsed,lts__d_atomic_input_cycles_active.avg.pct_of_peak_sustained_elapsed,lts__d_sectors.avg.pct_of_peak_sustained_elapsed,lts__d_sectors_fill_device.avg.pct_of_peak_sustained_elapsed,lts__d_sectors_fill_sysmem.avg.pct_of_peak_sustained_elapsed,lts__lts2xbar_cycles_active.avg.pct_of_peak_sustained_elapsed,lts__t_sectors.avg.pct_of_peak_sustained_elapsed,lts__t_tag_requests.avg.pct_of_peak_sustained_elapsed,lts__xbar2lts_cycles_active.avg.pct_of_peak_sustained_elapsed j  idc__request_cycles_active.avg.pct_of_peak_sustained_elapsed,sm__inst_executed.avg.pct_of_peak_sustained_elapsed,sm__inst_executed_pipe_adu.avg.pct_of_peak_sustained_elapsed,sm__inst_executed_pipe_cbu_pred_on_any.avg.pct_of_peak_sustained_elapsed,sm__inst_executed_pipe_ipa.avg.pct_of_peak_sustained_elapsed,sm__inst_executed_pipe_lsu.avg.pct_of_peak_sustained_elapsed,sm__inst_executed_pipe_tex.avg.pct_of_peak_sustained_elapsed,sm__inst_executed_pipe_uniform.avg.pct_of_peak_sustained_elapsed,sm__inst_executed_pipe_xu.avg.pct_of_peak_sustained_elapsed,sm__issue_active.avg.pct_of_peak_sustained_elapsed,sm__mio2rf_writeback_active.avg.pct_of_peak_sustained_elapsed,sm__mio_inst_issued.avg.pct_of_peak_sustained_elapsed,sm__mio_pq_read_cycles_active.avg.pct_of_peak_sustained_elapsed,sm__mio_pq_write_cycles_active.avg.pct_of_peak_sustained_elapsed,sm__pipe_alu_cycles_active.avg.pct_of_peak_sustained_elapsed,sm__pipe_fma_cycles_active.avg.pct_of_peak_sustained_elapsed,sm__pipe_fmaheavy_cycles_active.avg.pct_of_peak_sustained_elapsed,sm__pipe_fp64_cycles_active.avg.pct_of_peak_sustained_elapsed,sm__pipe_tensor_cycles_active.avg.pct_of_peak_sustained_elapsed j22 2dram__bytes_read.sum,dram__bytes_read.sum.pct_of_peak_sustained_elapsed,dram__bytes_read.sum.per_second,dram__bytes_write.sum,dram__bytes_write.sum.pct_of_peak_sustained_elapsed,dram__bytes_write.sum.per_second,l1tex__data_pipe_lsu_wavefronts_mem_shared.sum.pct_of_peak_sustained_elapsed,l1tex__m_l1tex2xbar_write_bytes.sum,l1tex__m_l1tex2xbar_write_bytes.sum.pct_of_peak_sustained_elapsed,l1tex__m_l1tex2xbar_write_bytes.sum.per_second,l1tex__m_xbar2l1tex_read_bytes.sum,l1tex__m_xbar2l1tex_read_bytes.sum.pct_of_peak_sustained_elapsed,l1tex__m_xbar2l1tex_read_bytes.sum.per_second,l1tex__t_requests_pipe_lsu_mem_global_op_atom.sum,l1tex__t_requests_pipe_lsu_mem_global_op_atom.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_lsu_mem_global_op_ld.sum,l1tex__t_requests_pipe_lsu_mem_global_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_lsu_mem_global_op_red.sum,l1tex__t_requests_pipe_lsu_mem_global_op_red.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_lsu_mem_global_op_st.sum,l1tex__t_requests_pipe_lsu_mem_global_op_st.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_lsu_mem_local_op_ld.sum,l1tex__t_requests_pipe_lsu_mem_local_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_lsu_mem_local_op_st.sum,l1tex__t_requests_pipe_lsu_mem_local_op_st.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_tex_mem_surface_op_atom.sum,l1tex__t_requests_pipe_tex_mem_surface_op_atom.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_tex_mem_surface_op_ld.sum,l1tex__t_requests_pipe_tex_mem_surface_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_tex_mem_surface_op_red.sum,l1tex__t_requests_pipe_tex_mem_surface_op_red.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_tex_mem_surface_op_st.sum,l1tex__t_requests_pipe_tex_mem_surface_op_st.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_tex_mem_texture.sum,l1tex__t_requests_pipe_tex_mem_texture.sum.pct_of_peak_sustained_elapsed,l1tex__t_sector_hit_rate.pct,lts__average_gcomp_output_sector_compression_achieved_rate.ratio,lts__gcomp_input_sectors.sum,lts__gcomp_input_sectors.sum.pct_of_peak_sustained_elapsed,lts__gcomp_input_sectors.sum.per_second,lts__gcomp_output_sectors.sum,lts__gcomp_output_sectors.sum.pct_of_peak_sustained_elapsed,lts__gcomp_output_sectors.sum.per_second,lts__t_sector_hit_rate.pct,lts__t_sectors_srcunit_tex_aperture_peer_op_read_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_peer_op_read_lookup_miss.sum.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_aperture_peer_op_read_lookup_miss.sum.per_second,lts__t_sectors_srcunit_tex_aperture_peer_op_red_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_peer_op_red_lookup_miss.sum.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_aperture_peer_op_red_lookup_miss.sum.per_second,lts__t_sectors_srcunit_tex_aperture_peer_op_write_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_peer_op_write_lookup_miss.sum.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_aperture_peer_op_write_lookup_miss.sum.per_second,lts__t_sectors_srcunit_tex_aperture_sysmem_op_read_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_sysmem_op_read_lookup_miss.sum.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_aperture_sysmem_op_read_lookup_miss.sum.per_second,lts__t_sectors_srcunit_tex_aperture_sysmem_op_red_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_sysmem_op_red_lookup_miss.sum.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_aperture_sysmem_op_red_lookup_miss.sum.per_second,lts__t_sectors_srcunit_tex_aperture_sysmem_op_write_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_sysmem_op_write_lookup_miss.sum.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_aperture_sysmem_op_write_lookup_miss.sum.per_second,lts__t_sectors_srcunit_tex_op_read.avg.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_op_read.sum,lts__t_sectors_srcunit_tex_op_write.avg.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_op_write.sum,sm__sass_l1tex_data_bytes_write_pipe_lsu_mem_shared_op_ldgsts_cache_access.sum,sm__sass_l1tex_data_bytes_write_pipe_lsu_mem_shared_op_ldgsts_cache_access.sum.pct_of_peak_sustained_elapsed,sm__sass_l1tex_data_bytes_write_pipe_lsu_mem_shared_op_ldgsts_cache_access.sum.per_second,sm__sass_l1tex_m_xbar2l1tex_read_bytes_mem_global_op_ldgsts_cache_bypass.sum,sm__sass_l1tex_m_xbar2l1tex_read_bytes_mem_global_op_ldgsts_cache_bypass.sum.pct_of_peak_sustained_elapsed,sm__sass_l1tex_m_xbar2l1tex_read_bytes_mem_global_op_ldgsts_cache_bypass.sum.per_second,sm__sass_l1tex_t_requests_pipe_lsu_mem_global_op_ldgsts.sum,sm__sass_l1tex_t_requests_pipe_lsu_mem_global_op_ldgsts.sum.pct_of_peak_sustained_elapsed,smsp__cycles_elapsed.sum,smsp__inst_executed_op_generic_atom_dot_alu.sum,smsp__inst_executed_op_generic_atom_dot_alu.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_generic_atom_dot_cas.sum,smsp__inst_executed_op_generic_atom_dot_cas.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_global_red.sum,smsp__inst_executed_op_global_red.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_ldgsts.sum,smsp__inst_executed_op_ldgsts.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_ldsm.sum,smsp__inst_executed_op_ldsm.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_shared_atom.sum,smsp__inst_executed_op_shared_atom.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_surface_atom_dot_alu.sum,smsp__inst_executed_op_surface_atom_dot_alu.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_surface_atom_dot_cas.sum,smsp__inst_executed_op_surface_atom_dot_cas.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_surface_ld.sum,smsp__inst_executed_op_surface_ld.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_surface_red.sum,smsp__inst_executed_op_surface_red.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_surface_st.sum,smsp__inst_executed_op_surface_st.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_texture.sum,smsp__inst_executed_op_texture.sum.pct_of_peak_sustained_elapsed,smsp__sass_inst_executed_op_global_ld.sum,smsp__sass_inst_executed_op_global_st.sum,smsp__sass_inst_executed_op_local_ld.sum,smsp__sass_inst_executed_op_local_st.sum,smsp__sass_inst_executed_op_shared_ld.sum,smsp__sass_inst_executed_op_shared_st.sum,smsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_ldgsts.sum,smsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_ldgsts.sum.pct_of_peak_sustained_elapsed j dram__bytes_read.sum,dram__bytes_read.sum.pct_of_peak_sustained_elapsed,dram__bytes_read.sum.per_second,dram__bytes_write.sum,dram__bytes_write.sum.pct_of_peak_sustained_elapsed,dram__bytes_write.sum.per_second,dram__sectors_read.sum,dram__sectors_write.sum jCC Cl1tex__lsu_writeback_active_mem_lg.sum,l1tex__lsu_writeback_active_mem_lg.sum.pct_of_peak_sustained_elapsed,l1tex__m_l1tex2xbar_write_sectors_mem_global_op_atom.sum,l1tex__m_l1tex2xbar_write_sectors_mem_global_op_atom.sum.pct_of_peak_sustained_elapsed,l1tex__m_l1tex2xbar_write_sectors_mem_global_op_red.sum,l1tex__m_l1tex2xbar_write_sectors_mem_global_op_red.sum.pct_of_peak_sustained_elapsed,l1tex__m_l1tex2xbar_write_sectors_mem_lg_op_st.sum,l1tex__m_l1tex2xbar_write_sectors_mem_lg_op_st.sum.pct_of_peak_sustained_elapsed,l1tex__m_l1tex2xbar_write_sectors_mem_surface_op_atom.sum,l1tex__m_l1tex2xbar_write_sectors_mem_surface_op_atom.sum.pct_of_peak_sustained_elapsed,l1tex__m_l1tex2xbar_write_sectors_mem_surface_op_red.sum,l1tex__m_l1tex2xbar_write_sectors_mem_surface_op_red.sum.pct_of_peak_sustained_elapsed,l1tex__m_l1tex2xbar_write_sectors_mem_surface_op_st.sum,l1tex__m_l1tex2xbar_write_sectors_mem_surface_op_st.sum.pct_of_peak_sustained_elapsed,l1tex__m_xbar2l1tex_read_sectors_mem_global_op_atom.sum,l1tex__m_xbar2l1tex_read_sectors_mem_global_op_atom.sum.pct_of_peak_sustained_elapsed,l1tex__m_xbar2l1tex_read_sectors_mem_lg_op_ld.sum,l1tex__m_xbar2l1tex_read_sectors_mem_lg_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__m_xbar2l1tex_read_sectors_mem_surface_op_atom.sum,l1tex__m_xbar2l1tex_read_sectors_mem_surface_op_atom.sum.pct_of_peak_sustained_elapsed,l1tex__m_xbar2l1tex_read_sectors_mem_surface_op_ld.sum,l1tex__m_xbar2l1tex_read_sectors_mem_surface_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__m_xbar2l1tex_read_sectors_mem_texture.sum,l1tex__m_xbar2l1tex_read_sectors_mem_texture.sum.pct_of_peak_sustained_elapsed,l1tex__t_output_wavefronts_pipe_lsu_mem_global_op_atom.sum,l1tex__t_output_wavefronts_pipe_lsu_mem_global_op_atom.sum.pct_of_peak_sustained_elapsed,l1tex__t_output_wavefronts_pipe_lsu_mem_global_op_ld.sum,l1tex__t_output_wavefronts_pipe_lsu_mem_global_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__t_output_wavefronts_pipe_lsu_mem_global_op_red.sum,l1tex__t_output_wavefronts_pipe_lsu_mem_global_op_red.sum.pct_of_peak_sustained_elapsed,l1tex__t_output_wavefronts_pipe_lsu_mem_global_op_st.sum,l1tex__t_output_wavefronts_pipe_lsu_mem_global_op_st.sum.pct_of_peak_sustained_elapsed,l1tex__t_output_wavefronts_pipe_lsu_mem_local_op_ld.sum,l1tex__t_output_wavefronts_pipe_lsu_mem_local_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__t_output_wavefronts_pipe_lsu_mem_local_op_st.sum,l1tex__t_output_wavefronts_pipe_lsu_mem_local_op_st.sum.pct_of_peak_sustained_elapsed,l1tex__t_output_wavefronts_pipe_tex_mem_surface_op_atom.sum,l1tex__t_output_wavefronts_pipe_tex_mem_surface_op_atom.sum.pct_of_peak_sustained_elapsed,l1tex__t_output_wavefronts_pipe_tex_mem_surface_op_ld.sum,l1tex__t_output_wavefronts_pipe_tex_mem_surface_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__t_output_wavefronts_pipe_tex_mem_surface_op_red.sum,l1tex__t_output_wavefronts_pipe_tex_mem_surface_op_red.sum.pct_of_peak_sustained_elapsed,l1tex__t_output_wavefronts_pipe_tex_mem_surface_op_st.sum,l1tex__t_output_wavefronts_pipe_tex_mem_surface_op_st.sum.pct_of_peak_sustained_elapsed,l1tex__t_output_wavefronts_pipe_tex_mem_texture.sum,l1tex__t_output_wavefronts_pipe_tex_mem_texture.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_lsu_mem_global_op_atom.sum,l1tex__t_requests_pipe_lsu_mem_global_op_atom.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_lsu_mem_global_op_ld.sum,l1tex__t_requests_pipe_lsu_mem_global_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_lsu_mem_global_op_red.sum,l1tex__t_requests_pipe_lsu_mem_global_op_red.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_lsu_mem_global_op_st.sum,l1tex__t_requests_pipe_lsu_mem_global_op_st.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_lsu_mem_local_op_ld.sum,l1tex__t_requests_pipe_lsu_mem_local_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_lsu_mem_local_op_st.sum,l1tex__t_requests_pipe_lsu_mem_local_op_st.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_tex_mem_surface_op_atom.sum,l1tex__t_requests_pipe_tex_mem_surface_op_atom.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_tex_mem_surface_op_ld.sum,l1tex__t_requests_pipe_tex_mem_surface_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_tex_mem_surface_op_red.sum,l1tex__t_requests_pipe_tex_mem_surface_op_red.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_tex_mem_surface_op_st.sum,l1tex__t_requests_pipe_tex_mem_surface_op_st.sum.pct_of_peak_sustained_elapsed,l1tex__t_requests_pipe_tex_mem_texture.sum,l1tex__t_requests_pipe_tex_mem_texture.sum.pct_of_peak_sustained_elapsed,l1tex__t_sector_pipe_lsu_mem_global_op_atom_hit_rate.pct,l1tex__t_sector_pipe_lsu_mem_global_op_ld_hit_rate.pct,l1tex__t_sector_pipe_lsu_mem_global_op_red_hit_rate.pct,l1tex__t_sector_pipe_lsu_mem_global_op_st_hit_rate.pct,l1tex__t_sector_pipe_lsu_mem_local_op_ld_hit_rate.pct,l1tex__t_sector_pipe_lsu_mem_local_op_st_hit_rate.pct,l1tex__t_sector_pipe_tex_mem_surface_op_atom_hit_rate.pct,l1tex__t_sector_pipe_tex_mem_surface_op_ld_hit_rate.pct,l1tex__t_sector_pipe_tex_mem_surface_op_red_hit_rate.pct,l1tex__t_sector_pipe_tex_mem_surface_op_st_hit_rate.pct,l1tex__t_sector_pipe_tex_mem_texture_op_tex_hit_rate.pct,l1tex__t_sectors_pipe_lsu_mem_global_op_atom.sum,l1tex__t_sectors_pipe_lsu_mem_global_op_atom_lookup_hit.sum,l1tex__t_sectors_pipe_lsu_mem_global_op_atom_lookup_miss.sum,l1tex__t_sectors_pipe_lsu_mem_global_op_ld.sum,l1tex__t_sectors_pipe_lsu_mem_global_op_ld_lookup_hit.sum,l1tex__t_sectors_pipe_lsu_mem_global_op_ld_lookup_miss.sum,l1tex__t_sectors_pipe_lsu_mem_global_op_red.sum,l1tex__t_sectors_pipe_lsu_mem_global_op_red_lookup_hit.sum,l1tex__t_sectors_pipe_lsu_mem_global_op_red_lookup_miss.sum,l1tex__t_sectors_pipe_lsu_mem_global_op_st.sum,l1tex__t_sectors_pipe_lsu_mem_global_op_st_lookup_hit.sum,l1tex__t_sectors_pipe_lsu_mem_global_op_st_lookup_miss.sum,l1tex__t_sectors_pipe_lsu_mem_local_op_ld.sum,l1tex__t_sectors_pipe_lsu_mem_local_op_ld_lookup_hit.sum,l1tex__t_sectors_pipe_lsu_mem_local_op_ld_lookup_miss.sum,l1tex__t_sectors_pipe_lsu_mem_local_op_st.sum,l1tex__t_sectors_pipe_lsu_mem_local_op_st_lookup_hit.sum,l1tex__t_sectors_pipe_lsu_mem_local_op_st_lookup_miss.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_atom.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_atom_lookup_hit.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_atom_lookup_miss.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_ld.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_ld_lookup_hit.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_ld_lookup_miss.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_red.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_red_lookup_hit.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_red_lookup_miss.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_st.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_st_lookup_hit.sum,l1tex__t_sectors_pipe_tex_mem_surface_op_st_lookup_miss.sum,l1tex__t_sectors_pipe_tex_mem_texture.sum,l1tex__t_sectors_pipe_tex_mem_texture_lookup_hit.sum,l1tex__t_sectors_pipe_tex_mem_texture_lookup_miss.sum,l1tex__tex_writeback_active.sum,l1tex__tex_writeback_active.sum.pct_of_peak_sustained_elapsed,sm__sass_inst_executed_op_ldgsts_cache_access.sum,sm__sass_inst_executed_op_ldgsts_cache_bypass.sum,sm__sass_l1tex_t_requests_pipe_lsu_mem_global_op_ldgsts_cache_access.sum,sm__sass_l1tex_t_requests_pipe_lsu_mem_global_op_ldgsts_cache_bypass.sum,sm__sass_l1tex_t_sectors_pipe_lsu_mem_global_op_ldgsts_cache_access.sum,sm__sass_l1tex_t_sectors_pipe_lsu_mem_global_op_ldgsts_cache_access.sum.pct_of_peak_sustained_elapsed,sm__sass_l1tex_t_sectors_pipe_lsu_mem_global_op_ldgsts_cache_bypass.sum,sm__sass_l1tex_t_sectors_pipe_lsu_mem_global_op_ldgsts_cache_bypass.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_generic_atom_dot_alu.sum,smsp__inst_executed_op_generic_atom_dot_cas.sum,smsp__inst_executed_op_global_red.sum,smsp__inst_executed_op_surface_atom_dot_alu.sum,smsp__inst_executed_op_surface_atom_dot_cas.sum,smsp__inst_executed_op_surface_ld.sum,smsp__inst_executed_op_surface_red.sum,smsp__inst_executed_op_surface_st.sum,smsp__inst_executed_op_texture.sum,smsp__sass_inst_executed_op_global_ld.sum,smsp__sass_inst_executed_op_global_st.sum,smsp__sass_inst_executed_op_local_ld.sum,smsp__sass_inst_executed_op_local_st.sum,smsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_ldgsts_cache_access.sum,smsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_ldgsts_cache_access.sum.pct_of_peak_sustained_elapsed,smsp__sass_l1tex_m_xbar2l1tex_read_sectors_mem_global_op_ldgsts_cache_bypass.sum,smsp__sass_l1tex_m_xbar2l1tex_read_sectors_mem_global_op_ldgsts_cache_bypass.sum.pct_of_peak_sustained_elapsed j lts__t_sectors_evict_first_lookup_hit.sum,lts__t_sectors_evict_first_lookup_miss.sum,lts__t_sectors_evict_last_lookup_hit.sum,lts__t_sectors_evict_last_lookup_miss.sum,lts__t_sectors_evict_normal_demote_lookup_hit.sum,lts__t_sectors_evict_normal_demote_lookup_miss.sum,lts__t_sectors_evict_normal_lookup_hit.sum,lts__t_sectors_evict_normal_lookup_miss.sum,lts__t_sectors_srcunit_tex_evict_first_lookup_hit.sum,lts__t_sectors_srcunit_tex_evict_first_lookup_miss.sum,lts__t_sectors_srcunit_tex_evict_last_lookup_hit.sum,lts__t_sectors_srcunit_tex_evict_last_lookup_miss.sum,lts__t_sectors_srcunit_tex_evict_normal_demote_lookup_hit.sum,lts__t_sectors_srcunit_tex_evict_normal_demote_lookup_miss.sum,lts__t_sectors_srcunit_tex_evict_normal_lookup_hit.sum,lts__t_sectors_srcunit_tex_evict_normal_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_atom_evict_first_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_atom_evict_first_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_atom_evict_last_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_atom_evict_last_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_atom_evict_normal_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_atom_evict_normal_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_read_evict_first_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_read_evict_first_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_read_evict_last_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_read_evict_last_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_read_evict_normal_demote_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_read_evict_normal_demote_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_read_evict_normal_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_read_evict_normal_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_write_evict_first_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_write_evict_first_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_write_evict_last_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_write_evict_last_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_write_evict_normal_demote_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_write_evict_normal_demote_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_write_evict_normal_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_write_evict_normal_lookup_miss.sum j"! !lts__t_requests.sum,lts__t_requests_srcunit_tex.sum,lts__t_requests_srcunit_tex_op_atom_dot_alu.sum,lts__t_requests_srcunit_tex_op_atom_dot_cas.sum,lts__t_requests_srcunit_tex_op_read.sum,lts__t_requests_srcunit_tex_op_red.sum,lts__t_requests_srcunit_tex_op_write.sum,lts__t_sectors.avg.pct_of_peak_sustained_elapsed,lts__t_sectors.avg.peak_sustained,lts__t_sectors.avg.per_cycle_elapsed,lts__t_sectors.sum,lts__t_sectors.sum.per_second,lts__t_sectors_aperture_device_lookup_miss.sum,lts__t_sectors_aperture_peer_lookup_miss.sum,lts__t_sectors_aperture_sysmem_lookup_miss.sum,lts__t_sectors_data_ecc.avg.pct_of_peak_sustained_elapsed,lts__t_sectors_data_ecc.avg.peak_sustained,lts__t_sectors_data_ecc.avg.per_cycle_elapsed,lts__t_sectors_data_ecc.sum,lts__t_sectors_data_ecc.sum.per_second,lts__t_sectors_lookup_hit.sum,lts__t_sectors_lookup_miss.sum,lts__t_sectors_srcunit_tex.avg.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex.avg.peak_sustained,lts__t_sectors_srcunit_tex.avg.per_cycle_elapsed,lts__t_sectors_srcunit_tex.sum,lts__t_sectors_srcunit_tex.sum.per_second,lts__t_sectors_srcunit_tex_aperture_device_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_device_op_atom_dot_alu_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_device_op_atom_dot_cas_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_device_op_read_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_device_op_red_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_device_op_write_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_peer_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_peer_op_atom_dot_alu_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_peer_op_atom_dot_cas_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_peer_op_read_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_peer_op_red_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_peer_op_write_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_sysmem_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_sysmem_op_atom_dot_alu_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_sysmem_op_atom_dot_cas_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_sysmem_op_read_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_sysmem_op_red_lookup_miss.sum,lts__t_sectors_srcunit_tex_aperture_sysmem_op_write_lookup_miss.sum,lts__t_sectors_srcunit_tex_lookup_hit.sum,lts__t_sectors_srcunit_tex_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_atom_dot_alu.avg.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_op_atom_dot_alu.avg.peak_sustained,lts__t_sectors_srcunit_tex_op_atom_dot_alu.avg.per_cycle_elapsed,lts__t_sectors_srcunit_tex_op_atom_dot_alu.sum,lts__t_sectors_srcunit_tex_op_atom_dot_alu.sum.per_second,lts__t_sectors_srcunit_tex_op_atom_dot_alu_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_atom_dot_alu_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_atom_dot_cas.avg.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_op_atom_dot_cas.avg.peak_sustained,lts__t_sectors_srcunit_tex_op_atom_dot_cas.avg.per_cycle_elapsed,lts__t_sectors_srcunit_tex_op_atom_dot_cas.sum,lts__t_sectors_srcunit_tex_op_atom_dot_cas.sum.per_second,lts__t_sectors_srcunit_tex_op_atom_dot_cas_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_atom_dot_cas_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_read.avg.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_op_read.avg.peak_sustained,lts__t_sectors_srcunit_tex_op_read.avg.per_cycle_elapsed,lts__t_sectors_srcunit_tex_op_read.sum,lts__t_sectors_srcunit_tex_op_read.sum.per_second,lts__t_sectors_srcunit_tex_op_read_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_read_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_red.avg.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_op_red.avg.peak_sustained,lts__t_sectors_srcunit_tex_op_red.avg.per_cycle_elapsed,lts__t_sectors_srcunit_tex_op_red.sum,lts__t_sectors_srcunit_tex_op_red.sum.per_second,lts__t_sectors_srcunit_tex_op_red_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_red_lookup_miss.sum,lts__t_sectors_srcunit_tex_op_write.avg.pct_of_peak_sustained_elapsed,lts__t_sectors_srcunit_tex_op_write.avg.peak_sustained,lts__t_sectors_srcunit_tex_op_write.avg.per_cycle_elapsed,lts__t_sectors_srcunit_tex_op_write.sum,lts__t_sectors_srcunit_tex_op_write.sum.per_second,lts__t_sectors_srcunit_tex_op_write_lookup_hit.sum,lts__t_sectors_srcunit_tex_op_write_lookup_miss.sum j  l1tex__data_bank_conflicts_pipe_lsu_mem_shared.sum,l1tex__data_bank_conflicts_pipe_lsu_mem_shared_op_atom.sum,l1tex__data_bank_conflicts_pipe_lsu_mem_shared_op_ld.sum,l1tex__data_bank_conflicts_pipe_lsu_mem_shared_op_st.sum,l1tex__data_pipe_lsu_wavefronts_mem_shared.sum,l1tex__data_pipe_lsu_wavefronts_mem_shared.sum.pct_of_peak_sustained_elapsed,l1tex__data_pipe_lsu_wavefronts_mem_shared_op_atom.sum,l1tex__data_pipe_lsu_wavefronts_mem_shared_op_atom.sum.pct_of_peak_sustained_elapsed,l1tex__data_pipe_lsu_wavefronts_mem_shared_op_ld.sum,l1tex__data_pipe_lsu_wavefronts_mem_shared_op_ld.sum.pct_of_peak_sustained_elapsed,l1tex__data_pipe_lsu_wavefronts_mem_shared_op_st.sum,l1tex__data_pipe_lsu_wavefronts_mem_shared_op_st.sum.pct_of_peak_sustained_elapsed,smsp__inst_executed_op_ldgsts.sum,smsp__inst_executed_op_ldsm.sum,smsp__inst_executed_op_shared_atom.sum,smsp__sass_inst_executed_op_shared_ld.sum,smsp__sass_inst_executed_op_shared_st.sum,smsp__sass_l1tex_data_bank_conflicts_pipe_lsu_mem_shared_op_ldgsts.sum,smsp__sass_l1tex_data_bank_conflicts_pipe_lsu_mem_shared_op_st.sum,smsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_ldgsts.sum,smsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_ldgsts.sum.pct_of_peak_sustained_elapsed,smsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_st.sum,smsp__sass_l1tex_data_pipe_lsu_wavefronts_mem_shared_op_st.sum.pct_of_peak_sustained_elapsed j smsp__pcsamp_warps_issue_stalled_barrier,smsp__pcsamp_warps_issue_stalled_branch_resolving,smsp__pcsamp_warps_issue_stalled_dispatch_stall,smsp__pcsamp_warps_issue_stalled_drain,smsp__pcsamp_warps_issue_stalled_imc_miss,smsp__pcsamp_warps_issue_stalled_lg_throttle,smsp__pcsamp_warps_issue_stalled_long_scoreboard,smsp__pcsamp_warps_issue_stalled_math_pipe_throttle,smsp__pcsamp_warps_issue_stalled_membar,smsp__pcsamp_warps_issue_stalled_mio_throttle,smsp__pcsamp_warps_issue_stalled_misc,smsp__pcsamp_warps_issue_stalled_no_instructions,smsp__pcsamp_warps_issue_stalled_not_selected,smsp__pcsamp_warps_issue_stalled_selected,smsp__pcsamp_warps_issue_stalled_short_scoreboard,smsp__pcsamp_warps_issue_stalled_sleeping,smsp__pcsamp_warps_issue_stalled_tex_throttle,smsp__pcsamp_warps_issue_stalled_wait j smsp__pcsamp_warps_issue_stalled_barrier_not_issued,smsp__pcsamp_warps_issue_stalled_branch_resolving_not_issued,smsp__pcsamp_warps_issue_stalled_dispatch_stall_not_issued,smsp__pcsamp_warps_issue_stalled_drain_not_issued,smsp__pcsamp_warps_issue_stalled_imc_miss_not_issued,smsp__pcsamp_warps_issue_stalled_lg_throttle_not_issued,smsp__pcsamp_warps_issue_stalled_long_scoreboard_not_issued,smsp__pcsamp_warps_issue_stalled_math_pipe_throttle_not_issued,smsp__pcsamp_warps_issue_stalled_membar_not_issued,smsp__pcsamp_warps_issue_stalled_mio_throttle_not_issued,smsp__pcsamp_warps_issue_stalled_misc_not_issued,smsp__pcsamp_warps_issue_stalled_no_instructions_not_issued,smsp__pcsamp_warps_issue_stalled_not_selected_not_issued,smsp__pcsamp_warps_issue_stalled_selected_not_issued,smsp__pcsamp_warps_issue_stalled_short_scoreboard_not_issued,smsp__pcsamp_warps_issue_stalled_sleeping_not_issued,smsp__pcsamp_warps_issue_stalled_tex_throttle_not_issued,smsp__pcsamp_warps_issue_stalled_wait_not_issued j ( j ( j ( j @ j @ j ( jO( (( (( (( (( (( (( (( jO( (( (( (( (( (( (( (( jc( ((d (( (( (( (( (( (( jV( ((> (( (( (( (( (( (( j ( ( FBSP.TriageSCG.dramc__read_throughput.avg.pct_of_peak_sustained_elapsed,FBSP.TriageSCG.dramc__throughput.avg.pct_of_peak_sustained_elapsed,FBSP.TriageSCG.dramc__write_throughput.avg.pct_of_peak_sustained_elapsed ( FE_B.TriageAC.gr__ctas_launched_queue_sync.sum,TriageAC.tpc__warps_active_realtime.avg.per_cycle_active,TriageAC.tpc__warps_active_realtime.sum.per_cycle_active ({ yLTS.TriageSCG.lts__average_t_sector_hit_rate_realtime.pct,LTS.TriageSCG.lts__throughput.avg.pct_of_peak_sustained_elapsed ( SM_A.TriageAC.l1tex__data_pipe_lsu_wavefronts.avg,SM_A.TriageAC.l1tex__lsu_writeback_active.avg,SM_A.TriageSCG.l1tex__throughput.avg.pct_of_peak_sustained_elapsedi (c aSM_A.TriageAC.sm__cycles_active.avg,SM_A.TriageAC.sm__inst_executed_realtime.avg.per_cycle_active ( SM_A.TriageSCG.sm__inst_executed_pipe_alu_realtime.avg.pct_of_peak_sustained_elapsed,SM_C.TriageSCG.smsp__inst_executed_pipe_fmaheavy.avg.pct_of_peak_sustained_elapsed,SM_C.TriageSCG.smsp__inst_executed_pipe_fmalite.avg.pct_of_peak_sustained_elapsed,TriageSCG.sm__throughput.avg.pct_of_peak_sustained_elapsed,pmsampling:sm__pipe_tensor_cycles_active_realtime.avg.pct_of_peak_sustained_elapsed2 (, *SM_B.TriageAC.l1tex__t_sector_hit_rate.pct j) ? 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'sm__inst_executed.avg.per_cycle_elapsedExecuted Ipc ElapsedF ;sm__instruction_throughput.avg.pct_of_peak_sustained_activeSM Busy= &sm__inst_executed.avg.per_cycle_activeExecuted Ipc ActiveD 0sm__inst_issued.avg.pct_of_peak_sustained_activeIssue Slots Busy9 $sm__inst_issued.avg.per_cycle_activeIssued Ipc Active * *  %Pipe Utilization (% of active cycles)" Utilization [%]d*B ;sm__pipe_alu_cycles_active.avg.pct_of_peak_sustained_activeALU*B ;sm__pipe_fma_cycles_active.avg.pct_of_peak_sustained_activeFMA*D sm__pipe_tensor_cycles_active.avg.pct_of_peak_sustained_active Tensor (All)*c Fsm__pipe_tensor_op_dmma_cycles_active.avg.pct_of_peak_sustained_active Tensor (DP)2 PPZZ*U Fsm__pipe_tensor_op_hmma_cycles_active.avg.pct_of_peak_sustained_active Tensor (FP)*Z Fsm__pipe_tensor_op_imma_cycles_active.avg.pct_of_peak_sustained_active Tensor (INT)2H* >sm__pipe_shared_cycles_active.avg.pct_of_peak_sustained_activeShared (FP64+FP16+Tensor)2FF:\ >sm__pipe_shared_cycles_active.avg.pct_of_peak_sustained_activeShared (FP16+Tensor)HK:d >sm__pipe_shared_cycles_active.avg.pct_of_peak_sustained_activeShared (FP64+Tensor) PPZZ*H ;sm__pipe_tma_cycles_active.avg.pct_of_peak_sustained_activeTMA2ZZ08@JPipeline utilization based on the number of cycles the pipeline was active. This takes the rates of different instructions executing on the pipeline into account. For an instruction requiring 4 cycles to complete execution, the counter is increased by 1 for 4 cycles.  2Pipe Utilization (% of peak instructions executed)" Utilization [%]d*B ;sm__inst_executed_pipe_adu.avg.pct_of_peak_sustained_activeADU*B ;sm__inst_executed_pipe_alu.avg.pct_of_peak_sustained_activeALU*B ;sm__inst_executed_pipe_cbu.avg.pct_of_peak_sustained_activeCBU*B ;sm__inst_executed_pipe_fma.avg.pct_of_peak_sustained_activeFMA* Table with NUMA IDs based on CPU affinity and memory affinity.2 , numa__dev_display_name_all Device Names  $ numa__cpu_affinity CPU Affinity  ) numa__id_cpuNUMA ID by CPU Affinity  / numa__id_memoryNUMA ID by Memory Affinity :_Non-uniform memory access (NUMA) affinities based on compute and memory distances for all GPUs.B fullZFFKVY Nvlink_Tables NVLink Tables>*O  Logical NVLink Properties  Logical NVLink Throughput NVLink Tables:0Detailed tables with properties for each NVLink.B fullB nvlinkJNvlink Nvlink_TopologyNVLink Topology=*)  NVLink TopologyNVLink Topology:ZNVLink Topology diagram shows logical NVLink connections with transmit/receive throughput.B fullB nvlinkJNvlink Occupancy OccupancyP"? &sm__maximum_warps_per_active_cycle_pctTheoretical Occupancy: !launch__occupancy_limit_registersBlock Limit RegistersI &sm__maximum_warps_avg_per_active_cycleTheoretical Active Warps per SM< "launch__occupancy_limit_shared_memBlock Limit Shared MemO 1sm__warps_active.avg.pct_of_peak_sustained_activeAchieved Occupancy2"2 launch__occupancy_limit_warpsBlock Limit WarpsM %sm__warps_active.avg.per_cycle_activeAchieved Active Warps Per SM2"0 launch__occupancy_limit_blocksBlock Limit SM: "launch__cluster_max_potential_sizeMax Cluster Size2Z5 launch__cluster_max_activeMax Active Clusters2Z6 launch__occupancy_cluster_pctCluster Occupancy2Z> !launch__occupancy_cluster_gpu_pctOverall GPU Occupancy2Z* " +Impact of Varying Register Count Per Thread Registers Per Thread!( Warp Occupancy("K $launch__occupancy_per_register_count!Warp Occupancy Per Register Count *6 4 launch__registers_per_threadRegisters Per Thread " Impact of Varying Block Size Block Size!( Warp Occupancy("C launch__occupancy_per_block_sizeWarp Occupancy Per Block Size *" launch__block_size Block Size " /Impact of Varying Shared Memory Usage Per Block! Shared Memory Per Block!( Warp Occupancy("M %launch__occupancy_per_shared_mem_size"Warp Occupancy Per Shared Mem Size *9 7 launch__shared_mem_per_blockShared Memory Per Block " Impact of Varying Cluster Size" Potential Cluster Size( Active Clusters("7 "launch__occupancy_per_cluster_sizeActive Clusters *& $ launch__cluster_size Cluster Size Z2 H %smsp__warps_active.avg.peak_sustainedGPU Maximum Warps Per Scheduler K (smsp__maximum_warps_avg_per_active_cycleTheoretical Warps Per Scheduler:Occupancy is the ratio of the number of active warps per multiprocessor to the maximum number of possible active warps. Another way to view occupancy is the percentage of the hardware's ability to process warps that is actively in use. Higher occupancy does not always result in higher performance, however, low occupancy always reduces the ability to hide latencies, resulting in overall performance degradation. Large discrepancies between the theoretical and the achieved occupancy during execution typically indicates highly imbalanced workloads.B basicB detailedB fullZ"- PmSampling PM Sampling*)  Compute"r"p ;TPC.TriageA.tpc__warps_active_realtime.avg.per_cycle_activeAverage Active Warps Per CycleJsampling_compute1"p"n ;TPC.TriageA.tpc__warps_active_realtime.sum.per_cycle_activeTotal Active Warps Per CycleJsampling_compute1"I"G SM.TriageA.sm__cycles_active.avgSM Active CyclesJsampling_compute1"f"d :SM.TriageA.sm__inst_executed_realtime.avg.per_cycle_activeExecuted Ipc ActiveJsampling_compute2 L1 Cache"V"T *SM.TriageA.l1tex__lsu_writeback_active.avgWriteback ThroughputJsampling_memory1"M"K -TriageA.l1tex__t_sector_hit_rate_realtime.pctHit RateJsampling_memory2"W"U .SM.TriageA.l1tex__data_pipe_lsu_wavefronts.avgWavefronts (Data)Jsampling_memory1 KK   Overview"H"F pmsampling:sm__ctas_launched.sumBlocks LaunchedJsampling_compute1"I"G pmsampling:sm__cycles_active.avgSM Active CyclesJsampling_compute1"f"d :pmsampling:sm__inst_executed_realtime.avg.per_cycle_activeExecuted Ipc ActiveJsampling_compute2 SM"m"k Gpmsampling:sm__inst_executed_realtime.avg.pct_of_peak_sustained_elapsed SM ThroughputJsampling_compute2""} Ppmsampling:sm__inst_executed_pipe_alu_realtime.avg.pct_of_peak_sustained_elapsedSM ALU Pipe ThroughputJsampling_compute2"" Spmsampling:sm__pipe_tensor_cycles_active_realtime.avg.pct_of_peak_sustained_elapsedSM Tensor Pipe ThroughputJsampling_compute2 DRAM"e"c >pmsampling:dramc__throughput.avg.pct_of_peak_sustained_elapsedDRAM ThroughputJsampling_memory5"o"m Cpmsampling:dramc__read_throughput.avg.pct_of_peak_sustained_elapsedDRAM Read ThroughputJsampling_memory5"q"o Dpmsampling:dramc__write_throughput.avg.pct_of_peak_sustained_elapsedDRAM Write ThroughputJsampling_memory5 L1 Cache"t"r Hpmsampling:l1tex__lsu_writeback_active.avg.pct_of_peak_sustained_elapsedWriteback ThroughputJsampling_memory1"G"E 'pmsampling:l1tex__t_sector_hit_rate.pctHit RateJsampling_memory3"W"U .pmsampling:l1tex__data_pipe_lsu_wavefronts.avgWavefronts (Data)Jsampling_memory4 PP  Overview"o"m 8TriageAC.tpc__warps_active_realtime.avg.per_cycle_activeAverage Active Warps Per CycleJsampling_compute1"m"k 8TriageAC.tpc__warps_active_realtime.sum.per_cycle_activeTotal Active Warps Per CycleJsampling_compute1"V"T .FE_B.TriageAC.gr__ctas_launched_queue_sync.sumBlocks LaunchedJsampling_compute1"L"J #SM_A.TriageAC.sm__cycles_active.avgSM Active CyclesJsampling_compute2"i"g =SM_A.TriageAC.sm__inst_executed_realtime.avg.per_cycle_activeExecuted Ipc ActiveJsampling_compute2 SM"`"^ :TriageSCG.sm__throughput.avg.pct_of_peak_sustained_elapsed SM ThroughputJsampling_compute3"" TSM_A.TriageSCG.sm__inst_executed_pipe_alu_realtime.avg.pct_of_peak_sustained_elapsedSM ALU Pipe ThroughputJsampling_compute3"" QSM_C.TriageSCG.smsp__inst_executed_pipe_fmalite.avg.pct_of_peak_sustained_elapsedSM FMA Light Pipe ThroughputJsampling_compute3"" RSM_C.TriageSCG.smsp__inst_executed_pipe_fmaheavy.avg.pct_of_peak_sustained_elapsedSM FMA Heavy Pipe ThroughputJsampling_compute3"" Spmsampling:sm__pipe_tensor_cycles_active_realtime.avg.pct_of_peak_sustained_elapsedSM Tensor Pipe ThroughputJsampling_compute3 DRAM"i"g BFBSP.TriageSCG.dramc__throughput.avg.pct_of_peak_sustained_elapsedDRAM ThroughputJsampling_memory3"r"p GFBSP.TriageSCG.dramc__read_throughput.avg.pct_of_peak_sustained_elapsedDRAM Read BandwidthJsampling_memory3"t"r HFBSP.TriageSCG.dramc__write_throughput.avg.pct_of_peak_sustained_elapsedDRAM Write BandwidthJsampling_memory3 L2 Cache"d"b ?LTS.TriageSCG.lts__throughput.avg.pct_of_peak_sustained_elapsed L2 ThroughputJsampling_memory4"\"Z 9LTS.TriageSCG.lts__average_t_sector_hit_rate_realtime.pct L2 Hit RateJsampling_memory4 L1 Cache"g"e BSM_A.TriageSCG.l1tex__throughput.avg.pct_of_peak_sustained_elapsed L1 ThroughputJsampling_memory1"Y"W -SM_A.TriageAC.l1tex__lsu_writeback_active.avgWriteback ThroughputJsampling_memory1"J"H *SM_B.TriageAC.l1tex__t_sector_hit_rate.pctHit RateJsampling_memory2"Z"X 1SM_A.TriageAC.l1tex__data_pipe_lsu_wavefronts.avgWavefronts (Data)Jsampling_memory1 VY   Overview"H"F pmsampling:sm__ctas_launched.sumBlocks LaunchedJsampling_compute1"I"G pmsampling:sm__cycles_active.avgSM Active CyclesJsampling_compute1"f"d :pmsampling:sm__inst_executed_realtime.avg.per_cycle_activeExecuted Ipc ActiveJsampling_compute2 SM"m"k Gpmsampling:sm__inst_executed_realtime.avg.pct_of_peak_sustained_elapsed SM ThroughputJsampling_compute2""} Ppmsampling:sm__inst_executed_pipe_alu_realtime.avg.pct_of_peak_sustained_elapsedSM ALU Pipe ThroughputJsampling_compute2"" Spmsampling:sm__pipe_tensor_cycles_active_realtime.avg.pct_of_peak_sustained_elapsedSM Tensor Pipe ThroughputJsampling_compute2 DRAM"e"c >pmsampling:dramc__throughput.avg.pct_of_peak_sustained_elapsedDRAM ThroughputJsampling_memory5"o"m Cpmsampling:dramc__read_throughput.avg.pct_of_peak_sustained_elapsedDRAM Read ThroughputJsampling_memory5"q"o Dpmsampling:dramc__write_throughput.avg.pct_of_peak_sustained_elapsedDRAM Write ThroughputJsampling_memory5 L1 Cache"G"E 'pmsampling:l1tex__t_sector_hit_rate.pctHit RateJsampling_memory3"W"U .pmsampling:l1tex__data_pipe_lsu_wavefronts.avgWavefronts (Data)Jsampling_memory4 ZZ:Timeline view of PM metrics sampled periodically over the workload duration. Data is collected across multiple passes. Use this section to understand workload behavior changes over its runtime.B fullb sampling_compute1b sampling_compute2b sampling_compute3b sampling_compute4b sampling_memory1b sampling_memory2b sampling_memory3b sampling_memory4b sampling_memory5b sampling_memory6b sampling_memory7 SchedulerStatsScheduler Statistics("E 'smsp__warps_active.avg.per_cycle_activeActive Warps Per SchedulerA 2smsp__issue_inst0.avg.pct_of_peak_sustained_active No EligibleI )smsp__warps_eligible.avg.per_cycle_activeEligible Warps Per SchedulerK 3smsp__issue_active.avg.pct_of_peak_sustained_activeOne or More EligibleD 'smsp__issue_active.avg.per_cycle_activeIssued Warp Per Scheduler *  Warps Per Scheduler"*H %smsp__warps_active.avg.peak_sustainedGPU Maximum Warps Per Scheduler*K (smsp__maximum_warps_avg_per_active_cycleTheoretical Warps Per Scheduler*E 'smsp__warps_active.avg.per_cycle_activeActive Warps Per Scheduler*I )smsp__warps_eligible.avg.per_cycle_activeEligible Warps Per Scheduler*D 'smsp__issue_active.avg.per_cycle_activeIssued Warp Per Scheduler2Q O %smsp__warps_active.avg.peak_sustained&Theoretical Active Warps Per Scheduler:Summary of the activity of the schedulers issuing instructions. Each scheduler maintains a pool of warps that it can issue instructions for. The upper bound of warps in the pool (Theoretical Warps) is limited by the launch configuration. On every cycle each scheduler checks the state of the allocated warps in the pool (Active Warps). Active warps that are not stalled (Eligible Warps) are ready to issue their next instruction. From the set of eligible warps the scheduler selects a single warp from which to issue one or more instructions (Issued Warp). On cycles with no eligible warps, the issue slot is skipped and no instruction is issued. Having many skipped issue slots indicates poor latency hiding.B full@ SourceCountersSource Countersd"8 !smsp__inst_executed_op_branch.sumBranch InstructionsP 5smsp__sass_average_branch_targets_threads_uniform.pctBranch Efficiency2"G *derived__smsp__inst_executed_op_branch_pctBranch Instructions RatioP /smsp__sass_branch_targets_threads_divergent.avgAvg. Divergent Branches2"* * N:L !Warp Stall Sampling (All Samples)' %group:smsp__pcsamp_warp_stall_reasons M:D Most Instructions Executed& inst_executedInstructions Executed "Hotspot Locations:Source metrics, including branch efficiency and sampled warp stall reasons. Warp Stall Sampling metrics are periodically sampled over the kernel runtime. They indicate when warps were stalled and couldn't be scheduled. See the documentation for a description of all stall reasons. Only focus on stalls if the schedulers fail to issue every cycle.B detailedB fullR D derived__avg_thread_executed$thread_inst_executed / inst_executed N !derived__avg_thread_executed_true)thread_inst_executed_true / inst_executed  7derived__memory_l2_theoretical_sectors_global_excessiveQmemory_l2_theoretical_sectors_global - memory_l2_theoretical_sectors_global_ideal q .derived__memory_l1_wavefronts_shared_excessive?memory_l1_wavefronts_shared - memory_l1_wavefronts_shared_ideal W (derived__memory_l1_conflicts_shared_nway+memory_l1_wavefronts_shared / inst_executed i *derived__smsp__inst_executed_op_branch_pct;smsp__inst_executed_op_branch.sum / smsp__inst_executed.sumb2 group_inst_executedInstructions Executedb* group_memory_access Memory Accessb group_l1L1 Cacheb group_l2L2 Cacheb; group_warp_stall_aggregatedWarp Stalls Aggregatedb$ group_warp_stall Warp Stallb= group_warp_stall_not_issuedWarp Stalls (Not Issued)j2 g %group:smsp__pcsamp_warp_stall_reasons!Warp Stall Sampling (All Samples)Jgroup_warp_stall_aggregated  0group:smsp__pcsamp_warp_stall_reasons_not_issued(Warp Stall Sampling (Not-issued Samples)BJgroup_warp_stall_aggregated I smsp__pcsamp_sample_count # SamplesBJgroup_warp_stall_aggregated G inst_executedInstructions Executed2"BJgroup_inst_executed O thread_inst_executedThread Instructions Executed2"Jgroup_inst_executed b thread_inst_executed_true*Predicated-On Thread Instructions Executed2"Jgroup_inst_executed T derived__avg_thread_executedAvg. Threads ExecutedB Jgroup_inst_executed g !derived__avg_thread_executed_true#Avg. Predicated-On Threads ExecutedB Jgroup_inst_executed W &smsp__branch_targets_threads_divergentDivergent Branches2"Jgroup_inst_executed 7 memory_type Address Space2"Jgroup_memory_access A memory_access_typeAccess Operation2"Jgroup_memory_access A memory_access_size_type Access Size2"Jgroup_memory_access , l1tex__cycles_active.sumL1 Active Cycles . l1tex__cycles_elapsed.sumL1 Elapsed Cycles G memory_l1_tag_requests_globalL1 Tag Requests Global2"Jgroup_l1 U (derived__memory_l1_conflicts_shared_nwayL1 Conflicts Shared N-WayBJgroup_l1 ` .derived__memory_l1_wavefronts_shared_excessiveL1 Wavefronts Shared ExcessiveBJgroup_l1 C memory_l1_wavefronts_sharedL1 Wavefronts Shared2"Jgroup_l1 O !memory_l1_wavefronts_shared_idealL1 Wavefronts Shared Ideal2"Jgroup_l1 * lts__cycles_active.sumL2 Active Cycles , lts__cycles_elapsed.sumL2 Elapsed Cycles r 7derived__memory_l2_theoretical_sectors_global_excessive'L2 Theoretical Sectors Global ExcessiveBJgroup_l2 U $memory_l2_theoretical_sectors_globalL2 Theoretical Sectors Global2"Jgroup_l2 a *memory_l2_theoretical_sectors_global_ideal#L2 Theoretical Sectors Global Ideal2"Jgroup_l2 S #memory_l2_theoretical_sectors_localL2 Theoretical Sectors Local2"Jgroup_l2 d 4smsp__sass_inst_executed_memdesc_explicit_evict_typeL2 Explicit Evict Policies2P"Jgroup_l2 u =smsp__sass_inst_executed_memdesc_explicit_hitprop_evict_first"L2 Explicit Hit Policy Evict First2P"Jgroup_l2 s smsp__sass_inst_executed_memdesc_explicit_hitprop_evict_normal#L2 Explicit Hit Policy Evict Normal2P"Jgroup_l2  Esmsp__sass_inst_executed_memdesc_explicit_hitprop_evict_normal_demote*L2 Explicit Hit Policy Evict Normal Demote2P"Jgroup_l2 w >smsp__sass_inst_executed_memdesc_explicit_missprop_evict_first#L2 Explicit Miss Policy Evict First2P"Jgroup_l2 y ?smsp__sass_inst_executed_memdesc_explicit_missprop_evict_normal$L2 Explicit Miss Policy Evict Normal2P"Jgroup_l2 K (smsp__pcsamp_warps_issue_stalled_barrier stall_barrierJgroup_warp_stall ] 1smsp__pcsamp_warps_issue_stalled_branch_resolvingstall_branch_resolvingJgroup_warp_stall S /smsp__pcsamp_warps_issue_stalled_dispatch_stallstall_dispatchJgroup_warp_stall G &smsp__pcsamp_warps_issue_stalled_drain stall_drainJgroup_warp_stall H )smsp__pcsamp_warps_issue_stalled_imc_miss stall_imcJgroup_warp_stall J ,smsp__pcsamp_warps_issue_stalled_lg_throttlestall_lgJgroup_warp_stall S 0smsp__pcsamp_warps_issue_stalled_long_scoreboard stall_long_sbJgroup_warp_stall S 3smsp__pcsamp_warps_issue_stalled_math_pipe_throttle stall_mathJgroup_warp_stall I 'smsp__pcsamp_warps_issue_stalled_membar stall_membarJgroup_warp_stall L -smsp__pcsamp_warps_issue_stalled_mio_throttle stall_mioJgroup_warp_stall E %smsp__pcsamp_warps_issue_stalled_misc stall_miscJgroup_warp_stall S 0smsp__pcsamp_warps_issue_stalled_no_instructions stall_no_instJgroup_warp_stall U -smsp__pcsamp_warps_issue_stalled_not_selectedstall_not_selectedJgroup_warp_stall M )smsp__pcsamp_warps_issue_stalled_selectedstall_selectedJgroup_warp_stall U 1smsp__pcsamp_warps_issue_stalled_short_scoreboardstall_short_sbJgroup_warp_stall J )smsp__pcsamp_warps_issue_stalled_sleeping stall_sleepJgroup_warp_stall L -smsp__pcsamp_warps_issue_stalled_tex_throttle stall_texJgroup_warp_stall E %smsp__pcsamp_warps_issue_stalled_wait stall_waitJgroup_warp_stall n 3smsp__pcsamp_warps_issue_stalled_barrier_not_issuedstall_barrier (Not Issued)Jgroup_warp_stall_not_issued  smsp__pcsamp_warps_issue_stalled_math_pipe_throttle_not_issuedstall_math (Not Issued)Jgroup_warp_stall_not_issued l 2smsp__pcsamp_warps_issue_stalled_membar_not_issuedstall_membar (Not Issued)Jgroup_warp_stall_not_issued o 8smsp__pcsamp_warps_issue_stalled_mio_throttle_not_issuedstall_mio (Not Issued)Jgroup_warp_stall_not_issued h 0smsp__pcsamp_warps_issue_stalled_misc_not_issuedstall_misc (Not Issued)Jgroup_warp_stall_not_issued v ;smsp__pcsamp_warps_issue_stalled_no_instructions_not_issuedstall_no_inst (Not Issued)Jgroup_warp_stall_not_issued x 8smsp__pcsamp_warps_issue_stalled_not_selected_not_issuedstall_not_selected (Not Issued)Jgroup_warp_stall_not_issued p 4smsp__pcsamp_warps_issue_stalled_selected_not_issuedstall_selected (Not Issued)Jgroup_warp_stall_not_issued x 6gpu__dram_throughput.avg.pct_of_peak_sustained_elapsedKV:< 6gpu__dram_throughput.avg.pct_of_peak_sustained_elapsedY #dram__cycles_elapsed.avg.per_secondDRAM Frequency2F:+ #dram__cycles_elapsed.avg.per_secondKV:) #dram__cycles_elapsed.avg.per_secondY*  GPU Throughput"" Speed Of Light (SOL) [%]d *D 0sm__throughput.avg.pct_of_peak_sustained_elapsedCompute (SM) [%]*N @gpu__compute_memory_throughput.avg.pct_of_peak_sustained_elapsed Memory [%]GPU Throughput Chart* * } { Compute Throughput Breakdown*U :breakdown:sm__throughput.avg.pct_of_peak_sustained_elapsed{UNIT}: {COMPOUND_NAME}08   Memory Throughput Breakdown*e Jbreakdown:gpu__compute_memory_throughput.avg.pct_of_peak_sustained_elapsed{UNIT}: {COMPOUND_NAME}08GPU Throughput Breakdown28 6 launch__waves_per_multiprocessor Waves Per SM2":High-level overview of the throughput for compute and memory resources of the GPU. For each unit, the throughput reports the achieved percentage of utilization with respect to the theoretical maximum. Breakdowns show the throughput for each individual sub-metric of Compute and Memory to clearly identify the highest contributor.B basicB detailedB fullB roofline SpeedOfLight_RooflineChart!GPU Speed Of Light Roofline Chart * 2 "Floating Point Operations Roofline" Arithmetic Intensity [FLOP/byte] Performance [FLOP/s]"  f 9derived__sm__sass_thread_inst_executed_op_ffma_pred_on_x2)Theoretical Predicated-On FFMA Operations1 !sm__cycles_elapsed.avg.per_second SM Frequency  dram__bytes.sum.peak_sustained!Theoretical DRAM Bytes Accessible2F:& dram__bytes.sum.peak_sustainedKV:$ dram__bytes.sum.peak_sustainedY #dram__cycles_elapsed.avg.per_secondDRAM Frequency2F:+ #dram__cycles_elapsed.avg.per_secondKV:) #dram__cycles_elapsed.avg.per_secondY Single Precision Roofline"  f 9derived__sm__sass_thread_inst_executed_op_dfma_pred_on_x2)Theoretical Predicated-On DFMA Operations1 !sm__cycles_elapsed.avg.per_second SM Frequency  dram__bytes.sum.peak_sustained!Theoretical DRAM Bytes Accessible2F:& dram__bytes.sum.peak_sustainedKV:$ dram__bytes.sum.peak_sustainedY #dram__cycles_elapsed.avg.per_secondDRAM Frequency2F:+ #dram__cycles_elapsed.avg.per_secondKV:) #dram__cycles_elapsed.avg.per_secondY Double Precision Roofline*   Esmsp__sass_thread_inst_executed_op_fadd_pred_on.sum.per_cycle_elapsed9Predicated-On FADD Thread Instructions Executed Per Cycle  Esmsp__sass_thread_inst_executed_op_fmul_pred_on.sum.per_cycle_elapsed9Predicated-On FMUL Thread Instructions Executed Per Cycle f ;derived__smsp__sass_thread_inst_executed_op_ffma_pred_on_x2'Predicated-On FFMA Operations Per Cycle3 #smsp__cycles_elapsed.avg.per_second SM Frequencyxv dram__bytes.sum.per_secondDRAM Bandwidth2F:" dram__bytes.sum.per_secondKV: dram__bytes.sum.per_secondY! Single Precision Achieved Value*   Esmsp__sass_thread_inst_executed_op_dadd_pred_on.sum.per_cycle_elapsed9Predicated-On DADD Thread Instructions Executed Per Cycle  Esmsp__sass_thread_inst_executed_op_dmul_pred_on.sum.per_cycle_elapsed9Predicated-On DMUL Thread Instructions Executed Per Cycle f ;derived__smsp__sass_thread_inst_executed_op_dfma_pred_on_x2'Predicated-On DFMA Operations Per Cycle3 #smsp__cycles_elapsed.avg.per_second SM Frequencyxv dram__bytes.sum.per_secondDRAM Bandwidth2F:" dram__bytes.sum.per_secondKV: dram__bytes.sum.per_secondY! Double Precision Achieved ValueGPU Throughput Rooflines2  @sm__sass_thread_inst_executed_op_ffma_pred_on.sum.peak_sustained;Theoretical Predicated-On FFMA Thread Instructions Executed  @sm__sass_thread_inst_executed_op_dfma_pred_on.sum.peak_sustained;Theoretical Predicated-On DFMA Thread Instructions Executed  Esmsp__sass_thread_inst_executed_op_ffma_pred_on.sum.per_cycle_elapsed9Predicated-On FFMA Thread Instructions Executed Per Cycle  Esmsp__sass_thread_inst_executed_op_dfma_pred_on.sum.per_cycle_elapsed9Predicated-On DFMA Thread Instructions Executed Per Cycle:qHigh-level overview of the utilization for compute and memory resources of the GPU presented as a roofline chart.B detailedB fullB rooflineJ SpeedOfLightR  9derived__sm__sass_thread_inst_executed_op_ffma_pred_on_x2Dsm__sass_thread_inst_executed_op_ffma_pred_on.sum.peak_sustained * 2  9derived__sm__sass_thread_inst_executed_op_dfma_pred_on_x2Dsm__sass_thread_inst_executed_op_dfma_pred_on.sum.peak_sustained * 2  ;derived__smsp__sass_thread_inst_executed_op_ffma_pred_on_x2Ismsp__sass_thread_inst_executed_op_ffma_pred_on.sum.per_cycle_elapsed * 2  ;derived__smsp__sass_thread_inst_executed_op_dfma_pred_on_x2Ismsp__sass_thread_inst_executed_op_dfma_pred_on.sum.per_cycle_elapsed * 2Z" WarpStateStatsWarp State Statistics2"V 0smsp__average_warp_latency_per_inst_issued.ratio"Warp Cycles Per Issued InstructionR 2smsp__thread_inst_executed_per_inst_executed.ratioAvg. Active Threads Per WarpZ 2smsp__average_warps_active_per_inst_executed.ratio$Warp Cycles Per Executed Instructionf :smsp__thread_inst_executed_pred_on_per_inst_executed.ratio(Avg. Not Predicated Off Threads Per Warp*  Warp State (All Cycles) Warp States" Cycles per Instruction*M >smsp__average_warps_issue_stalled_drain_per_issue_active.ratio Stall Drain*S Asmsp__average_warps_issue_stalled_imc_miss_per_issue_active.ratioStall IMC Miss*Q @smsp__average_warps_issue_stalled_barrier_per_issue_active.ratio Stall Barrier*O =smsp__average_warps_issue_stalled_gmma_per_issue_active.ratio Stall GMMA2Z*c Ismsp__average_warps_issue_stalled_branch_resolving_per_issue_active.ratioStall Branch Resolving*O ?smsp__average_warps_issue_stalled_membar_per_issue_active.ratio Stall Membar*c Ismsp__average_warps_issue_stalled_short_scoreboard_per_issue_active.ratioStall Short Scoreboard*S Asmsp__average_warps_issue_stalled_sleeping_per_issue_active.ratioStall Sleeping*K =smsp__average_warps_issue_stalled_wait_per_issue_active.ratio Stall Wait*_ Gsmsp__average_warps_issue_stalled_no_instruction_per_issue_active.ratioStall No Instruction*g Ksmsp__average_warps_issue_stalled_math_pipe_throttle_per_issue_active.ratioStall Math Pipe Throttle*[ Esmsp__average_warps_issue_stalled_tex_throttle_per_issue_active.ratioStall Tex Throttle*Y Dsmsp__average_warps_issue_stalled_lg_throttle_per_issue_active.ratioStall LG Throttle*_ Gsmsp__average_warps_issue_stalled_dispatch_stall_per_issue_active.ratioStall Dispatch Stall*K =smsp__average_warps_issue_stalled_misc_per_issue_active.ratio Stall Misc*[ Esmsp__average_warps_issue_stalled_not_selected_per_issue_active.ratioStall Not Selected*M Asmsp__average_warps_issue_stalled_selected_per_issue_active.ratioSelected*a Hsmsp__average_warps_issue_stalled_long_scoreboard_per_issue_active.ratioStall Long Scoreboard*[ Esmsp__average_warps_issue_stalled_mio_throttle_per_issue_active.ratioStall MIO Throttle08@2F D 'smsp__issue_active.avg.per_cycle_activeIssued Warp Per Scheduler:Analysis of the states in which all warps spent cycles during the kernel execution. The warp states describe a warp's readiness or inability to issue its next instruction. The warp cycles per instruction define the latency between two consecutive instructions. The higher the value, the more warp parallelism is required to hide this latency. For each warp state, the chart shows the average number of cycles spent in that state per issued instruction. Stalls are not always impacting the overall performance nor are they completely avoidable. Only focus on stall reasons if the schedulers fail to issue every cycle. When executing a kernel with mixed library and user code, these metrics show the combined values.B full SOLBottleneck Bottleneck   The kernel is utilizing greater than 80.0% of the available compute or memory performance of the device. To further improve performance, work will likely need to be shifted from the most utilized to another unit. Start by analyzing DRAM in the @section:MemoryWorkloadAnalysis:Memory Workload Analysis@ section."High Throughput" SpeedOfLight+ ComputeCompute Bottleneck" SpeedOfLight IssueSlotUtilizationIssue Slot Utilization   Every scheduler is capable of issuing one instruction per cycle, but for this kernel each scheduler only issues an instruction every 9.8 cycles. This might leave hardware resources underutilized and may lead to less optimal performance. Out of the maximum of 12 warps per scheduler, this kernel allocates an average of 11.39 active warps per scheduler, but only an average of 0.14 warps were eligible per cycle. Eligible warps are the subset of active warps that are ready to issue their next instruction. Every cycle with no eligible warp results in no instruction being issued and the issue slot remains unused. To increase the number of eligible warps, avoid possible load imbalances due to highly different execution durations per warp. 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